[llvm-branch-commits] [llvm-branch] r85267 - in /llvm/branches/Apple/Leela: include/llvm/Target/ lib/CodeGen/ lib/Target/ARM/ test/CodeGen/ARM/ test/CodeGen/Thumb2/ test/CodeGen/X86/
Bill Wendling
isanbard at gmail.com
Tue Oct 27 11:37:23 PDT 2009
Author: void
Date: Tue Oct 27 13:37:21 2009
New Revision: 85267
URL: http://llvm.org/viewvc/llvm-project?rev=85267&view=rev
Log:
$ svn merge -c 84978 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r84978 into '.':
U include/llvm/Target/TargetInstrInfo.h
U lib/CodeGen/SimpleRegisterCoalescing.cpp
$ svn merge -c 84983 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r84983 into '.':
U lib/CodeGen/LowerSubregs.cpp
$ svn merge -c 85044 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r85044 into '.':
G include/llvm/Target/TargetInstrInfo.h
$ svn merge -c 85045 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r85045 into '.':
G lib/CodeGen/SimpleRegisterCoalescing.cpp
$ svn merge -c 85046 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r85046 into '.':
G lib/CodeGen/LowerSubregs.cpp
$ svn merge -c 85047 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r85047 into '.':
U lib/CodeGen/VirtRegRewriter.cpp
$ svn merge -c 85048 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r85048 into '.':
U lib/Target/ARM/ARMBaseInstrInfo.cpp
$ svn merge -c 85049 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r85049 into '.':
U lib/Target/ARM/ARMBaseRegisterInfo.h
U lib/Target/ARM/ARMBaseRegisterInfo.cpp
$ svn merge -c 85050 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r85050 into '.':
U test/CodeGen/ARM/fnmacs.ll
U test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug.ll
$ svn merge -c 85051 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r85051 into '.':
A test/CodeGen/Thumb2/cross-rc-coalescing-2.ll
A test/CodeGen/Thumb2/cross-rc-coalescing-1.ll
$ svn merge -c 85091 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r85091 into '.':
A test/CodeGen/X86/2009-10-25-RewriterBug.ll
G include/llvm/Target/TargetInstrInfo.h
U lib/CodeGen/RegisterScavenging.cpp
G lib/CodeGen/VirtRegRewriter.cpp
G lib/CodeGen/SimpleRegisterCoalescing.cpp
Added:
llvm/branches/Apple/Leela/test/CodeGen/Thumb2/cross-rc-coalescing-1.ll
- copied unchanged from r85051, llvm/trunk/test/CodeGen/Thumb2/cross-rc-coalescing-1.ll
llvm/branches/Apple/Leela/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll
- copied unchanged from r85051, llvm/trunk/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll
llvm/branches/Apple/Leela/test/CodeGen/X86/2009-10-25-RewriterBug.ll
- copied unchanged from r85091, llvm/trunk/test/CodeGen/X86/2009-10-25-RewriterBug.ll
Modified:
llvm/branches/Apple/Leela/include/llvm/Target/TargetInstrInfo.h
llvm/branches/Apple/Leela/lib/CodeGen/LowerSubregs.cpp
llvm/branches/Apple/Leela/lib/CodeGen/RegisterScavenging.cpp
llvm/branches/Apple/Leela/lib/CodeGen/SimpleRegisterCoalescing.cpp
llvm/branches/Apple/Leela/lib/CodeGen/VirtRegRewriter.cpp
llvm/branches/Apple/Leela/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm/branches/Apple/Leela/lib/Target/ARM/ARMBaseRegisterInfo.cpp
llvm/branches/Apple/Leela/lib/Target/ARM/ARMBaseRegisterInfo.h
llvm/branches/Apple/Leela/test/CodeGen/ARM/fnmacs.ll
llvm/branches/Apple/Leela/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug.ll
Modified: llvm/branches/Apple/Leela/include/llvm/Target/TargetInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/include/llvm/Target/TargetInstrInfo.h?rev=85267&r1=85266&r2=85267&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/include/llvm/Target/TargetInstrInfo.h (original)
+++ llvm/branches/Apple/Leela/include/llvm/Target/TargetInstrInfo.h Tue Oct 27 13:37:21 2009
@@ -133,13 +133,34 @@
AliasAnalysis *AA) const;
public:
- /// Return true if the instruction is a register to register move and return
- /// the source and dest operands and their sub-register indices by reference.
+ /// isMoveInstr - Return true if the instruction is a register to register
+ /// move and return the source and dest operands and their sub-register
+ /// indices by reference.
virtual bool isMoveInstr(const MachineInstr& MI,
unsigned& SrcReg, unsigned& DstReg,
unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
return false;
}
+
+ /// isIdentityCopy - Return true if the instruction is a copy (or
+ /// extract_subreg, insert_subreg, subreg_to_reg) where the source and
+ /// destination registers are the same.
+ bool isIdentityCopy(const MachineInstr &MI) const {
+ unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
+ if (isMoveInstr(MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
+ SrcReg == DstReg)
+ return true;
+
+ if (MI.getOpcode() == TargetInstrInfo::EXTRACT_SUBREG &&
+ MI.getOperand(0).getReg() == MI.getOperand(1).getReg())
+ return true;
+
+ if ((MI.getOpcode() == TargetInstrInfo::INSERT_SUBREG ||
+ MI.getOpcode() == TargetInstrInfo::SUBREG_TO_REG) &&
+ MI.getOperand(0).getReg() == MI.getOperand(2).getReg())
+ return true;
+ return false;
+ }
/// isLoadFromStackSlot - If the specified machine instruction is a direct
/// load from a stack slot, return the virtual or physical register number of
Modified: llvm/branches/Apple/Leela/lib/CodeGen/LowerSubregs.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/CodeGen/LowerSubregs.cpp?rev=85267&r1=85266&r2=85267&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/CodeGen/LowerSubregs.cpp (original)
+++ llvm/branches/Apple/Leela/lib/CodeGen/LowerSubregs.cpp Tue Oct 27 13:37:21 2009
@@ -32,6 +32,11 @@
namespace {
struct VISIBILITY_HIDDEN LowerSubregsInstructionPass
: public MachineFunctionPass {
+ private:
+ const TargetRegisterInfo *TRI;
+ const TargetInstrInfo *TII;
+
+ public:
static char ID; // Pass identification, replacement for typeid
LowerSubregsInstructionPass() : MachineFunctionPass(&ID) {}
@@ -48,15 +53,16 @@
/// runOnMachineFunction - pass entry point
bool runOnMachineFunction(MachineFunction&);
-
+
+ private:
bool LowerExtract(MachineInstr *MI);
bool LowerInsert(MachineInstr *MI);
bool LowerSubregToReg(MachineInstr *MI);
void TransferDeadFlag(MachineInstr *MI, unsigned DstReg,
- const TargetRegisterInfo &TRI);
+ const TargetRegisterInfo *TRI);
void TransferKillFlag(MachineInstr *MI, unsigned SrcReg,
- const TargetRegisterInfo &TRI,
+ const TargetRegisterInfo *TRI,
bool AddIfNotFound = false);
};
@@ -73,10 +79,10 @@
void
LowerSubregsInstructionPass::TransferDeadFlag(MachineInstr *MI,
unsigned DstReg,
- const TargetRegisterInfo &TRI) {
+ const TargetRegisterInfo *TRI) {
for (MachineBasicBlock::iterator MII =
prior(MachineBasicBlock::iterator(MI)); ; --MII) {
- if (MII->addRegisterDead(DstReg, &TRI))
+ if (MII->addRegisterDead(DstReg, TRI))
break;
assert(MII != MI->getParent()->begin() &&
"copyRegToReg output doesn't reference destination register!");
@@ -89,11 +95,11 @@
void
LowerSubregsInstructionPass::TransferKillFlag(MachineInstr *MI,
unsigned SrcReg,
- const TargetRegisterInfo &TRI,
+ const TargetRegisterInfo *TRI,
bool AddIfNotFound) {
for (MachineBasicBlock::iterator MII =
prior(MachineBasicBlock::iterator(MI)); ; --MII) {
- if (MII->addRegisterKilled(SrcReg, &TRI, AddIfNotFound))
+ if (MII->addRegisterKilled(SrcReg, TRI, AddIfNotFound))
break;
assert(MII != MI->getParent()->begin() &&
"copyRegToReg output doesn't reference source register!");
@@ -102,9 +108,6 @@
bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) {
MachineBasicBlock *MBB = MI->getParent();
- MachineFunction &MF = *MBB->getParent();
- const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo();
- const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
assert(MI->getOperand(0).isReg() && MI->getOperand(0).isDef() &&
MI->getOperand(1).isReg() && MI->getOperand(1).isUse() &&
@@ -113,7 +116,7 @@
unsigned DstReg = MI->getOperand(0).getReg();
unsigned SuperReg = MI->getOperand(1).getReg();
unsigned SubIdx = MI->getOperand(2).getImm();
- unsigned SrcReg = TRI.getSubReg(SuperReg, SubIdx);
+ unsigned SrcReg = TRI->getSubReg(SuperReg, SubIdx);
assert(TargetRegisterInfo::isPhysicalRegister(SuperReg) &&
"Extract supperg source must be a physical register");
@@ -128,7 +131,7 @@
if (MI->getOperand(1).isKill()) {
// We must make sure the super-register gets killed. Replace the
// instruction with KILL.
- MI->setDesc(TII.get(TargetInstrInfo::KILL));
+ MI->setDesc(TII->get(TargetInstrInfo::KILL));
MI->RemoveOperand(2); // SubIdx
DEBUG(errs() << "subreg: replace by: " << *MI);
return true;
@@ -137,9 +140,9 @@
DEBUG(errs() << "subreg: eliminated!");
} else {
// Insert copy
- const TargetRegisterClass *TRCS = TRI.getPhysicalRegisterRegClass(DstReg);
- const TargetRegisterClass *TRCD = TRI.getPhysicalRegisterRegClass(SrcReg);
- bool Emitted = TII.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRCD, TRCS);
+ const TargetRegisterClass *TRCS = TRI->getPhysicalRegisterRegClass(DstReg);
+ const TargetRegisterClass *TRCD = TRI->getPhysicalRegisterRegClass(SrcReg);
+ bool Emitted = TII->copyRegToReg(*MBB, MI, DstReg, SrcReg, TRCD, TRCS);
(void)Emitted;
assert(Emitted && "Subreg and Dst must be of compatible register class");
// Transfer the kill/dead flags, if needed.
@@ -160,9 +163,6 @@
bool LowerSubregsInstructionPass::LowerSubregToReg(MachineInstr *MI) {
MachineBasicBlock *MBB = MI->getParent();
- MachineFunction &MF = *MBB->getParent();
- const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo();
- const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
MI->getOperand(1).isImm() &&
(MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&
@@ -174,7 +174,7 @@
unsigned SubIdx = MI->getOperand(3).getImm();
assert(SubIdx != 0 && "Invalid index for insert_subreg");
- unsigned DstSubReg = TRI.getSubReg(DstReg, SubIdx);
+ unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx);
assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
"Insert destination must be in a physical register");
@@ -193,9 +193,11 @@
DEBUG(errs() << "subreg: eliminated!");
} else {
// Insert sub-register copy
- const TargetRegisterClass *TRC0= TRI.getPhysicalRegisterRegClass(DstSubReg);
- const TargetRegisterClass *TRC1= TRI.getPhysicalRegisterRegClass(InsReg);
- TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1);
+ const TargetRegisterClass *TRC0= TRI->getPhysicalRegisterRegClass(DstSubReg);
+ const TargetRegisterClass *TRC1= TRI->getPhysicalRegisterRegClass(InsReg);
+ bool Emitted = TII->copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1);
+ (void)Emitted;
+ assert(Emitted && "Subreg and Dst must be of compatible register class");
// Transfer the kill/dead flags, if needed.
if (MI->getOperand(0).isDead())
TransferDeadFlag(MI, DstSubReg, TRI);
@@ -209,14 +211,11 @@
DEBUG(errs() << '\n');
MBB->erase(MI);
- return true;
+ return true;
}
bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
MachineBasicBlock *MBB = MI->getParent();
- MachineFunction &MF = *MBB->getParent();
- const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo();
- const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
(MI->getOperand(1).isReg() && MI->getOperand(1).isUse()) &&
(MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&
@@ -231,7 +230,7 @@
assert(DstReg == SrcReg && "insert_subreg not a two-address instruction?");
assert(SubIdx != 0 && "Invalid index for insert_subreg");
- unsigned DstSubReg = TRI.getSubReg(DstReg, SubIdx);
+ unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx);
assert(DstSubReg && "invalid subregister index for register");
assert(TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
"Insert superreg source must be in a physical register");
@@ -245,7 +244,7 @@
// <undef>, we need to make sure it is alive by inserting a KILL
if (MI->getOperand(1).isUndef() && !MI->getOperand(0).isDead()) {
MachineInstrBuilder MIB = BuildMI(*MBB, MI, MI->getDebugLoc(),
- TII.get(TargetInstrInfo::KILL), DstReg);
+ TII->get(TargetInstrInfo::KILL), DstReg);
if (MI->getOperand(2).isUndef())
MIB.addReg(InsReg, RegState::Undef);
else
@@ -257,15 +256,18 @@
}
} else {
// Insert sub-register copy
- const TargetRegisterClass *TRC0= TRI.getPhysicalRegisterRegClass(DstSubReg);
- const TargetRegisterClass *TRC1= TRI.getPhysicalRegisterRegClass(InsReg);
+ const TargetRegisterClass *TRC0= TRI->getPhysicalRegisterRegClass(DstSubReg);
+ const TargetRegisterClass *TRC1= TRI->getPhysicalRegisterRegClass(InsReg);
if (MI->getOperand(2).isUndef())
// If the source register being inserted is undef, then this becomes a
// KILL.
BuildMI(*MBB, MI, MI->getDebugLoc(),
- TII.get(TargetInstrInfo::KILL), DstSubReg);
- else
- TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1);
+ TII->get(TargetInstrInfo::KILL), DstSubReg);
+ else {
+ bool Emitted = TII->copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1);
+ (void)Emitted;
+ assert(Emitted && "Subreg and Dst must be of compatible register class");
+ }
MachineBasicBlock::iterator CopyMI = MI;
--CopyMI;
@@ -303,6 +305,8 @@
<< "********** LOWERING SUBREG INSTRS **********\n"
<< "********** Function: "
<< MF.getFunction()->getName() << '\n');
+ TRI = MF.getTarget().getRegisterInfo();
+ TII = MF.getTarget().getInstrInfo();
bool MadeChange = false;
@@ -310,8 +314,8 @@
mbbi != mbbe; ++mbbi) {
for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
mi != me;) {
- MachineInstr *MI = mi++;
-
+ MachineBasicBlock::iterator nmi = next(mi);
+ MachineInstr *MI = mi;
if (MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
MadeChange |= LowerExtract(MI);
} else if (MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG) {
@@ -319,6 +323,7 @@
} else if (MI->getOpcode() == TargetInstrInfo::SUBREG_TO_REG) {
MadeChange |= LowerSubregToReg(MI);
}
+ mi = nmi;
}
}
Modified: llvm/branches/Apple/Leela/lib/CodeGen/RegisterScavenging.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/CodeGen/RegisterScavenging.cpp?rev=85267&r1=85266&r2=85267&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/CodeGen/RegisterScavenging.cpp (original)
+++ llvm/branches/Apple/Leela/lib/CodeGen/RegisterScavenging.cpp Tue Oct 27 13:37:21 2009
@@ -177,7 +177,24 @@
if (!Reg || isReserved(Reg))
continue;
if (MO.isUse()) {
- assert(isUsed(Reg) && "Using an undefined register!");
+ if (!isUsed(Reg)) {
+ // Check if it's partial live: e.g.
+ // D0 = insert_subreg D0<undef>, S0
+ // ... D0
+ // The problem is the insert_subreg could be eliminated. The use of
+ // D0 is using a partially undef value. This is not *incorrect* since
+ // S1 is can be freely clobbered.
+ // Ideally we would like a way to model this, but leaving the
+ // insert_subreg around causes both correctness and performance issues.
+ bool SubUsed = false;
+ for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
+ unsigned SubReg = *SubRegs; ++SubRegs)
+ if (isUsed(SubReg)) {
+ SubUsed = true;
+ break;
+ }
+ assert(SubUsed && "Using an undefined register!");
+ }
assert((!EarlyClobberRegs.test(Reg) || MI->isRegTiedToDefOperand(i)) &&
"Using an early clobbered register!");
} else {
Modified: llvm/branches/Apple/Leela/lib/CodeGen/SimpleRegisterCoalescing.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=85267&r1=85266&r2=85267&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/CodeGen/SimpleRegisterCoalescing.cpp (original)
+++ llvm/branches/Apple/Leela/lib/CodeGen/SimpleRegisterCoalescing.cpp Tue Oct 27 13:37:21 2009
@@ -922,7 +922,7 @@
DefMI->getOperand(DeadIdx).setIsDead();
else
DefMI->addOperand(MachineOperand::CreateReg(li.reg,
- true, true, false, true));
+ /*def*/true, /*implicit*/true, /*kill*/false, /*dead*/true));
LRStart = li_->getNextSlot(LRStart);
}
}
@@ -2556,6 +2556,7 @@
return true;
}
+
void SimpleRegisterCoalescing::CalculateSpillWeights() {
SmallSet<unsigned, 4> Processed;
for (MachineFunction::iterator mbbi = mf_->begin(), mbbe = mf_->end();
@@ -2566,9 +2567,14 @@
unsigned loopDepth = loop ? loop->getLoopDepth() : 0;
bool isExit = loop ? loop->isLoopExit(MBB) : false;
- for (MachineBasicBlock::iterator mii = MBB->begin(), mie = MBB->end();
+ for (MachineBasicBlock::const_iterator mii = MBB->begin(), mie = MBB->end();
mii != mie; ++mii) {
- MachineInstr *MI = mii;
+ const MachineInstr *MI = mii;
+ if (tii_->isIdentityCopy(*MI))
+ continue;
+
+ if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF)
+ continue;
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &mopi = MI->getOperand(i);
@@ -2598,8 +2604,7 @@
float Weight = li_->getSpillWeight(HasDef, HasUse, loopDepth);
if (HasDef && isExit) {
// Looks like this is a loop count variable update.
- LiveIndex DefIdx =
- li_->getDefIndex(li_->getInstructionIndex(MI));
+ LiveIndex DefIdx = li_->getDefIndex(li_->getInstructionIndex(MI));
const LiveRange *DLR =
li_->getInterval(Reg).getLiveRangeContaining(DefIdx);
if (DLR->end > MBBEnd)
@@ -2706,7 +2711,7 @@
// registers unless the definition is dead. e.g.
// %DO<def> = INSERT_SUBREG %D0<undef>, %S0<kill>, 1
// or else the scavenger may complain. LowerSubregs will
- // change this to an IMPLICIT_DEF later.
+ // delete them later.
DoDelete = false;
}
if (MI->registerDefIsDead(DstReg)) {
Modified: llvm/branches/Apple/Leela/lib/CodeGen/VirtRegRewriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/CodeGen/VirtRegRewriter.cpp?rev=85267&r1=85266&r2=85267&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/CodeGen/VirtRegRewriter.cpp (original)
+++ llvm/branches/Apple/Leela/lib/CodeGen/VirtRegRewriter.cpp Tue Oct 27 13:37:21 2009
@@ -614,7 +614,7 @@
assert(MO.isUse());
unsigned SubIdx = MO.getSubReg();
unsigned Phys = VRM.getPhys(VirtReg);
- assert(Phys);
+ assert(Phys && "Virtual register is not assigned a register?");
unsigned RReg = SubIdx ? TRI->getSubReg(Phys, SubIdx) : Phys;
MO.setReg(RReg);
MO.setSubReg(0);
@@ -857,7 +857,7 @@
Spills.ClobberPhysReg(NewPhysReg);
Spills.ClobberPhysReg(NewOp.PhysRegReused);
- unsigned RReg = SubIdx ? TRI->getSubReg(NewPhysReg, SubIdx) : NewPhysReg;
+ unsigned RReg = SubIdx ? TRI->getSubReg(NewPhysReg, SubIdx) :NewPhysReg;
MI->getOperand(NewOp.Operand).setReg(RReg);
MI->getOperand(NewOp.Operand).setSubReg(0);
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=85267&r1=85266&r2=85267&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/ARMBaseInstrInfo.cpp Tue Oct 27 13:37:21 2009
@@ -749,18 +749,24 @@
unsigned PredReg = MI->getOperand(3).getReg();
if (OpNum == 0) { // move -> store
unsigned SrcReg = MI->getOperand(1).getReg();
+ unsigned SrcSubReg = MI->getOperand(1).getSubReg();
bool isKill = MI->getOperand(1).isKill();
bool isUndef = MI->getOperand(1).isUndef();
if (Opc == ARM::MOVr)
NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::STR))
- .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
+ .addReg(SrcReg,
+ getKillRegState(isKill) | getUndefRegState(isUndef),
+ SrcSubReg)
.addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
else // ARM::t2MOVr
NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12))
- .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
+ .addReg(SrcReg,
+ getKillRegState(isKill) | getUndefRegState(isUndef),
+ SrcSubReg)
.addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
} else { // move -> load
unsigned DstReg = MI->getOperand(0).getReg();
+ unsigned DstSubReg = MI->getOperand(0).getSubReg();
bool isDead = MI->getOperand(0).isDead();
bool isUndef = MI->getOperand(0).isUndef();
if (Opc == ARM::MOVr)
@@ -768,14 +774,14 @@
.addReg(DstReg,
RegState::Define |
getDeadRegState(isDead) |
- getUndefRegState(isUndef))
+ getUndefRegState(isUndef), DstSubReg)
.addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
else // ARM::t2MOVr
NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12))
.addReg(DstReg,
RegState::Define |
getDeadRegState(isDead) |
- getUndefRegState(isUndef))
+ getUndefRegState(isUndef), DstSubReg)
.addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
}
} else if (Opc == ARM::tMOVgpr2gpr ||
@@ -783,20 +789,25 @@
Opc == ARM::tMOVgpr2tgpr) {
if (OpNum == 0) { // move -> store
unsigned SrcReg = MI->getOperand(1).getReg();
+ unsigned SrcSubReg = MI->getOperand(1).getSubReg();
bool isKill = MI->getOperand(1).isKill();
bool isUndef = MI->getOperand(1).isUndef();
NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2STRi12))
- .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
+ .addReg(SrcReg,
+ getKillRegState(isKill) | getUndefRegState(isUndef),
+ SrcSubReg)
.addFrameIndex(FI).addImm(0).addImm(ARMCC::AL).addReg(0);
} else { // move -> load
unsigned DstReg = MI->getOperand(0).getReg();
+ unsigned DstSubReg = MI->getOperand(0).getSubReg();
bool isDead = MI->getOperand(0).isDead();
bool isUndef = MI->getOperand(0).isUndef();
NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::t2LDRi12))
.addReg(DstReg,
RegState::Define |
getDeadRegState(isDead) |
- getUndefRegState(isUndef))
+ getUndefRegState(isUndef),
+ DstSubReg)
.addFrameIndex(FI).addImm(0).addImm(ARMCC::AL).addReg(0);
}
} else if (Opc == ARM::FCPYS) {
@@ -804,21 +815,25 @@
unsigned PredReg = MI->getOperand(3).getReg();
if (OpNum == 0) { // move -> store
unsigned SrcReg = MI->getOperand(1).getReg();
+ unsigned SrcSubReg = MI->getOperand(1).getSubReg();
bool isKill = MI->getOperand(1).isKill();
bool isUndef = MI->getOperand(1).isUndef();
NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTS))
- .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
+ .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef),
+ SrcSubReg)
.addFrameIndex(FI)
.addImm(0).addImm(Pred).addReg(PredReg);
} else { // move -> load
unsigned DstReg = MI->getOperand(0).getReg();
+ unsigned DstSubReg = MI->getOperand(0).getSubReg();
bool isDead = MI->getOperand(0).isDead();
bool isUndef = MI->getOperand(0).isUndef();
NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDS))
.addReg(DstReg,
RegState::Define |
getDeadRegState(isDead) |
- getUndefRegState(isUndef))
+ getUndefRegState(isUndef),
+ DstSubReg)
.addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
}
}
@@ -827,20 +842,25 @@
unsigned PredReg = MI->getOperand(3).getReg();
if (OpNum == 0) { // move -> store
unsigned SrcReg = MI->getOperand(1).getReg();
+ unsigned SrcSubReg = MI->getOperand(1).getSubReg();
bool isKill = MI->getOperand(1).isKill();
bool isUndef = MI->getOperand(1).isUndef();
NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTD))
- .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
+ .addReg(SrcReg,
+ getKillRegState(isKill) | getUndefRegState(isUndef),
+ SrcSubReg)
.addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
} else { // move -> load
unsigned DstReg = MI->getOperand(0).getReg();
+ unsigned DstSubReg = MI->getOperand(0).getSubReg();
bool isDead = MI->getOperand(0).isDead();
bool isUndef = MI->getOperand(0).isUndef();
NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDD))
.addReg(DstReg,
RegState::Define |
getDeadRegState(isDead) |
- getUndefRegState(isUndef))
+ getUndefRegState(isUndef),
+ DstSubReg)
.addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
}
}
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/ARMBaseRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=85267&r1=85266&r2=85267&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/ARMBaseRegisterInfo.cpp Tue Oct 27 13:37:21 2009
@@ -254,6 +254,33 @@
}
const TargetRegisterClass *
+ARMBaseRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
+ const TargetRegisterClass *B,
+ unsigned SubIdx) const {
+ switch (SubIdx) {
+ default: return 0;
+ case 1:
+ case 2:
+ case 3:
+ case 4:
+ // S sub-registers.
+ if (A->getSize() == 8) {
+ if (A == &ARM::DPR_8RegClass)
+ return A;
+ return &ARM::DPR_VFP2RegClass;
+ }
+
+ assert(A->getSize() == 16 && "Expecting a Q register class!");
+ return &ARM::QPR_VFP2RegClass;
+ case 5:
+ case 6:
+ // D sub-registers.
+ return A;
+ }
+ return 0;
+}
+
+const TargetRegisterClass *
ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const {
return ARM::GPRRegisterClass;
}
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/ARMBaseRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/ARMBaseRegisterInfo.h?rev=85267&r1=85266&r2=85267&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/ARMBaseRegisterInfo.h (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/ARMBaseRegisterInfo.h Tue Oct 27 13:37:21 2009
@@ -74,6 +74,13 @@
BitVector getReservedRegs(const MachineFunction &MF) const;
+ /// getMatchingSuperRegClass - Return a subclass of the specified register
+ /// class A so that each register in it has a sub-register of the
+ /// specified sub-register index which is in the specified register class B.
+ virtual const TargetRegisterClass *
+ getMatchingSuperRegClass(const TargetRegisterClass *A,
+ const TargetRegisterClass *B, unsigned Idx) const;
+
const TargetRegisterClass *getPointerRegClass(unsigned Kind = 0) const;
std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
Modified: llvm/branches/Apple/Leela/test/CodeGen/ARM/fnmacs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/test/CodeGen/ARM/fnmacs.ll?rev=85267&r1=85266&r2=85267&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/test/CodeGen/ARM/fnmacs.ll (original)
+++ llvm/branches/Apple/Leela/test/CodeGen/ARM/fnmacs.ll Tue Oct 27 13:37:21 2009
@@ -1,11 +1,16 @@
-; RUN: llc < %s -march=arm -mattr=+vfp2 | grep -E {fnmacs\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
-; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | grep -E {vmls.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1
-; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | grep -E {fnmacs\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
-; RUN: llc < %s -march=arm -mcpu=cortex-a8 | grep -E {vmls.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1
-; RUN: llc < %s -march=arm -mcpu=cortex-a9 | grep -E {fnmacs\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
+; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2
+; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | FileCheck %s -check-prefix=NEON
+; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | FileCheck %s -check-prefix=NEONFP
define float @test(float %acc, float %a, float %b) {
entry:
+; VFP2: fnmacs
+; NEON: fnmacs
+
+; NEONFP: vmls
+; NEONFP-NOT: fcpys
+; NEONFP: fmrs
+
%0 = fmul float %a, %b
%1 = fsub float %acc, %0
ret float %1
Modified: llvm/branches/Apple/Leela/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug.ll?rev=85267&r1=85266&r2=85267&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug.ll (original)
+++ llvm/branches/Apple/Leela/test/CodeGen/Thumb2/2009-08-04-SubregLoweringBug.ll Tue Oct 27 13:37:21 2009
@@ -1,5 +1,5 @@
; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mattr=+neon -arm-use-neon-fp
-; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mattr=+neon -arm-use-neon-fp | grep fcpys | count 1
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mattr=+neon -arm-use-neon-fp | not grep fcpys
; rdar://7117307
%struct.Hosp = type { i32, i32, i32, %struct.List, %struct.List, %struct.List, %struct.List }
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