[llvm-branch-commits] [llvm-branch] r84984 - /llvm/branches/Apple/Leela/lib/Target/ARM/ARMRegisterInfo.td

[Bill Wendling]

Author: void
Date: Fri Oct 23 19:37:28 2009
New Revision: 84984

URL: http://llvm.org/viewvc/llvm-project?rev=84984&view=rev
Log:
$ svn merge -c 84977 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r84977 into '.':
U    lib/Target/ARM/ARMRegisterInfo.td
$ svn merge -c 84982 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r84982 into '.':
G    lib/Target/ARM/ARMRegisterInfo.td


Modified:
    llvm/branches/Apple/Leela/lib/Target/ARM/ARMRegisterInfo.td

Modified: llvm/branches/Apple/Leela/lib/Target/ARM/ARMRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/ARMRegisterInfo.td?rev=84984&r1=84983&r2=84984&view=diff

==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/ARMRegisterInfo.td (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/ARMRegisterInfo.td Fri Oct 23 19:37:28 2009
@@ -129,9 +129,6 @@
     iterator allocation_order_begin(const MachineFunction &MF) const;
     iterator allocation_order_end(const MachineFunction &MF) const;
   }];
-  // FIXME: We are reserving r12 in case the PEI needs to use it to
-  // generate large stack offset. Make it available once we have register
-  // scavenging. Similarly r3 is reserved in Thumb mode for now.
   let MethodBodies = [{
     // FP is R11, R9 is available.
     static const unsigned ARM_GPR_AO_1[] = {
@@ -169,10 +166,20 @@
       ARM::R4, ARM::R5, ARM::R6,
       ARM::R8, ARM::R9, ARM::R10,ARM::R11,ARM::R7 };
 
+    // For Thumb1 mode, we don't want to allocate hi regs at all, as we
+    // don't know how to spill them. If we make our prologue/epilogue code
+    // smarter at some point, we can go back to using the above allocation
+    // orders for the Thumb1 instructions that know how to use hi regs.
+    static const unsigned THUMB_GPR_AO[] = {
+      ARM::R0, ARM::R1, ARM::R2, ARM::R3,
+      ARM::R4, ARM::R5, ARM::R6, ARM::R7 };
+
     GPRClass::iterator
     GPRClass::allocation_order_begin(const MachineFunction &MF) const {
       const TargetMachine &TM = MF.getTarget();
       const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
+      if (Subtarget.isThumb1Only())
+        return THUMB_GPR_AO;
       if (Subtarget.isTargetDarwin()) {
         if (Subtarget.isR9Reserved())
           return ARM_GPR_AO_4;
@@ -195,6 +202,12 @@
       const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
       GPRClass::iterator I;
 
+      if (Subtarget.isThumb1Only()) {
+        I = THUMB_GPR_AO + (sizeof(THUMB_GPR_AO)/sizeof(unsigned));
+        // Mac OS X requires FP not to be clobbered for backtracing purpose.
+        return (Subtarget.isTargetDarwin() || RI->hasFP(MF)) ? I-1 : I;
+      }
+
       if (Subtarget.isTargetDarwin()) {
         if (Subtarget.isR9Reserved())
           I = ARM_GPR_AO_4 + (sizeof(ARM_GPR_AO_4)/sizeof(unsigned));