[llvm-branch-commits] [llvm-branch] r84957 - in /llvm/branches/Apple/Leela: lib/Target/X86/X86Subtarget.h test/CodeGen/X86/2007-01-08-InstrSched.ll test/CodeGen/X86/sse2.ll test/CodeGen/X86/sse3.ll test/CodeGen/X86/vshift-1.ll test/CodeGen/X86/vshift-2.ll test/CodeGen/X86/vshift-3.ll test/CodeGen/X86/vshift-5.ll
Bill Wendling
isanbard at gmail.com
Fri Oct 23 11:17:23 PDT 2009
Author: void
Date: Fri Oct 23 13:17:22 2009
New Revision: 84957
URL: http://llvm.org/viewvc/llvm-project?rev=84957&view=rev
Log:
$ svn merge -c 84931 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r84931 into '.':
U lib/Target/X86/X86Subtarget.h
$ svn merge -c 84932 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r84932 into '.':
U test/CodeGen/X86/sse2.ll
U test/CodeGen/X86/vshift-1.ll
U test/CodeGen/X86/vshift-3.ll
U test/CodeGen/X86/vshift-5.ll
U test/CodeGen/X86/2007-01-08-InstrSched.ll
U test/CodeGen/X86/sse3.ll
U test/CodeGen/X86/vshift-2.ll
Modified:
llvm/branches/Apple/Leela/lib/Target/X86/X86Subtarget.h
llvm/branches/Apple/Leela/test/CodeGen/X86/2007-01-08-InstrSched.ll
llvm/branches/Apple/Leela/test/CodeGen/X86/sse2.ll
llvm/branches/Apple/Leela/test/CodeGen/X86/sse3.ll
llvm/branches/Apple/Leela/test/CodeGen/X86/vshift-1.ll
llvm/branches/Apple/Leela/test/CodeGen/X86/vshift-2.ll
llvm/branches/Apple/Leela/test/CodeGen/X86/vshift-3.ll
llvm/branches/Apple/Leela/test/CodeGen/X86/vshift-5.ll
Modified: llvm/branches/Apple/Leela/lib/Target/X86/X86Subtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/X86/X86Subtarget.h?rev=84957&r1=84956&r2=84957&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/X86/X86Subtarget.h (original)
+++ llvm/branches/Apple/Leela/lib/Target/X86/X86Subtarget.h Fri Oct 23 13:17:22 2009
@@ -227,7 +227,7 @@
/// at 'More' optimization level.
bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
TargetSubtarget::AntiDepBreakMode& mode) const {
- mode = TargetSubtarget::ANTIDEP_NONE;
+ mode = TargetSubtarget::ANTIDEP_CRITICAL;
return OptLevel >= CodeGenOpt::Default;
}
};
Modified: llvm/branches/Apple/Leela/test/CodeGen/X86/2007-01-08-InstrSched.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/test/CodeGen/X86/2007-01-08-InstrSched.ll?rev=84957&r1=84956&r2=84957&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/test/CodeGen/X86/2007-01-08-InstrSched.ll (original)
+++ llvm/branches/Apple/Leela/test/CodeGen/X86/2007-01-08-InstrSched.ll Fri Oct 23 13:17:22 2009
@@ -11,12 +11,12 @@
%tmp14 = fadd float %tmp12, %tmp7
ret float %tmp14
-; CHECK: mulss LCPI1_0(%rip)
-; CHECK-NEXT: mulss LCPI1_1(%rip)
-; CHECK-NEXT: addss
; CHECK: mulss LCPI1_3(%rip)
+; CHECK-NEXT: mulss LCPI1_0(%rip)
+; CHECK-NEXT: mulss LCPI1_1(%rip)
; CHECK-NEXT: mulss LCPI1_2(%rip)
; CHECK-NEXT: addss
; CHECK-NEXT: addss
+; CHECK-NEXT: addss
; CHECK-NEXT: ret
}
Modified: llvm/branches/Apple/Leela/test/CodeGen/X86/sse2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/test/CodeGen/X86/sse2.ll?rev=84957&r1=84956&r2=84957&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/test/CodeGen/X86/sse2.ll (original)
+++ llvm/branches/Apple/Leela/test/CodeGen/X86/sse2.ll Fri Oct 23 13:17:22 2009
@@ -10,10 +10,10 @@
; CHECK: t1:
; CHECK: movl 8(%esp), %eax
+; CHECK-NEXT: movl 4(%esp), %ecx
; CHECK-NEXT: movapd (%eax), %xmm0
-; CHECK-NEXT: movl 4(%esp), %eax
; CHECK-NEXT: movlpd 12(%esp), %xmm0
-; CHECK-NEXT: movapd %xmm0, (%eax)
+; CHECK-NEXT: movapd %xmm0, (%ecx)
; CHECK-NEXT: ret
}
@@ -26,9 +26,9 @@
; CHECK: t2:
; CHECK: movl 8(%esp), %eax
+; CHECK-NEXT: movl 4(%esp), %ecx
; CHECK-NEXT: movapd (%eax), %xmm0
-; CHECK-NEXT: movl 4(%esp), %eax
; CHECK-NEXT: movhpd 12(%esp), %xmm0
-; CHECK-NEXT: movapd %xmm0, (%eax)
+; CHECK-NEXT: movapd %xmm0, (%ecx)
; CHECK-NEXT: ret
}
Modified: llvm/branches/Apple/Leela/test/CodeGen/X86/sse3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/test/CodeGen/X86/sse3.ll?rev=84957&r1=84956&r2=84957&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/test/CodeGen/X86/sse3.ll (original)
+++ llvm/branches/Apple/Leela/test/CodeGen/X86/sse3.ll Fri Oct 23 13:17:22 2009
@@ -168,11 +168,11 @@
ret void
; X64: t10:
; X64: pextrw $4, %xmm0, %eax
+; X64: pextrw $6, %xmm0, %edx
; X64: movlhps %xmm1, %xmm1
; X64: pshuflw $8, %xmm1, %xmm1
; X64: pinsrw $2, %eax, %xmm1
-; X64: pextrw $6, %xmm0, %eax
-; X64: pinsrw $3, %eax, %xmm1
+; X64: pinsrw $3, %edx, %xmm1
}
Modified: llvm/branches/Apple/Leela/test/CodeGen/X86/vshift-1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/test/CodeGen/X86/vshift-1.ll?rev=84957&r1=84956&r2=84957&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/test/CodeGen/X86/vshift-1.ll (original)
+++ llvm/branches/Apple/Leela/test/CodeGen/X86/vshift-1.ll Fri Oct 23 13:17:22 2009
@@ -63,7 +63,7 @@
; CHECK: shift3b:
; CHECK: movzwl
; CHECK: movd
-; CHECK: psllw
+; CHECK-NEXT: psllw
%0 = insertelement <8 x i16> undef, i16 %amt, i32 0
%1 = insertelement <8 x i16> %0, i16 %amt, i32 1
%2 = insertelement <8 x i16> %0, i16 %amt, i32 2
Modified: llvm/branches/Apple/Leela/test/CodeGen/X86/vshift-2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/test/CodeGen/X86/vshift-2.ll?rev=84957&r1=84956&r2=84957&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/test/CodeGen/X86/vshift-2.ll (original)
+++ llvm/branches/Apple/Leela/test/CodeGen/X86/vshift-2.ll Fri Oct 23 13:17:22 2009
@@ -63,7 +63,7 @@
; CHECK: shift3b:
; CHECK: movzwl
; CHECK: movd
-; CHECK: psrlw
+; CHECK-NEXT: psrlw
%0 = insertelement <8 x i16> undef, i16 %amt, i32 0
%1 = insertelement <8 x i16> %0, i16 %amt, i32 1
%2 = insertelement <8 x i16> %0, i16 %amt, i32 2
Modified: llvm/branches/Apple/Leela/test/CodeGen/X86/vshift-3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/test/CodeGen/X86/vshift-3.ll?rev=84957&r1=84956&r2=84957&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/test/CodeGen/X86/vshift-3.ll (original)
+++ llvm/branches/Apple/Leela/test/CodeGen/X86/vshift-3.ll Fri Oct 23 13:17:22 2009
@@ -52,7 +52,7 @@
; CHECK: shift3b:
; CHECK: movzwl
; CHECK: movd
-; CHECK: psraw
+; CHECK-NEXT: psraw
%0 = insertelement <8 x i16> undef, i16 %amt, i32 0
%1 = insertelement <8 x i16> %0, i16 %amt, i32 1
%2 = insertelement <8 x i16> %0, i16 %amt, i32 2
Modified: llvm/branches/Apple/Leela/test/CodeGen/X86/vshift-5.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/test/CodeGen/X86/vshift-5.ll?rev=84957&r1=84956&r2=84957&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/test/CodeGen/X86/vshift-5.ll (original)
+++ llvm/branches/Apple/Leela/test/CodeGen/X86/vshift-5.ll Fri Oct 23 13:17:22 2009
@@ -6,7 +6,7 @@
entry:
; CHECK: shift5a:
; CHECK: movd
-; CHECK: pslld
+; CHECK-NEXT: pslld
%amt = load i32* %pamt
%tmp0 = insertelement <4 x i32> undef, i32 %amt, i32 0
%shamt = shufflevector <4 x i32> %tmp0, <4 x i32> undef, <4 x i32> zeroinitializer
@@ -20,7 +20,7 @@
entry:
; CHECK: shift5b:
; CHECK: movd
-; CHECK: psrad
+; CHECK-NEXT: psrad
%amt = load i32* %pamt
%tmp0 = insertelement <4 x i32> undef, i32 %amt, i32 0
%shamt = shufflevector <4 x i32> %tmp0, <4 x i32> undef, <4 x i32> zeroinitializer
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