[llvm-branch-commits] [llvm-branch] r84897 - in /llvm/branches/Apple/Leela: lib/Target/ARM/ARMISelDAGToDAG.cpp lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrThumb2.td lib/Target/ARM/ARMSubtarget.cpp lib/Target/ARM/Thumb2ITBlockPass.cpp test/CodeGen/ARM/ldrd.ll test/CodeGen/ARM/movt.ll test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll test/CodeGen/Thumb2/thumb2-mov2.ll
Bill Wendling
isanbard at gmail.com
Thu Oct 22 14:26:19 PDT 2009
Author: void
Date: Thu Oct 22 16:26:19 2009
New Revision: 84897
URL: http://llvm.org/viewvc/llvm-project?rev=84897&view=rev
Log:
$ svn merge -c 84212 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r84212 into '.':
A test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll
U lib/Target/ARM/Thumb2ITBlockPass.cpp
$ svn merge -c 84249 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r84249 into '.':
U test/CodeGen/ARM/ldrd.ll
U lib/Target/ARM/ARMSubtarget.cpp
$ svn merge -c 84751 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r84751 into '.':
A test/CodeGen/ARM/movt.ll
U test/CodeGen/Thumb2/thumb2-mov2.ll
U lib/Target/ARM/ARMInstrThumb2.td
U lib/Target/ARM/ARMInstrInfo.td
U lib/Target/ARM/ARMISelLowering.cpp
U lib/Target/ARM/ARMISelDAGToDAG.cpp
Added:
llvm/branches/Apple/Leela/test/CodeGen/ARM/movt.ll
- copied unchanged from r84751, llvm/trunk/test/CodeGen/ARM/movt.ll
llvm/branches/Apple/Leela/test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll
- copied unchanged from r84212, llvm/trunk/test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll
Modified:
llvm/branches/Apple/Leela/lib/Target/ARM/ARMISelDAGToDAG.cpp
llvm/branches/Apple/Leela/lib/Target/ARM/ARMISelLowering.cpp
llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrInfo.td
llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrThumb2.td
llvm/branches/Apple/Leela/lib/Target/ARM/ARMSubtarget.cpp
llvm/branches/Apple/Leela/lib/Target/ARM/Thumb2ITBlockPass.cpp
llvm/branches/Apple/Leela/test/CodeGen/ARM/ldrd.ll
llvm/branches/Apple/Leela/test/CodeGen/Thumb2/thumb2-mov2.ll
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/ARMISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=84897&r1=84896&r2=84897&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/ARMISelDAGToDAG.cpp Thu Oct 22 16:26:19 2009
@@ -1427,6 +1427,43 @@
}
}
break;
+ case ISD::AND: {
+ // (and (or x, c2), c1) and top 16-bits of c1 and c2 match, lower 16-bits
+ // of c1 are 0xffff, and lower 16-bit of c2 are 0. That is, the top 16-bits
+ // are entirely contributed by c2 and lower 16-bits are entirely contributed
+ // by x. That's equal to (or (and x, 0xffff), (and c1, 0xffff0000)).
+ // Select it to: "movt x, ((c1 & 0xffff) >> 16)
+ EVT VT = Op.getValueType();
+ if (VT != MVT::i32)
+ break;
+ unsigned Opc = (Subtarget->isThumb() && Subtarget->hasThumb2())
+ ? ARM::t2MOVTi16
+ : (Subtarget->hasV6T2Ops() ? ARM::MOVTi16 : 0);
+ if (!Opc)
+ break;
+ SDValue N0 = Op.getOperand(0), N1 = Op.getOperand(1);
+ ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
+ if (!N1C)
+ break;
+ if (N0.getOpcode() == ISD::OR && N0.getNode()->hasOneUse()) {
+ SDValue N2 = N0.getOperand(1);
+ ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
+ if (!N2C)
+ break;
+ unsigned N1CVal = N1C->getZExtValue();
+ unsigned N2CVal = N2C->getZExtValue();
+ if ((N1CVal & 0xffff0000U) == (N2CVal & 0xffff0000U) &&
+ (N1CVal & 0xffffU) == 0xffffU &&
+ (N2CVal & 0xffffU) == 0x0U) {
+ SDValue Imm16 = CurDAG->getTargetConstant((N2CVal & 0xFFFF0000U) >> 16,
+ MVT::i32);
+ SDValue Ops[] = { N0.getOperand(0), Imm16,
+ getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
+ return CurDAG->getMachineNode(Opc, dl, VT, Ops, 4);
+ }
+ }
+ break;
+ }
case ARMISD::FMRRD:
return CurDAG->getMachineNode(ARM::FMRRD, dl, MVT::i32, MVT::i32,
Op.getOperand(0), getAL(CurDAG),
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/ARMISelLowering.cpp?rev=84897&r1=84896&r2=84897&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/ARMISelLowering.cpp Thu Oct 22 16:26:19 2009
@@ -3036,7 +3036,6 @@
return SDValue();
}
-
/// PerformFMRRDCombine - Target-specific dag combine xforms for ARMISD::FMRRD.
static SDValue PerformFMRRDCombine(SDNode *N,
TargetLowering::DAGCombinerInfo &DCI) {
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrInfo.td?rev=84897&r1=84896&r2=84897&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrInfo.td Thu Oct 22 16:26:19 2009
@@ -980,6 +980,9 @@
let Inst{25} = 1;
}
+def : ARMPat<(or GPR:$src, 0xffff0000), (MOVTi16 GPR:$src, 0xffff)>,
+ Requires<[IsARM, HasV6T2]>;
+
let Uses = [CPSR] in
def MOVrx : AsI1<0b1101, (outs GPR:$dst), (ins GPR:$src), Pseudo, IIC_iMOVsi,
"mov", " $dst, $src, rrx",
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrThumb2.td?rev=84897&r1=84896&r2=84897&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrThumb2.td Thu Oct 22 16:26:19 2009
@@ -685,6 +685,8 @@
[(set GPR:$dst,
(or (and GPR:$src, 0xffff), lo16AllZero:$imm))]>;
+def : T2Pat<(or GPR:$src, 0xffff0000), (t2MOVTi16 GPR:$src, 0xffff)>;
+
//===----------------------------------------------------------------------===//
// Extend Instructions.
//
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/ARMSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/ARMSubtarget.cpp?rev=84897&r1=84896&r2=84897&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/ARMSubtarget.cpp (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/ARMSubtarget.cpp Thu Oct 22 16:26:19 2009
@@ -27,11 +27,11 @@
cl::init(false), cl::Hidden);
ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &FS,
- bool isThumb)
+ bool isT)
: ARMArchVersion(V4T)
, ARMFPUType(None)
, UseNEONForSinglePrecisionFP(UseNEONFP)
- , IsThumb(isThumb)
+ , IsThumb(isT)
, ThumbMode(Thumb1)
, PostRAScheduler(false)
, IsR9Reserved(ReserveR9)
@@ -98,9 +98,11 @@
if (isTargetDarwin())
IsR9Reserved = ReserveR9 | (ARMArchVersion < V6);
+ if (!isThumb() || hasThumb2())
+ PostRAScheduler = true;
+
// Set CPU specific features.
if (CPUString == "cortex-a8") {
- PostRAScheduler = true;
if (UseNEONFP.getPosition() == 0)
UseNEONForSinglePrecisionFP = true;
}
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/Thumb2ITBlockPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/Thumb2ITBlockPass.cpp?rev=84897&r1=84896&r2=84897&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/Thumb2ITBlockPass.cpp (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/Thumb2ITBlockPass.cpp Thu Oct 22 16:26:19 2009
@@ -107,8 +107,12 @@
// Finalize IT mask.
ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC);
unsigned Mask = 0, Pos = 3;
- while (MBBI != E && Pos) {
+ // Branches, including tricky ones like LDM_RET, need to end an IT
+ // block so check the instruction we just put in the block.
+ while (MBBI != E && Pos &&
+ (!MI->getDesc().isBranch() && !MI->getDesc().isReturn())) {
MachineInstr *NMI = &*MBBI;
+ MI = NMI;
DebugLoc ndl = NMI->getDebugLoc();
unsigned NPredReg = 0;
ARMCC::CondCodes NCC = getPredicate(NMI, NPredReg);
Modified: llvm/branches/Apple/Leela/test/CodeGen/ARM/ldrd.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/test/CodeGen/ARM/ldrd.ll?rev=84897&r1=84896&r2=84897&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/test/CodeGen/ARM/ldrd.ll (original)
+++ llvm/branches/Apple/Leela/test/CodeGen/ARM/ldrd.ll Thu Oct 22 16:26:19 2009
@@ -7,13 +7,13 @@
define i64 @t(i64 %a) nounwind readonly {
entry:
-;V6: ldrd r2, [r2]
+;V6: ldrd r2, [r2]
-;V5: ldr r3, [r2]
-;V5-NEXT: ldr r2, [r2, #+4]
+;V5: ldr r3, [r2]
+;V5: ldr r2, [r2, #+4]
-;EABI: ldr r3, [r2]
-;EABI-NEXT: ldr r2, [r2, #+4]
+;EABI: ldr r3, [r2]
+;EABI: ldr r2, [r2, #+4]
%0 = load i64** @b, align 4
%1 = load i64* %0, align 4
Modified: llvm/branches/Apple/Leela/test/CodeGen/Thumb2/thumb2-mov2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/test/CodeGen/Thumb2/thumb2-mov2.ll?rev=84897&r1=84896&r2=84897&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/test/CodeGen/Thumb2/thumb2-mov2.ll (original)
+++ llvm/branches/Apple/Leela/test/CodeGen/Thumb2/thumb2-mov2.ll Thu Oct 22 16:26:19 2009
@@ -2,10 +2,7 @@
define i32 @t2MOVTi16_ok_1(i32 %a) {
; CHECK: t2MOVTi16_ok_1:
-; CHECK: movs r1, #0
-; CHECK-NEXT: movt r1, #1234
-; CHECK: movw r1, #65535
-; CHECK-NEXT: movt r1, #1234
+; CHECK: movt r0, #1234
%1 = and i32 %a, 65535
%2 = shl i32 1234, 16
%3 = or i32 %1, %2
@@ -15,10 +12,7 @@
define i32 @t2MOVTi16_test_1(i32 %a) {
; CHECK: t2MOVTi16_test_1:
-; CHECK: movs r1, #0
-; CHECK-NEXT: movt r1, #1234
-; CHECK: movw r1, #65535
-; CHECK-NEXT: movt r1, #1234
+; CHECK: movt r0, #1234
%1 = shl i32 255, 8
%2 = shl i32 1234, 8
%3 = or i32 %1, 255 ; This give us 0xFFFF in %3
@@ -31,10 +25,7 @@
define i32 @t2MOVTi16_test_2(i32 %a) {
; CHECK: t2MOVTi16_test_2:
-; CHECK: movs r1, #0
-; CHECK-NEXT: movt r1, #1234
-; CHECK: movw r1, #65535
-; CHECK-NEXT: movt r1, #1234
+; CHECK: movt r0, #1234
%1 = shl i32 255, 8
%2 = shl i32 1234, 8
%3 = or i32 %1, 255 ; This give us 0xFFFF in %3
@@ -48,10 +39,7 @@
define i32 @t2MOVTi16_test_3(i32 %a) {
; CHECK: t2MOVTi16_test_3:
-; CHECK: movs r1, #0
-; CHECK-NEXT: movt r1, #1234
-; CHECK: movw r1, #65535
-; CHECK-NEXT: movt r1, #1234
+; CHECK: movt r0, #1234
%1 = shl i32 255, 8
%2 = shl i32 1234, 8
%3 = or i32 %1, 255 ; This give us 0xFFFF in %3
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