[llvm-branch-commits] [llvm-branch] r84822 - in /llvm/branches/Apple/Leela: lib/CodeGen/PrologEpilogInserter.cpp lib/CodeGen/RegisterScavenging.cpp lib/Target/ARM/ARMAddressingModes.h lib/Target/ARM/ARMBaseRegisterInfo.cpp lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrThumb2.td lib/Target/ARM/Thumb1RegisterInfo.cpp lib/Target/ARM/Thumb1RegisterInfo.h test/CodeGen/Thumb2/thumb2-mov.ll test/CodeGen/Thumb2/thumb2-mov2.ll
Jim Grosbach
grosbach at apple.com
Wed Oct 21 18:24:32 PDT 2009
Author: grosbach
Date: Wed Oct 21 20:24:25 2009
New Revision: 84822
URL: http://llvm.org/viewvc/llvm-project?rev=84822&view=rev
Log:
ARM merges.
84133, 84138, 84641, 84657, 84664, 84669, 84761, 84778, 84791, 84792, 84798.
Modified:
llvm/branches/Apple/Leela/lib/CodeGen/PrologEpilogInserter.cpp
llvm/branches/Apple/Leela/lib/CodeGen/RegisterScavenging.cpp
llvm/branches/Apple/Leela/lib/Target/ARM/ARMAddressingModes.h
llvm/branches/Apple/Leela/lib/Target/ARM/ARMBaseRegisterInfo.cpp
llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrInfo.td
llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrThumb2.td
llvm/branches/Apple/Leela/lib/Target/ARM/Thumb1RegisterInfo.cpp
llvm/branches/Apple/Leela/lib/Target/ARM/Thumb1RegisterInfo.h
llvm/branches/Apple/Leela/test/CodeGen/Thumb2/thumb2-mov.ll
llvm/branches/Apple/Leela/test/CodeGen/Thumb2/thumb2-mov2.ll
Modified: llvm/branches/Apple/Leela/lib/CodeGen/PrologEpilogInserter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/CodeGen/PrologEpilogInserter.cpp?rev=84822&r1=84821&r2=84822&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/CodeGen/PrologEpilogInserter.cpp (original)
+++ llvm/branches/Apple/Leela/lib/CodeGen/PrologEpilogInserter.cpp Wed Oct 21 20:24:25 2009
@@ -729,10 +729,12 @@
/// the instruciton range. Return the operand number of the kill in Operand.
static MachineBasicBlock::iterator
findLastUseReg(MachineBasicBlock::iterator I, MachineBasicBlock::iterator ME,
- unsigned Reg, unsigned *Operand) {
+ unsigned Reg) {
// Scan forward to find the last use of this virtual register
for (++I; I != ME; ++I) {
MachineInstr *MI = I;
+ bool isDefInsn = false;
+ bool isKillInsn = false;
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
if (MI->getOperand(i).isReg()) {
unsigned OpReg = MI->getOperand(i).getReg();
@@ -740,13 +742,14 @@
continue;
assert (OpReg == Reg
&& "overlapping use of scavenged index register!");
- // If this is the killing use, we're done
- if (MI->getOperand(i).isKill()) {
- if (Operand)
- *Operand = i;
- return I;
- }
+ // If this is the killing use, we have a candidate.
+ if (MI->getOperand(i).isKill())
+ isKillInsn = true;
+ else if (MI->getOperand(i).isDef())
+ isDefInsn = true;
}
+ if (isKillInsn && !isDefInsn)
+ return I;
}
// If we hit the end of the basic block, there was no kill of
// the virtual register, which is wrong.
@@ -763,11 +766,14 @@
E = Fn.end(); BB != E; ++BB) {
RS->enterBasicBlock(BB);
+ // FIXME: The logic flow in this function is still too convoluted.
+ // It needs a cleanup refactoring. Do that in preparation for tracking
+ // more than one scratch register value and using ranges to find
+ // available scratch registers.
unsigned CurrentVirtReg = 0;
unsigned CurrentScratchReg = 0;
bool havePrevValue = false;
- unsigned PrevScratchReg = 0;
- int PrevValue;
+ int PrevValue = 0;
MachineInstr *PrevLastUseMI = NULL;
unsigned PrevLastUseOp = 0;
bool trackingCurrentValue = false;
@@ -776,11 +782,13 @@
// The instruction stream may change in the loop, so check BB->end()
// directly.
- for (MachineBasicBlock::iterator I = BB->begin(); I != BB->end(); ++I) {
+ for (MachineBasicBlock::iterator I = BB->begin(); I != BB->end(); ) {
MachineInstr *MI = I;
- // Likewise, call getNumOperands() each iteration, as the MI may change
- // inside the loop (with 'i' updated accordingly).
- for (unsigned i = 0; i != MI->getNumOperands(); ++i)
+ bool isDefInsn = false;
+ bool isKillInsn = false;
+ bool clobbersScratchReg = false;
+ bool DoIncr = true;
+ for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
if (MI->getOperand(i).isReg()) {
MachineOperand &MO = MI->getOperand(i);
unsigned Reg = MO.getReg();
@@ -789,21 +797,24 @@
if (!TargetRegisterInfo::isVirtualRegister(Reg)) {
// If we have a previous scratch reg, check and see if anything
// here kills whatever value is in there.
- if (Reg == PrevScratchReg) {
+ if (Reg == CurrentScratchReg) {
if (MO.isUse()) {
// Two-address operands implicitly kill
- if (MO.isKill() || MI->isRegTiedToDefOperand(i)) {
- havePrevValue = false;
- PrevScratchReg = 0;
- }
+ if (MO.isKill() || MI->isRegTiedToDefOperand(i))
+ clobbersScratchReg = true;
} else {
assert (MO.isDef());
- havePrevValue = false;
- PrevScratchReg = 0;
+ clobbersScratchReg = true;
}
}
continue;
}
+ // If this is a def, remember that this insn defines the value.
+ // This lets us properly consider insns which re-use the scratch
+ // register, such as r2 = sub r2, #imm, in the middle of the
+ // scratch range.
+ if (MO.isDef())
+ isDefInsn = true;
// Have we already allocated a scratch register for this virtual?
if (Reg != CurrentVirtReg) {
@@ -834,49 +845,75 @@
// for the virtual register are exclusively for the purpose
// of populating the value in the register. That's reasonable
// for these frame index registers, but it's still a very, very
- // strong assumption. Perhaps this implies that the frame index
- // elimination should be before register allocation, with
- // conservative heuristics since we'll know less then, and
- // the reuse calculations done directly when doing the code-gen?
+ // strong assumption. rdar://7322732. Better would be to
+ // explicitly check each instruction in the range for references
+ // to the virtual register. Only delete those insns that
+ // touch the virtual register.
// Find the last use of the new virtual register. Remove all
// instruction between here and there, and update the current
// instruction to reference the last use insn instead.
MachineBasicBlock::iterator LastUseMI =
- findLastUseReg(I, BB->end(), Reg, &i);
+ findLastUseReg(I, BB->end(), Reg);
+
// Remove all instructions up 'til the last use, since they're
// just calculating the value we already have.
BB->erase(I, LastUseMI);
MI = I = LastUseMI;
- CurrentScratchReg = PrevScratchReg;
- // Extend the live range of the register
+ // Extend the live range of the scratch register
PrevLastUseMI->getOperand(PrevLastUseOp).setIsKill(false);
RS->setUsed(CurrentScratchReg);
- } else {
CurrentVirtReg = Reg;
- const TargetRegisterClass *RC = Fn.getRegInfo().getRegClass(Reg);
- CurrentScratchReg = RS->FindUnusedReg(RC);
- if (CurrentScratchReg == 0)
- // No register is "free". Scavenge a register.
- CurrentScratchReg = RS->scavengeRegister(RC, I, SPAdj);
- PrevValue = Value;
+ // We deleted the instruction we were scanning the operands of.
+ // Jump back to the instruction iterator loop. Don't increment
+ // past this instruction since we updated the iterator already.
+ DoIncr = false;
+ break;
}
+
+ // Scavenge a new scratch register
+ CurrentVirtReg = Reg;
+ const TargetRegisterClass *RC = Fn.getRegInfo().getRegClass(Reg);
+ CurrentScratchReg = RS->FindUnusedReg(RC);
+ if (CurrentScratchReg == 0)
+ // No register is "free". Scavenge a register.
+ CurrentScratchReg = RS->scavengeRegister(RC, I, SPAdj);
+
+ PrevValue = Value;
}
+ // replace this reference to the virtual register with the
+ // scratch register.
assert (CurrentScratchReg && "Missing scratch register!");
MI->getOperand(i).setReg(CurrentScratchReg);
- // If this is the last use of the register, stop tracking it.
if (MI->getOperand(i).isKill()) {
- PrevScratchReg = CurrentScratchReg;
- PrevLastUseMI = MI;
+ isKillInsn = true;
PrevLastUseOp = i;
- CurrentScratchReg = CurrentVirtReg = 0;
- havePrevValue = trackingCurrentValue;
+ PrevLastUseMI = MI;
}
}
- RS->forward(MI);
+ }
+ // If this is the last use of the scratch, stop tracking it. The
+ // last use will be a kill operand in an instruction that does
+ // not also define the scratch register.
+ if (isKillInsn && !isDefInsn) {
+ CurrentVirtReg = 0;
+ havePrevValue = trackingCurrentValue;
+ }
+ // Similarly, notice if instruction clobbered the value in the
+ // register we're tracking for possible later reuse. This is noted
+ // above, but enforced here since the value is still live while we
+ // process the rest of the operands of the instruction.
+ if (clobbersScratchReg) {
+ havePrevValue = false;
+ CurrentScratchReg = 0;
+ }
+ if (DoIncr) {
+ RS->forward(I);
+ ++I;
+ }
}
}
}
Modified: llvm/branches/Apple/Leela/lib/CodeGen/RegisterScavenging.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/CodeGen/RegisterScavenging.cpp?rev=84822&r1=84821&r2=84822&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/CodeGen/RegisterScavenging.cpp (original)
+++ llvm/branches/Apple/Leela/lib/CodeGen/RegisterScavenging.cpp Wed Oct 21 20:24:25 2009
@@ -310,6 +310,8 @@
// Restore the scavenged register before its use (or first terminator).
TII->loadRegFromStackSlot(*MBB, UseMI, SReg, ScavengingFrameIndex, RC);
+ II = prior(UseMI);
+ TRI->eliminateFrameIndex(II, SPAdj, NULL, this);
}
ScavengeRestore = prior(UseMI);
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/ARMAddressingModes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/ARMAddressingModes.h?rev=84822&r1=84821&r2=84822&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/ARMAddressingModes.h (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/ARMAddressingModes.h Wed Oct 21 20:24:25 2009
@@ -342,6 +342,66 @@
return -1;
}
+ static inline unsigned getT2SOImmValRotate(unsigned V) {
+ if ((V & ~255U) == 0) return 0;
+ // Use CTZ to compute the rotate amount.
+ unsigned RotAmt = CountTrailingZeros_32(V);
+ return (32 - RotAmt) & 31;
+ }
+
+ static inline bool isT2SOImmTwoPartVal (unsigned Imm) {
+ unsigned V = Imm;
+ // Passing values can be any combination of splat values and shifter
+ // values. If this can be handled with a single shifter or splat, bail
+ // out. Those should be handled directly, not with a two-part val.
+ if (getT2SOImmValSplatVal(V) != -1)
+ return false;
+ V = rotr32 (~255U, getT2SOImmValRotate(V)) & V;
+ if (V == 0)
+ return false;
+
+ // If this can be handled as an immediate, accept.
+ if (getT2SOImmVal(V) != -1) return true;
+
+ // Likewise, try masking out a splat value first.
+ V = Imm;
+ if (getT2SOImmValSplatVal(V & 0xff00ff00U) != -1)
+ V &= ~0xff00ff00U;
+ else if (getT2SOImmValSplatVal(V & 0x00ff00ffU) != -1)
+ V &= ~0x00ff00ffU;
+ // If what's left can be handled as an immediate, accept.
+ if (getT2SOImmVal(V) != -1) return true;
+
+ // Otherwise, do not accept.
+ return false;
+ }
+
+ static inline unsigned getT2SOImmTwoPartFirst(unsigned Imm) {
+ assert (isT2SOImmTwoPartVal(Imm) &&
+ "Immedate cannot be encoded as two part immediate!");
+ // Try a shifter operand as one part
+ unsigned V = rotr32 (~255, getT2SOImmValRotate(Imm)) & Imm;
+ // If the rest is encodable as an immediate, then return it.
+ if (getT2SOImmVal(V) != -1) return V;
+
+ // Try masking out a splat value first.
+ if (getT2SOImmValSplatVal(Imm & 0xff00ff00U) != -1)
+ return Imm & 0xff00ff00U;
+
+ // The other splat is all that's left as an option.
+ assert (getT2SOImmValSplatVal(Imm & 0x00ff00ffU) != -1);
+ return Imm & 0x00ff00ffU;
+ }
+
+ static inline unsigned getT2SOImmTwoPartSecond(unsigned Imm) {
+ // Mask out the first hunk
+ Imm ^= getT2SOImmTwoPartFirst(Imm);
+ // Return what's left
+ assert (getT2SOImmVal(Imm) != -1 &&
+ "Unable to encode second part of T2 two part SO immediate");
+ return Imm;
+ }
+
//===--------------------------------------------------------------------===//
// Addressing Mode #2
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/ARMBaseRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=84822&r1=84821&r2=84822&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/ARMBaseRegisterInfo.cpp Wed Oct 21 20:24:25 2009
@@ -36,8 +36,18 @@
#include "llvm/Target/TargetOptions.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/SmallVector.h"
+#include "llvm/Support/CommandLine.h"
using namespace llvm;
+static cl::opt<bool>
+ScavengeFrameIndexVals("arm-virtual-frame-index-vals", cl::Hidden,
+ cl::init(false),
+ cl::desc("Resolve frame index values via scavenging in PEI"));
+
+static cl::opt<bool>
+ReuseFrameIndexVals("arm-reuse-frame-index-vals", cl::Hidden, cl::init(false),
+ cl::desc("Reuse repeated frame index values"));
+
unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum,
bool *isSPVFP) {
if (isSPVFP)
@@ -934,9 +944,10 @@
requiresRegisterScavenging(const MachineFunction &MF) const {
return true;
}
+
bool ARMBaseRegisterInfo::
requiresFrameIndexScavenging(const MachineFunction &MF) const {
- return true;
+ return ScavengeFrameIndexVals;
}
// hasReservedCallFrame - Under normal circumstances, when a frame pointer is
@@ -1014,6 +1025,17 @@
MBB.erase(I);
}
+/// findScratchRegister - Find a 'free' ARM register. If register scavenger
+/// is not being used, R12 is available. Otherwise, try for a call-clobbered
+/// register first and then a spilled callee-saved register if that fails.
+static
+unsigned findScratchRegister(RegScavenger *RS, const TargetRegisterClass *RC,
+ ARMFunctionInfo *AFI) {
+ unsigned Reg = RS ? RS->FindUnusedReg(RC) : (unsigned) ARM::R12;
+ assert(!AFI->isThumb1OnlyFunction());
+ return Reg;
+}
+
unsigned
ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
int SPAdj, int *Value,
@@ -1077,8 +1099,19 @@
// Must be addrmode4.
MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false);
else {
- ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass);
- *Value = Offset;
+ if (!ScavengeFrameIndexVals) {
+ // Insert a set of r12 with the full address: r12 = sp + offset
+ // If the offset we have is too large to fit into the instruction, we need
+ // to form it with a series of ADDri's. Do this by taking 8-bit chunks
+ // out of 'Offset'.
+ ScratchReg = findScratchRegister(RS, ARM::GPRRegisterClass, AFI);
+ if (ScratchReg == 0)
+ // No register is "free". Scavenge a register.
+ ScratchReg = RS->scavengeRegister(ARM::GPRRegisterClass, II, SPAdj);
+ } else {
+ ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass);
+ *Value = Offset;
+ }
if (!AFI->isThumbFunction())
emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
Offset, Pred, PredReg, TII);
@@ -1088,6 +1121,8 @@
Offset, Pred, PredReg, TII);
}
MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
+ if (!ReuseFrameIndexVals || !ScavengeFrameIndexVals)
+ ScratchReg = 0;
}
return ScratchReg;
}
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrInfo.td?rev=84822&r1=84821&r2=84822&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrInfo.td Wed Oct 21 20:24:25 2009
@@ -1518,6 +1518,12 @@
def : ARMPat<(xor GPR:$LHS, so_imm2part:$RHS),
(EORri (EORri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
(so_imm2part_2 imm:$RHS))>;
+def : ARMPat<(add GPR:$LHS, so_imm2part:$RHS),
+ (ADDri (ADDri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
+ (so_imm2part_2 imm:$RHS))>;
+def : ARMPat<(sub GPR:$LHS, so_imm2part:$RHS),
+ (SUBri (SUBri GPR:$LHS, (so_imm2part_1 imm:$RHS)),
+ (so_imm2part_2 imm:$RHS))>;
// 32-bit immediate using movw + movt.
// This is a single pseudo instruction to make it re-materializable. Remove
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrThumb2.td?rev=84822&r1=84821&r2=84822&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrThumb2.td Wed Oct 21 20:24:25 2009
@@ -69,6 +69,25 @@
return ARM_AM::getT2SOImmVal(-((int)N->getZExtValue())) != -1;
}], t2_so_imm_neg_XFORM>;
+// Break t2_so_imm's up into two pieces. This handles immediates with up to 16
+// bits set in them. This uses t2_so_imm2part to match and t2_so_imm2part_[12]
+// to get the first/second pieces.
+def t2_so_imm2part : Operand<i32>,
+ PatLeaf<(imm), [{
+ return ARM_AM::isT2SOImmTwoPartVal((unsigned)N->getZExtValue());
+ }]> {
+}
+
+def t2_so_imm2part_1 : SDNodeXForm<imm, [{
+ unsigned V = ARM_AM::getT2SOImmTwoPartFirst((unsigned)N->getZExtValue());
+ return CurDAG->getTargetConstant(V, MVT::i32);
+}]>;
+
+def t2_so_imm2part_2 : SDNodeXForm<imm, [{
+ unsigned V = ARM_AM::getT2SOImmTwoPartSecond((unsigned)N->getZExtValue());
+ return CurDAG->getTargetConstant(V, MVT::i32);
+}]>;
+
/// imm1_31 predicate - True if the 32-bit immediate is in the range [1,31].
def imm1_31 : PatLeaf<(i32 imm), [{
return (int32_t)N->getZExtValue() >= 1 && (int32_t)N->getZExtValue() < 32;
@@ -1123,6 +1142,20 @@
// Non-Instruction Patterns
//
+// Two piece so_imms.
+def : T2Pat<(or GPR:$LHS, t2_so_imm2part:$RHS),
+ (t2ORRri (t2ORRri GPR:$LHS, (t2_so_imm2part_1 imm:$RHS)),
+ (t2_so_imm2part_2 imm:$RHS))>;
+def : T2Pat<(xor GPR:$LHS, t2_so_imm2part:$RHS),
+ (t2EORri (t2EORri GPR:$LHS, (t2_so_imm2part_1 imm:$RHS)),
+ (t2_so_imm2part_2 imm:$RHS))>;
+def : T2Pat<(add GPR:$LHS, t2_so_imm2part:$RHS),
+ (t2ADDri (t2ADDri GPR:$LHS, (t2_so_imm2part_1 imm:$RHS)),
+ (t2_so_imm2part_2 imm:$RHS))>;
+def : T2Pat<(sub GPR:$LHS, t2_so_imm2part:$RHS),
+ (t2SUBri (t2SUBri GPR:$LHS, (t2_so_imm2part_1 imm:$RHS)),
+ (t2_so_imm2part_2 imm:$RHS))>;
+
// ConstantPool, GlobalAddress, and JumpTable
def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>;
def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>;
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/Thumb1RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/Thumb1RegisterInfo.cpp?rev=84822&r1=84821&r2=84822&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/Thumb1RegisterInfo.cpp (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/Thumb1RegisterInfo.cpp Wed Oct 21 20:24:25 2009
@@ -77,6 +77,18 @@
return TargetRegisterInfo::getPhysicalRegisterRegClass(Reg, VT);
}
+bool
+Thumb1RegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
+ return true;
+}
+
+bool
+Thumb1RegisterInfo::requiresFrameIndexScavenging(const MachineFunction &MF)
+ const {
+ return true;
+}
+
+
bool Thumb1RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
const MachineFrameInfo *FFI = MF.getFrameInfo();
unsigned CFSize = FFI->getMaxCallFrameSize();
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/Thumb1RegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/Thumb1RegisterInfo.h?rev=84822&r1=84821&r2=84822&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/Thumb1RegisterInfo.h (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/Thumb1RegisterInfo.h Wed Oct 21 20:24:25 2009
@@ -40,6 +40,9 @@
const TargetRegisterClass *
getPhysicalRegisterRegClass(unsigned Reg, EVT VT = MVT::Other) const;
+ bool requiresRegisterScavenging(const MachineFunction &MF) const;
+ bool requiresFrameIndexScavenging(const MachineFunction &MF) const;
+
bool hasReservedCallFrame(MachineFunction &MF) const;
void eliminateCallFramePseudoInstr(MachineFunction &MF,
Modified: llvm/branches/Apple/Leela/test/CodeGen/Thumb2/thumb2-mov.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/test/CodeGen/Thumb2/thumb2-mov.ll?rev=84822&r1=84821&r2=84822&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/test/CodeGen/Thumb2/thumb2-mov.ll (original)
+++ llvm/branches/Apple/Leela/test/CodeGen/Thumb2/thumb2-mov.ll Wed Oct 21 20:24:25 2009
@@ -10,29 +10,32 @@
ret i32 %ret
}
-define i32 @t2_const_var2_1_fail_1(i32 %lhs) {
-;CHECK: t2_const_var2_1_fail_1:
-;CHECK: movt
+define i32 @t2_const_var2_1_ok_2(i32 %lhs) {
+;CHECK: t2_const_var2_1_ok_2:
+;CHECK: #11206656
+;CHECK: #187
%ret = add i32 %lhs, 11206843 ; 0x00ab00bb
ret i32 %ret
}
-define i32 @t2_const_var2_1_fail_2(i32 %lhs) {
-;CHECK: t2_const_var2_1_fail_2:
-;CHECK: movt
+define i32 @t2_const_var2_1_ok_3(i32 %lhs) {
+;CHECK: t2_const_var2_1_ok_3:
+;CHECK: #11206827
+;CHECK: #16777216
%ret = add i32 %lhs, 27984043 ; 0x01ab00ab
ret i32 %ret
}
-define i32 @t2_const_var2_1_fail_3(i32 %lhs) {
-;CHECK: t2_const_var2_1_fail_3:
-;CHECK: movt
+define i32 @t2_const_var2_1_ok_4(i32 %lhs) {
+;CHECK: t2_const_var2_1_ok_4:
+;CHECK: #16777472
+;CHECK: #11206827
%ret = add i32 %lhs, 27984299 ; 0x01ab01ab
ret i32 %ret
}
-define i32 @t2_const_var2_1_fail_4(i32 %lhs) {
-;CHECK: t2_const_var2_1_fail_4:
+define i32 @t2_const_var2_1_fail_1(i32 %lhs) {
+;CHECK: t2_const_var2_1_fail_1:
;CHECK: movt
%ret = add i32 %lhs, 28027649 ; 0x01abab01
ret i32 %ret
@@ -46,29 +49,31 @@
ret i32 %ret
}
-define i32 @t2_const_var2_2_fail_1(i32 %lhs) {
-;CHECK: t2_const_var2_2_fail_1:
-;CHECK: movt
+define i32 @t2_const_var2_2_ok_2(i32 %lhs) {
+;CHECK: t2_const_var2_2_ok_2:
+;CHECK: #-1426063360
+;CHECK: #47616
%ret = add i32 %lhs, 2868951552 ; 0xab00ba00
ret i32 %ret
}
-define i32 @t2_const_var2_2_fail_2(i32 %lhs) {
-;CHECK: t2_const_var2_2_fail_2:
-;CHECK: movt
+define i32 @t2_const_var2_2_ok_3(i32 %lhs) {
+;CHECK: t2_const_var2_2_ok_3:
+;CHECK: #-1426019584
%ret = add i32 %lhs, 2868947728 ; 0xab00ab10
ret i32 %ret
}
-define i32 @t2_const_var2_2_fail_3(i32 %lhs) {
-;CHECK: t2_const_var2_2_fail_3:
-;CHECK: movt
+define i32 @t2_const_var2_2_ok_4(i32 %lhs) {
+;CHECK: t2_const_var2_2_ok_4:
+;CHECK: #-1426019584
+;CHECK: #1048592
%ret = add i32 %lhs, 2869996304 ; 0xab10ab10
ret i32 %ret
}
-define i32 @t2_const_var2_2_fail_4(i32 %lhs) {
-;CHECK: t2_const_var2_2_fail_4:
+define i32 @t2_const_var2_2_fail_1(i32 %lhs) {
+;CHECK: t2_const_var2_2_fail_1:
;CHECK: movt
%ret = add i32 %lhs, 279685904 ; 0x10abab10
ret i32 %ret
@@ -125,9 +130,10 @@
ret i32 %ret
}
-define i32 @t2_const_var3_2_fail_1(i32 %lhs) {
-;CHECK: t2_const_var3_2_fail_1:
-;CHECK: movt
+define i32 @t2_const_var3_2_ok_2(i32 %lhs) {
+;CHECK: t2_const_var3_2_ok_2:
+;CHECK: #2097152
+;CHECK: #1843200
%ret = add i32 %lhs, 3940352 ; 0b00000000001111000010000000000000
ret i32 %ret
}
Modified: llvm/branches/Apple/Leela/test/CodeGen/Thumb2/thumb2-mov2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/test/CodeGen/Thumb2/thumb2-mov2.ll?rev=84822&r1=84821&r2=84822&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/test/CodeGen/Thumb2/thumb2-mov2.ll (original)
+++ llvm/branches/Apple/Leela/test/CodeGen/Thumb2/thumb2-mov2.ll Wed Oct 21 20:24:25 2009
@@ -67,10 +67,10 @@
define i32 @t2MOVTi16_test_nomatch_1(i32 %a) {
; CHECK: t2MOVTi16_test_nomatch_1:
-; CHECK: movw r1, #16384
-; CHECK-NEXT: movt r1, #154
+; CHECK: #8388608
; CHECK: movw r1, #65535
; CHECK-NEXT: movt r1, #154
+; CHECK: #1720320
%1 = shl i32 255, 8
%2 = shl i32 1234, 8
%3 = or i32 %1, 255 ; This give us 0xFFFF in %3
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