[llvm-branch-commits] [llvm-branch] r89813 - in /llvm/branches/Apple/Zoidberg: lib/Target/PowerPC/PPCFrameInfo.h lib/Target/PowerPC/PPCISelDAGToDAG.cpp lib/Target/PowerPC/PPCISelLowering.cpp lib/Target/PowerPC/PPCRegisterInfo.cpp test/CodeGen/PowerPC/Frames-alloca.ll test/CodeGen/PowerPC/Frames-large.ll test/CodeGen/PowerPC/Frames-small.ll test/CodeGen/PowerPC/ppc-prologue.ll
Dale Johannesen
dalej at apple.com
Tue Nov 24 15:22:50 PST 2009
Author: johannes
Date: Tue Nov 24 17:22:47 2009
New Revision: 89813
URL: http://llvm.org/viewvc/llvm-project?rev=89813&view=rev
Log:
$ svn merge -c 89724 https://dalej@llvm.org/svn/llvm-project/llvm/trunk
--- Merging r89724 into '.':
U lib/Target/PowerPC/PPCRegisterInfo.cpp
U lib/Target/PowerPC/PPCISelLowering.cpp
U lib/Target/PowerPC/PPCISelDAGToDAG.cpp
$ svn merge -c 89811 https://dalej@llvm.org/svn/llvm-project/llvm/trunk
--- Merging r89811 into '.':
U test/CodeGen/PowerPC/ppc-prologue.ll
U test/CodeGen/PowerPC/Frames-large.ll
U test/CodeGen/PowerPC/Frames-alloca.ll
U test/CodeGen/PowerPC/Frames-small.ll
U lib/Target/PowerPC/PPCFrameInfo.h
G lib/Target/PowerPC/PPCRegisterInfo.cpp
Modified:
llvm/branches/Apple/Zoidberg/lib/Target/PowerPC/PPCFrameInfo.h
llvm/branches/Apple/Zoidberg/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
llvm/branches/Apple/Zoidberg/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/branches/Apple/Zoidberg/lib/Target/PowerPC/PPCRegisterInfo.cpp
llvm/branches/Apple/Zoidberg/test/CodeGen/PowerPC/Frames-alloca.ll
llvm/branches/Apple/Zoidberg/test/CodeGen/PowerPC/Frames-large.ll
llvm/branches/Apple/Zoidberg/test/CodeGen/PowerPC/Frames-small.ll
llvm/branches/Apple/Zoidberg/test/CodeGen/PowerPC/ppc-prologue.ll
Modified: llvm/branches/Apple/Zoidberg/lib/Target/PowerPC/PPCFrameInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Zoidberg/lib/Target/PowerPC/PPCFrameInfo.h?rev=89813&r1=89812&r2=89813&view=diff
==============================================================================
--- llvm/branches/Apple/Zoidberg/lib/Target/PowerPC/PPCFrameInfo.h (original)
+++ llvm/branches/Apple/Zoidberg/lib/Target/PowerPC/PPCFrameInfo.h Tue Nov 24 17:22:47 2009
@@ -42,11 +42,12 @@
/// frame pointer.
static unsigned getFramePointerSaveOffset(bool isPPC64, bool isDarwinABI) {
// For the Darwin ABI:
- // Use the TOC save slot in the PowerPC linkage area for saving the frame
- // pointer (if needed.) LLVM does not generate code that uses the TOC (R2
- // is treated as a caller saved register.)
+ // We cannot use the TOC save slot (offset +20) in the PowerPC linkage area
+ // for saving the frame pointer (if needed.) While the published ABI has
+ // not used this slot since at least MacOSX 10.2, there is older code
+ // around that does use it, and that needs to continue to work.
if (isDarwinABI)
- return isPPC64 ? 40 : 20;
+ return isPPC64 ? -8U : -4U;
// SVR4 ABI: First slot in the general register save area.
return -4U;
@@ -90,6 +91,17 @@
// With the SVR4 ABI, callee-saved registers have fixed offsets on the stack.
const SpillSlot *
getCalleeSavedSpillSlots(unsigned &NumEntries) const {
+ if (TM.getSubtarget<PPCSubtarget>().isDarwinABI()) {
+ NumEntries = 1;
+ if (TM.getSubtarget<PPCSubtarget>().isPPC64()) {
+ static const SpillSlot darwin64Offsets[] = {PPC::X31, -8};
+ return darwin64Offsets;
+ } else {
+ static const SpillSlot darwinOffsets[] = {PPC::R31, -4};
+ return darwinOffsets;
+ }
+ }
+
// Early exit if not using the SVR4 ABI.
if (!TM.getSubtarget<PPCSubtarget>().isSVR4ABI()) {
NumEntries = 0;
Modified: llvm/branches/Apple/Zoidberg/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Zoidberg/lib/Target/PowerPC/PPCISelDAGToDAG.cpp?rev=89813&r1=89812&r2=89813&view=diff
==============================================================================
--- llvm/branches/Apple/Zoidberg/lib/Target/PowerPC/PPCISelDAGToDAG.cpp (original)
+++ llvm/branches/Apple/Zoidberg/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Tue Nov 24 17:22:47 2009
@@ -86,7 +86,7 @@
/// isRotateAndMask - Returns true if Mask and Shift can be folded into a
/// rotate and mask opcode and mask operation.
- static bool isRotateAndMask(SDNode *N, unsigned Mask, bool IsShiftMask,
+ static bool isRotateAndMask(SDNode *N, unsigned Mask, bool isShiftMask,
unsigned &SH, unsigned &MB, unsigned &ME);
/// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
@@ -358,7 +358,7 @@
}
bool PPCDAGToDAGISel::isRotateAndMask(SDNode *N, unsigned Mask,
- bool IsShiftMask, unsigned &SH,
+ bool isShiftMask, unsigned &SH,
unsigned &MB, unsigned &ME) {
// Don't even go down this path for i64, since different logic will be
// necessary for rldicl/rldicr/rldimi.
@@ -374,12 +374,12 @@
if (Opcode == ISD::SHL) {
// apply shift left to mask if it comes first
- if (IsShiftMask) Mask = Mask << Shift;
+ if (isShiftMask) Mask = Mask << Shift;
// determine which bits are made indeterminant by shift
Indeterminant = ~(0xFFFFFFFFu << Shift);
} else if (Opcode == ISD::SRL) {
// apply shift right to mask if it comes first
- if (IsShiftMask) Mask = Mask >> Shift;
+ if (isShiftMask) Mask = Mask >> Shift;
// determine which bits are made indeterminant by shift
Indeterminant = ~(0xFFFFFFFFu >> Shift);
// adjust for the left rotate
Modified: llvm/branches/Apple/Zoidberg/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Zoidberg/lib/Target/PowerPC/PPCISelLowering.cpp?rev=89813&r1=89812&r2=89813&view=diff
==============================================================================
--- llvm/branches/Apple/Zoidberg/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/branches/Apple/Zoidberg/lib/Target/PowerPC/PPCISelLowering.cpp Tue Nov 24 17:22:47 2009
@@ -2176,10 +2176,10 @@
/// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
/// adjusted to accomodate the arguments for the tailcall.
-static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool IsTailCall,
+static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
unsigned ParamSize) {
- if (!IsTailCall) return 0;
+ if (!isTailCall) return 0;
PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
unsigned CallerMinReservedArea = FI->getMinReservedArea();
@@ -3189,8 +3189,8 @@
EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
// Construct the stack pointer operand.
- bool IsPPC64 = Subtarget.isPPC64();
- unsigned SP = IsPPC64 ? PPC::X1 : PPC::R1;
+ bool isPPC64 = Subtarget.isPPC64();
+ unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
SDValue StackPtr = DAG.getRegister(SP, PtrVT);
// Get the operands for the STACKRESTORE.
@@ -3212,7 +3212,7 @@
SDValue
PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
MachineFunction &MF = DAG.getMachineFunction();
- bool IsPPC64 = PPCSubTarget.isPPC64();
+ bool isPPC64 = PPCSubTarget.isPPC64();
bool isDarwinABI = PPCSubTarget.isDarwinABI();
EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
@@ -3224,9 +3224,9 @@
// If the frame pointer save index hasn't been defined yet.
if (!RASI) {
// Find out what the fix offset of the frame pointer save area.
- int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, isDarwinABI);
+ int LROffset = PPCFrameInfo::getReturnSaveOffset(isPPC64, isDarwinABI);
// Allocate the frame index for frame pointer save area.
- RASI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, LROffset,
+ RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset,
true, false);
// Save the result.
FI->setReturnAddrSaveIndex(RASI);
@@ -3237,7 +3237,7 @@
SDValue
PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
MachineFunction &MF = DAG.getMachineFunction();
- bool IsPPC64 = PPCSubTarget.isPPC64();
+ bool isPPC64 = PPCSubTarget.isPPC64();
bool isDarwinABI = PPCSubTarget.isDarwinABI();
EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
@@ -3249,11 +3249,11 @@
// If the frame pointer save index hasn't been defined yet.
if (!FPSI) {
// Find out what the fix offset of the frame pointer save area.
- int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64,
+ int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(isPPC64,
isDarwinABI);
// Allocate the frame index for frame pointer save area.
- FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset,
+ FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset,
true, false);
// Save the result.
FI->setFramePointerSaveIndex(FPSI);
Modified: llvm/branches/Apple/Zoidberg/lib/Target/PowerPC/PPCRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Zoidberg/lib/Target/PowerPC/PPCRegisterInfo.cpp?rev=89813&r1=89812&r2=89813&view=diff
==============================================================================
--- llvm/branches/Apple/Zoidberg/lib/Target/PowerPC/PPCRegisterInfo.cpp (original)
+++ llvm/branches/Apple/Zoidberg/lib/Target/PowerPC/PPCRegisterInfo.cpp Tue Nov 24 17:22:47 2009
@@ -1032,18 +1032,17 @@
// Save R31 if necessary
int FPSI = FI->getFramePointerSaveIndex();
- bool IsPPC64 = Subtarget.isPPC64();
- bool IsSVR4ABI = Subtarget.isSVR4ABI();
+ bool isPPC64 = Subtarget.isPPC64();
bool isDarwinABI = Subtarget.isDarwinABI();
MachineFrameInfo *MFI = MF.getFrameInfo();
// If the frame pointer save index hasn't been defined yet.
- if (!FPSI && needsFP(MF) && IsSVR4ABI) {
+ if (!FPSI && needsFP(MF)) {
// Find out what the fix offset of the frame pointer save area.
- int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64,
+ int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(isPPC64,
isDarwinABI);
// Allocate the frame index for frame pointer save area.
- FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset,
+ FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset,
true, false);
// Save the result.
FI->setFramePointerSaveIndex(FPSI);
@@ -1067,7 +1066,7 @@
if (needsFP(MF) || spillsCR(MF)) {
const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
- const TargetRegisterClass *RC = IsPPC64 ? G8RC : GPRC;
+ const TargetRegisterClass *RC = isPPC64 ? G8RC : GPRC;
RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
RC->getAlignment(),
false));
@@ -1297,7 +1296,7 @@
int NegFrameSize = -FrameSize;
// Get processor type.
- bool IsPPC64 = Subtarget.isPPC64();
+ bool isPPC64 = Subtarget.isPPC64();
// Get operating system
bool isDarwinABI = Subtarget.isDarwinABI();
// Check if the link register (LR) must be saved.
@@ -1306,7 +1305,7 @@
// Do we have a frame pointer for this function?
bool HasFP = hasFP(MF) && FrameSize;
- int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, isDarwinABI);
+ int LROffset = PPCFrameInfo::getReturnSaveOffset(isPPC64, isDarwinABI);
int FPOffset = 0;
if (HasFP) {
@@ -1316,11 +1315,11 @@
assert(FPIndex && "No Frame Pointer Save Slot!");
FPOffset = FFI->getObjectOffset(FPIndex);
} else {
- FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, isDarwinABI);
+ FPOffset = PPCFrameInfo::getFramePointerSaveOffset(isPPC64, isDarwinABI);
}
}
- if (IsPPC64) {
+ if (isPPC64) {
if (MustSaveLR)
BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR8), PPC::X0);
@@ -1361,7 +1360,7 @@
// Adjust stack pointer: r1 += NegFrameSize.
// If there is a preferred stack alignment, align R1 now
- if (!IsPPC64) {
+ if (!isPPC64) {
// PPC32.
if (ALIGN_STACK && MaxAlign > TargetAlign) {
assert(isPowerOf2_32(MaxAlign)&&isInt16(MaxAlign)&&"Invalid alignment!");
@@ -1444,19 +1443,19 @@
MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize);
Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc));
} else {
- MachineLocation SP(IsPPC64 ? PPC::X31 : PPC::R31);
+ MachineLocation SP(isPPC64 ? PPC::X31 : PPC::R31);
Moves.push_back(MachineMove(FrameLabelId, SP, SP));
}
if (HasFP) {
MachineLocation FPDst(MachineLocation::VirtualFP, FPOffset);
- MachineLocation FPSrc(IsPPC64 ? PPC::X31 : PPC::R31);
+ MachineLocation FPSrc(isPPC64 ? PPC::X31 : PPC::R31);
Moves.push_back(MachineMove(FrameLabelId, FPDst, FPSrc));
}
if (MustSaveLR) {
MachineLocation LRDst(MachineLocation::VirtualFP, LROffset);
- MachineLocation LRSrc(IsPPC64 ? PPC::LR8 : PPC::LR);
+ MachineLocation LRSrc(isPPC64 ? PPC::LR8 : PPC::LR);
Moves.push_back(MachineMove(FrameLabelId, LRDst, LRSrc));
}
}
@@ -1465,7 +1464,7 @@
// If there is a frame pointer, copy R1 into R31
if (HasFP) {
- if (!IsPPC64) {
+ if (!isPPC64) {
BuildMI(MBB, MBBI, dl, TII.get(PPC::OR), PPC::R31)
.addReg(PPC::R1)
.addReg(PPC::R1);
@@ -1481,8 +1480,8 @@
// Mark effective beginning of when frame pointer is ready.
BuildMI(MBB, MBBI, dl, TII.get(PPC::DBG_LABEL)).addImm(ReadyLabelId);
- MachineLocation FPDst(HasFP ? (IsPPC64 ? PPC::X31 : PPC::R31) :
- (IsPPC64 ? PPC::X1 : PPC::R1));
+ MachineLocation FPDst(HasFP ? (isPPC64 ? PPC::X31 : PPC::R31) :
+ (isPPC64 ? PPC::X1 : PPC::R1));
MachineLocation FPSrc(MachineLocation::VirtualFP);
Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc));
}
@@ -1528,7 +1527,7 @@
int FrameSize = MFI->getStackSize();
// Get processor type.
- bool IsPPC64 = Subtarget.isPPC64();
+ bool isPPC64 = Subtarget.isPPC64();
// Get operating system
bool isDarwinABI = Subtarget.isDarwinABI();
// Check if the link register (LR) has been saved.
@@ -1537,7 +1536,7 @@
// Do we have a frame pointer for this function?
bool HasFP = hasFP(MF) && FrameSize;
- int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, isDarwinABI);
+ int LROffset = PPCFrameInfo::getReturnSaveOffset(isPPC64, isDarwinABI);
int FPOffset = 0;
if (HasFP) {
@@ -1547,7 +1546,7 @@
assert(FPIndex && "No Frame Pointer Save Slot!");
FPOffset = FFI->getObjectOffset(FPIndex);
} else {
- FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, isDarwinABI);
+ FPOffset = PPCFrameInfo::getFramePointerSaveOffset(isPPC64, isDarwinABI);
}
}
@@ -1575,7 +1574,7 @@
if (FrameSize) {
// The loaded (or persistent) stack pointer value is offset by the 'stwu'
// on entry to the function. Add this offset back now.
- if (!IsPPC64) {
+ if (!isPPC64) {
// If this function contained a fastcc call and PerformTailCallOpt is
// enabled (=> hasFastCall()==true) the fastcc call might contain a tail
// call which invalidates the stack pointer value in SP(0). So we use the
@@ -1629,7 +1628,7 @@
}
}
- if (IsPPC64) {
+ if (isPPC64) {
if (MustSaveLR)
BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X0)
.addImm(LROffset/4).addReg(PPC::X1);
@@ -1659,13 +1658,13 @@
MF.getFunction()->getCallingConv() == CallingConv::Fast) {
PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
unsigned CallerAllocatedAmt = FI->getMinReservedArea();
- unsigned StackReg = IsPPC64 ? PPC::X1 : PPC::R1;
- unsigned FPReg = IsPPC64 ? PPC::X31 : PPC::R31;
- unsigned TmpReg = IsPPC64 ? PPC::X0 : PPC::R0;
- unsigned ADDIInstr = IsPPC64 ? PPC::ADDI8 : PPC::ADDI;
- unsigned ADDInstr = IsPPC64 ? PPC::ADD8 : PPC::ADD4;
- unsigned LISInstr = IsPPC64 ? PPC::LIS8 : PPC::LIS;
- unsigned ORIInstr = IsPPC64 ? PPC::ORI8 : PPC::ORI;
+ unsigned StackReg = isPPC64 ? PPC::X1 : PPC::R1;
+ unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31;
+ unsigned TmpReg = isPPC64 ? PPC::X0 : PPC::R0;
+ unsigned ADDIInstr = isPPC64 ? PPC::ADDI8 : PPC::ADDI;
+ unsigned ADDInstr = isPPC64 ? PPC::ADD8 : PPC::ADD4;
+ unsigned LISInstr = isPPC64 ? PPC::LIS8 : PPC::LIS;
+ unsigned ORIInstr = isPPC64 ? PPC::ORI8 : PPC::ORI;
if (CallerAllocatedAmt && isInt16(CallerAllocatedAmt)) {
BuildMI(MBB, MBBI, dl, TII.get(ADDIInstr), StackReg)
Modified: llvm/branches/Apple/Zoidberg/test/CodeGen/PowerPC/Frames-alloca.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Zoidberg/test/CodeGen/PowerPC/Frames-alloca.ll?rev=89813&r1=89812&r2=89813&view=diff
==============================================================================
--- llvm/branches/Apple/Zoidberg/test/CodeGen/PowerPC/Frames-alloca.ll (original)
+++ llvm/branches/Apple/Zoidberg/test/CodeGen/PowerPC/Frames-alloca.ll Tue Nov 24 17:22:47 2009
@@ -6,23 +6,23 @@
; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -enable-ppc32-regscavenger | FileCheck %s -check-prefix=PPC32-RS
; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim -enable-ppc32-regscavenger | FileCheck %s -check-prefix=PPC32-RS-NOFP
-; CHECK-PPC32: stw r31, 20(r1)
+; CHECK-PPC32: stw r31, -4(r1)
; CHECK-PPC32: lwz r1, 0(r1)
-; CHECK-PPC32: lwz r31, 20(r1)
-; CHECK-PPC32-NOFP: stw r31, 20(r1)
+; CHECK-PPC32: lwz r31, -4(r1)
+; CHECK-PPC32-NOFP: stw r31, -4(r1)
; CHECK-PPC32-NOFP: lwz r1, 0(r1)
-; CHECK-PPC32-NOFP: lwz r31, 20(r1)
+; CHECK-PPC32-NOFP: lwz r31, -4(r1)
; CHECK-PPC32-RS: stwu r1, -80(r1)
; CHECK-PPC32-RS-NOFP: stwu r1, -80(r1)
-; CHECK-PPC64: std r31, 40(r1)
-; CHECK-PPC64: stdu r1, -112(r1)
+; CHECK-PPC64: std r31, -8(r1)
+; CHECK-PPC64: stdu r1, -128(r1)
; CHECK-PPC64: ld r1, 0(r1)
-; CHECK-PPC64: ld r31, 40(r1)
-; CHECK-PPC64-NOFP: std r31, 40(r1)
-; CHECK-PPC64-NOFP: stdu r1, -112(r1)
+; CHECK-PPC64: ld r31, -8(r1)
+; CHECK-PPC64-NOFP: std r31, -8(r1)
+; CHECK-PPC64-NOFP: stdu r1, -128(r1)
; CHECK-PPC64-NOFP: ld r1, 0(r1)
-; CHECK-PPC64-NOFP: ld r31, 40(r1)
+; CHECK-PPC64-NOFP: ld r31, -8(r1)
define i32* @f1(i32 %n) {
%tmp = alloca i32, i32 %n ; <i32*> [#uses=1]
Modified: llvm/branches/Apple/Zoidberg/test/CodeGen/PowerPC/Frames-large.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Zoidberg/test/CodeGen/PowerPC/Frames-large.ll?rev=89813&r1=89812&r2=89813&view=diff
==============================================================================
--- llvm/branches/Apple/Zoidberg/test/CodeGen/PowerPC/Frames-large.ll (original)
+++ llvm/branches/Apple/Zoidberg/test/CodeGen/PowerPC/Frames-large.ll Tue Nov 24 17:22:47 2009
@@ -22,13 +22,13 @@
; PPC32-NOFP: blr
; PPC32-FP: _f1:
-; PPC32-FP: stw r31, 20(r1)
+; PPC32-FP: stw r31, -4(r1)
; PPC32-FP: lis r0, -1
; PPC32-FP: ori r0, r0, 32704
; PPC32-FP: stwux r1, r1, r0
; ...
; PPC32-FP: lwz r1, 0(r1)
-; PPC32-FP: lwz r31, 20(r1)
+; PPC32-FP: lwz r31, -4(r1)
; PPC32-FP: blr
@@ -42,11 +42,11 @@
; PPC64-FP: _f1:
-; PPC64-FP: std r31, 40(r1)
+; PPC64-FP: std r31, -8(r1)
; PPC64-FP: lis r0, -1
-; PPC64-FP: ori r0, r0, 32656
+; PPC64-FP: ori r0, r0, 32640
; PPC64-FP: stdux r1, r1, r0
; ...
; PPC64-FP: ld r1, 0(r1)
-; PPC64-FP: ld r31, 40(r1)
+; PPC64-FP: ld r31, -8(r1)
; PPC64-FP: blr
Modified: llvm/branches/Apple/Zoidberg/test/CodeGen/PowerPC/Frames-small.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Zoidberg/test/CodeGen/PowerPC/Frames-small.ll?rev=89813&r1=89812&r2=89813&view=diff
==============================================================================
--- llvm/branches/Apple/Zoidberg/test/CodeGen/PowerPC/Frames-small.ll (original)
+++ llvm/branches/Apple/Zoidberg/test/CodeGen/PowerPC/Frames-small.ll Tue Nov 24 17:22:47 2009
@@ -1,26 +1,26 @@
; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -o %t1
-; RUN not grep {stw r31, 20(r1)} %t1
+; RUN not grep {stw r31, -4(r1)} %t1
; RUN: grep {stwu r1, -16448(r1)} %t1
; RUN: grep {addi r1, r1, 16448} %t1
; RUN: llc < %s -march=ppc32 | \
-; RUN: not grep {lwz r31, 20(r1)}
+; RUN: not grep {lwz r31, -4(r1)}
; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim \
; RUN: -o %t2
-; RUN: grep {stw r31, 20(r1)} %t2
+; RUN: grep {stw r31, -4(r1)} %t2
; RUN: grep {stwu r1, -16448(r1)} %t2
; RUN: grep {addi r1, r1, 16448} %t2
-; RUN: grep {lwz r31, 20(r1)} %t2
+; RUN: grep {lwz r31, -4(r1)} %t2
; RUN: llc < %s -march=ppc64 -mtriple=powerpc-apple-darwin8 -o %t3
-; RUN: not grep {std r31, 40(r1)} %t3
+; RUN: not grep {std r31, -8(r1)} %t3
; RUN: grep {stdu r1, -16496(r1)} %t3
; RUN: grep {addi r1, r1, 16496} %t3
-; RUN: not grep {ld r31, 40(r1)} %t3
+; RUN: not grep {ld r31, -8(r1)} %t3
; RUN: llc < %s -march=ppc64 -mtriple=powerpc-apple-darwin8 -disable-fp-elim \
; RUN: -o %t4
-; RUN: grep {std r31, 40(r1)} %t4
-; RUN: grep {stdu r1, -16496(r1)} %t4
-; RUN: grep {addi r1, r1, 16496} %t4
-; RUN: grep {ld r31, 40(r1)} %t4
+; RUN: grep {std r31, -8(r1)} %t4
+; RUN: grep {stdu r1, -16512(r1)} %t4
+; RUN: grep {addi r1, r1, 16512} %t4
+; RUN: grep {ld r31, -8(r1)} %t4
define i32* @f1() {
%tmp = alloca i32, i32 4095 ; <i32*> [#uses=1]
Modified: llvm/branches/Apple/Zoidberg/test/CodeGen/PowerPC/ppc-prologue.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Zoidberg/test/CodeGen/PowerPC/ppc-prologue.ll?rev=89813&r1=89812&r2=89813&view=diff
==============================================================================
--- llvm/branches/Apple/Zoidberg/test/CodeGen/PowerPC/ppc-prologue.ll (original)
+++ llvm/branches/Apple/Zoidberg/test/CodeGen/PowerPC/ppc-prologue.ll Tue Nov 24 17:22:47 2009
@@ -2,7 +2,7 @@
define i32 @_Z4funci(i32 %a) ssp {
; CHECK: mflr r0
-; CHECK-NEXT: stw r31, 20(r1)
+; CHECK-NEXT: stw r31, -4(r1)
; CHECK-NEXT: stw r0, 8(r1)
; CHECK-NEXT: stwu r1, -80(r1)
; CHECK-NEXT: Llabel1:
More information about the llvm-branch-commits
mailing list