[llvm-branch-commits] [llvm-branch] r89727 - in /llvm/branches/Apple/Zoidberg: lib/CodeGen/MachineLICM.cpp lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrThumb.td lib/Target/ARM/ARMInstrThumb2.td lib/Target/ARM/ARMInstrVFP.td test/CodeGen/ARM/remat-2.ll test/CodeGen/Thumb2/cross-rc-coalescing-2.ll test/CodeGen/Thumb2/ldr-str-imm12.ll test/CodeGen/Thumb2/machine-licm.ll test/CodeGen/X86/2009-10-08-MachineLICMBug.ll test/CodeGen/X86/pic-load-remat.ll

Evan Cheng evan.cheng at apple.com
Mon Nov 23 17:38:56 PST 2009


Author: evancheng
Date: Mon Nov 23 19:38:56 2009
New Revision: 89727

URL: http://llvm.org/viewvc/llvm-project?rev=89727&view=rev
Log:
Merge 89440, 89478, and 89510.

Added:
    llvm/branches/Apple/Zoidberg/test/CodeGen/ARM/remat-2.ll
Modified:
    llvm/branches/Apple/Zoidberg/lib/CodeGen/MachineLICM.cpp
    llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMBaseInstrInfo.cpp
    llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMInstrInfo.td
    llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMInstrThumb.td
    llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMInstrThumb2.td
    llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMInstrVFP.td
    llvm/branches/Apple/Zoidberg/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll
    llvm/branches/Apple/Zoidberg/test/CodeGen/Thumb2/ldr-str-imm12.ll
    llvm/branches/Apple/Zoidberg/test/CodeGen/Thumb2/machine-licm.ll
    llvm/branches/Apple/Zoidberg/test/CodeGen/X86/2009-10-08-MachineLICMBug.ll
    llvm/branches/Apple/Zoidberg/test/CodeGen/X86/pic-load-remat.ll

Modified: llvm/branches/Apple/Zoidberg/lib/CodeGen/MachineLICM.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Zoidberg/lib/CodeGen/MachineLICM.cpp?rev=89727&r1=89726&r2=89727&view=diff

==============================================================================
--- llvm/branches/Apple/Zoidberg/lib/CodeGen/MachineLICM.cpp (original)
+++ llvm/branches/Apple/Zoidberg/lib/CodeGen/MachineLICM.cpp Mon Nov 23 19:38:56 2009
@@ -34,16 +34,11 @@
 #include "llvm/Analysis/AliasAnalysis.h"
 #include "llvm/ADT/DenseMap.h"
 #include "llvm/ADT/Statistic.h"
-#include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/raw_ostream.h"
 
 using namespace llvm;
 
-static cl::opt<bool> HoistLdConst("licm-const-load",
-                                  cl::desc("LICM load from constant memory"),
-                                  cl::init(false), cl::Hidden);
-
 STATISTIC(NumHoisted, "Number of machine instructions hoisted out of loops");
 STATISTIC(NumCSEed,   "Number of hoisted machine instructions CSEed");
 
@@ -102,7 +97,7 @@
 
     /// IsProfitableToHoist - Return true if it is potentially profitable to
     /// hoist the given loop invariant.
-    bool IsProfitableToHoist(MachineInstr &MI, bool &isConstLd);
+    bool IsProfitableToHoist(MachineInstr &MI);
 
     /// HoistRegion - Walk the specified region of the CFG (defined by all
     /// blocks dominated by the specified block, and that are in the current
@@ -367,9 +362,7 @@
 
 /// IsProfitableToHoist - Return true if it is potentially profitable to hoist
 /// the given loop invariant.
-bool MachineLICM::IsProfitableToHoist(MachineInstr &MI, bool &isConstLd) {
-  isConstLd = false;
-
+bool MachineLICM::IsProfitableToHoist(MachineInstr &MI) {
   if (MI.getOpcode() == TargetInstrInfo::IMPLICIT_DEF)
     return false;
 
@@ -382,9 +375,8 @@
   // adding a store in the loop preheader. But the reload is no more expensive.
   // The side benefit is these loads are frequently CSE'ed.
   if (!TII->isTriviallyReMaterializable(&MI, AA)) {
-    if (!HoistLdConst || !isLoadFromConstantMemory(&MI))
+    if (!isLoadFromConstantMemory(&MI))
       return false;
-    isConstLd = true;
   }
 
   // If result(s) of this instruction is used by PHIs, then don't hoist it.
@@ -439,9 +431,7 @@
   MBB->insert(MI, NewMIs[1]);
   // If unfolding produced a load that wasn't loop-invariant or profitable to
   // hoist, discard the new instructions and bail.
-  bool isConstLd;
-  if (!IsLoopInvariantInst(*NewMIs[0]) ||
-      !IsProfitableToHoist(*NewMIs[0], isConstLd)) {
+  if (!IsLoopInvariantInst(*NewMIs[0]) || !IsProfitableToHoist(*NewMIs[0])) {
     NewMIs[0]->eraseFromParent();
     NewMIs[1]->eraseFromParent();
     return 0;
@@ -507,9 +497,7 @@
 ///
 void MachineLICM::Hoist(MachineInstr *MI) {
   // First check whether we should hoist this instruction.
-  bool isConstLd;
-  if (!IsLoopInvariantInst(*MI) ||
-      !IsProfitableToHoist(*MI, isConstLd)) {
+  if (!IsLoopInvariantInst(*MI) || !IsProfitableToHoist(*MI)) {
     // If not, try unfolding a hoistable load.
     MI = ExtractHoistableLoad(MI);
     if (!MI) return;
@@ -518,10 +506,7 @@
   // Now move the instructions to the predecessor, inserting it before any
   // terminator instructions.
   DEBUG({
-      errs() << "Hoisting ";
-      if (isConstLd)
-        errs() << "load from constant mem ";
-      errs() << *MI;
+      errs() << "Hoisting " << *MI;
       if (CurPreheader->getBasicBlock())
         errs() << " to MachineBasicBlock "
                << CurPreheader->getName();

Modified: llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=89727&r1=89726&r2=89727&view=diff

==============================================================================
--- llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMBaseInstrInfo.cpp Mon Nov 23 19:38:56 2009
@@ -978,7 +978,10 @@
                                   const MachineInstr *MI1,
                                   const MachineRegisterInfo *MRI) const {
   int Opcode = MI0->getOpcode();
-  if (Opcode == ARM::t2LDRpci_pic || Opcode == ARM::tLDRpci_pic) {
+  if (Opcode == ARM::t2LDRpci ||
+      Opcode == ARM::t2LDRpci_pic ||
+      Opcode == ARM::tLDRpci ||
+      Opcode == ARM::tLDRpci_pic) {
     if (MI1->getOpcode() != Opcode)
       return false;
     if (MI0->getNumOperands() != MI1->getNumOperands())

Modified: llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMInstrInfo.td?rev=89727&r1=89726&r2=89727&view=diff

==============================================================================
--- llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMInstrInfo.td Mon Nov 23 19:38:56 2009
@@ -597,7 +597,6 @@
                    [(set GPR:$dst, (ARMpic_add GPR:$a, imm:$cp))]>;
 
 let AddedComplexity = 10 in {
-let canFoldAsLoad = 1 in
 def PICLDR  : AXI2ldw<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
                   Pseudo, IIC_iLoadr, "\n${addr:label}:\n\tldr$p\t$dst, $addr",
                   [(set GPR:$dst, (load addrmodepc:$addr))]>;
@@ -817,13 +816,14 @@
 //
 
 // Load
-let canFoldAsLoad = 1, isReMaterializable = 1 in 
+let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in 
 def LDR  : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, IIC_iLoadr,
                "ldr", "\t$dst, $addr",
                [(set GPR:$dst, (load addrmode2:$addr))]>;
 
 // Special LDR for loads from non-pc-relative constpools.
-let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1 in
+let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
+    mayHaveSideEffects = 1  in
 def LDRcp : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm, IIC_iLoadr,
                  "ldr", "\t$dst, $addr", []>;
 

Modified: llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMInstrThumb.td?rev=89727&r1=89726&r2=89727&view=diff

==============================================================================
--- llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMInstrThumb.td Mon Nov 23 19:38:56 2009
@@ -296,7 +296,7 @@
 //  Load Store Instructions.
 //
 
-let canFoldAsLoad = 1 in
+let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
 def tLDR : T1pI4<(outs tGPR:$dst), (ins t_addrmode_s4:$addr), IIC_iLoadr, 
                "ldr", "\t$dst, $addr",
                [(set tGPR:$dst, (load t_addrmode_s4:$addr))]>;
@@ -332,13 +332,14 @@
 
 // Load tconstpool
 // FIXME: Use ldr.n to work around a Darwin assembler bug.
-let canFoldAsLoad = 1 in
+let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1  in 
 def tLDRpci : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr), IIC_iLoadi,
                   "ldr", ".n\t$dst, $addr",
                   [(set tGPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>;
 
 // Special LDR for loads from non-pc-relative constpools.
-let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1 in
+let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
+    mayHaveSideEffects = 1  in
 def tLDRcp  : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr), IIC_iLoadi,
                   "ldr", "\t$dst, $addr", []>;
 

Modified: llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMInstrThumb2.td?rev=89727&r1=89726&r2=89727&view=diff

==============================================================================
--- llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMInstrThumb2.td Mon Nov 23 19:38:56 2009
@@ -486,7 +486,7 @@
 //
 
 // Load
-let canFoldAsLoad = 1 in
+let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1  in 
 defm t2LDR   : T2I_ld<"ldr",  UnOpFrag<(load node:$Src)>>;
 
 // Loads with zero extension
@@ -1198,7 +1198,7 @@
 // Pseudo instruction that combines ldr from constpool and add pc. This should
 // be expanded into two instructions late to allow if-conversion and
 // scheduling.
-let isReMaterializable = 1 in
+let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in 
 def t2LDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
                    NoItinerary, "@ ldr.w\t$dst, $addr\n$cp:\n\tadd\t$dst, pc",
                [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),

Modified: llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMInstrVFP.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMInstrVFP.td?rev=89727&r1=89726&r2=89727&view=diff

==============================================================================
--- llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMInstrVFP.td (original)
+++ llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMInstrVFP.td Mon Nov 23 19:38:56 2009
@@ -54,7 +54,7 @@
 //  Load / store Instructions.
 //
 
-let canFoldAsLoad = 1 in {
+let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
 def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$dst), (ins addrmode5:$addr),
                  IIC_fpLoad64, "vldr", ".64\t$dst, $addr",
                  [(set DPR:$dst, (load addrmode5:$addr))]>;

Added: llvm/branches/Apple/Zoidberg/test/CodeGen/ARM/remat-2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Zoidberg/test/CodeGen/ARM/remat-2.ll?rev=89727&view=auto

==============================================================================
--- llvm/branches/Apple/Zoidberg/test/CodeGen/ARM/remat-2.ll (added)
+++ llvm/branches/Apple/Zoidberg/test/CodeGen/ARM/remat-2.ll Mon Nov 23 19:38:56 2009
@@ -0,0 +1,65 @@
+; RUN: llc < %s -march=arm -mattr=+v6,+vfp2 -stats -info-output-file - | grep "Number of re-materialization"
+
+define arm_apcscc i32 @main(i32 %argc, i8** nocapture %argv) nounwind {
+entry:
+  br i1 undef, label %smvp.exit, label %bb.i3
+
+bb.i3:                                            ; preds = %bb.i3, %bb134
+  br i1 undef, label %smvp.exit, label %bb.i3
+
+smvp.exit:                                        ; preds = %bb.i3
+  %0 = fmul double undef, 2.400000e-03            ; <double> [#uses=2]
+  br i1 undef, label %bb138.preheader, label %bb159
+
+bb138.preheader:                                  ; preds = %smvp.exit
+  br label %bb138
+
+bb138:                                            ; preds = %bb138, %bb138.preheader
+  br i1 undef, label %bb138, label %bb145.loopexit
+
+bb142:                                            ; preds = %bb.nph218.bb.nph218.split_crit_edge, %phi0.exit
+  %1 = fmul double undef, -1.200000e-03           ; <double> [#uses=1]
+  %2 = fadd double undef, %1                      ; <double> [#uses=1]
+  %3 = fmul double %2, undef                      ; <double> [#uses=1]
+  %4 = fsub double 0.000000e+00, %3               ; <double> [#uses=1]
+  br i1 %14, label %phi1.exit, label %bb.i35
+
+bb.i35:                                           ; preds = %bb142
+  %5 = call arm_apcscc  double @sin(double %15) nounwind readonly ; <double> [#uses=1]
+  %6 = fmul double %5, 0x4031740AFA84AD8A         ; <double> [#uses=1]
+  %7 = fsub double 1.000000e+00, undef            ; <double> [#uses=1]
+  %8 = fdiv double %7, 6.000000e-01               ; <double> [#uses=1]
+  br label %phi1.exit
+
+phi1.exit:                                        ; preds = %bb.i35, %bb142
+  %.pn = phi double [ %6, %bb.i35 ], [ 0.000000e+00, %bb142 ] ; <double> [#uses=0]
+  %9 = phi double [ %8, %bb.i35 ], [ 0.000000e+00, %bb142 ] ; <double> [#uses=1]
+  %10 = fmul double undef, %9                     ; <double> [#uses=0]
+  br i1 %14, label %phi0.exit, label %bb.i
+
+bb.i:                                             ; preds = %phi1.exit
+  unreachable
+
+phi0.exit:                                        ; preds = %phi1.exit
+  %11 = fsub double %4, undef                     ; <double> [#uses=1]
+  %12 = fadd double 0.000000e+00, %11             ; <double> [#uses=1]
+  store double %12, double* undef, align 4
+  br label %bb142
+
+bb145.loopexit:                                   ; preds = %bb138
+  br i1 undef, label %bb.nph218.bb.nph218.split_crit_edge, label %bb159
+
+bb.nph218.bb.nph218.split_crit_edge:              ; preds = %bb145.loopexit
+  %13 = fmul double %0, 0x401921FB54442D18        ; <double> [#uses=1]
+  %14 = fcmp ugt double %0, 6.000000e-01          ; <i1> [#uses=2]
+  %15 = fdiv double %13, 6.000000e-01             ; <double> [#uses=1]
+  br label %bb142
+
+bb159:                                            ; preds = %bb145.loopexit, %smvp.exit, %bb134
+  unreachable
+
+bb166:                                            ; preds = %bb127
+  unreachable
+}
+
+declare arm_apcscc double @sin(double) nounwind readonly

Modified: llvm/branches/Apple/Zoidberg/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Zoidberg/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll?rev=89727&r1=89726&r2=89727&view=diff

==============================================================================
--- llvm/branches/Apple/Zoidberg/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll (original)
+++ llvm/branches/Apple/Zoidberg/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll Mon Nov 23 19:38:56 2009
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mcpu=cortex-a8 | grep vmov.f32 | count 5
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mcpu=cortex-a8 | grep vmov.f32 | count 7
 
 define arm_apcscc void @fht(float* nocapture %fz, i16 signext %n) nounwind {
 entry:

Modified: llvm/branches/Apple/Zoidberg/test/CodeGen/Thumb2/ldr-str-imm12.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Zoidberg/test/CodeGen/Thumb2/ldr-str-imm12.ll?rev=89727&r1=89726&r2=89727&view=diff

==============================================================================
--- llvm/branches/Apple/Zoidberg/test/CodeGen/Thumb2/ldr-str-imm12.ll (original)
+++ llvm/branches/Apple/Zoidberg/test/CodeGen/Thumb2/ldr-str-imm12.ll Mon Nov 23 19:38:56 2009
@@ -22,8 +22,7 @@
 
 define arm_apcscc %union.rec* @Manifest(%union.rec* %x, %union.rec* %env, %struct.STYLE* %style, %union.rec** %bthr, %union.rec** %fthr, %union.rec** %target, %union.rec** %crs, i32 %ok, i32 %need_expand, %union.rec** %enclose, i32 %fcr) nounwind {
 entry:
-; CHECK:       ldr.w	r9, [r7, #+32]
-; CHECK-NEXT : str.w	r9, [sp, #+28]
+; CHECK:       ldr.w	r9, [r7, #+28]
   %xgaps.i = alloca [32 x %union.rec*], align 4   ; <[32 x %union.rec*]*> [#uses=0]
   %ycomp.i = alloca [32 x %union.rec*], align 4   ; <[32 x %union.rec*]*> [#uses=0]
   br i1 false, label %bb, label %bb20
@@ -53,7 +52,6 @@
 ; CHECK: str r{{[0-7]}}, [sp]
 ; CHECK: str r{{[0-7]}}, [sp, #+4]
 ; CHECK: str r{{[0-7]}}, [sp, #+8]
-; CHECK: ldr r{{[0-7]}}, [sp, #+28]
 ; CHECK: str r{{[0-7]}}, [sp, #+24]
   store %union.rec* null, %union.rec** @zz_hold, align 4
   store %union.rec* null, %union.rec** @zz_res, align 4

Modified: llvm/branches/Apple/Zoidberg/test/CodeGen/Thumb2/machine-licm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Zoidberg/test/CodeGen/Thumb2/machine-licm.ll?rev=89727&r1=89726&r2=89727&view=diff

==============================================================================
--- llvm/branches/Apple/Zoidberg/test/CodeGen/Thumb2/machine-licm.ll (original)
+++ llvm/branches/Apple/Zoidberg/test/CodeGen/Thumb2/machine-licm.ll Mon Nov 23 19:38:56 2009
@@ -1,4 +1,5 @@
-; RUN: llc < %s -mtriple=thumbv7-apple-darwin -relocation-model=pic -disable-fp-elim | FileCheck %s
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin -disable-fp-elim                       | FileCheck %s
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin -relocation-model=pic -disable-fp-elim | FileCheck %s --check-prefix=PIC
 ; rdar://7353541
 ; rdar://7354376
 
@@ -17,12 +18,24 @@
 bb.nph:                                           ; preds = %entry
 ; CHECK: BB#1
 ; CHECK: ldr.n r2, LCPI1_0
-; CHECK: add r2, pc
-; CHECK: ldr r{{[0-9]+}}, [r2]
+; CHECK: ldr r3, [r2]
+; CHECK: ldr r3, [r3]
+; CHECK: ldr r2, [r2]
 ; CHECK: LBB1_2
 ; CHECK: LCPI1_0:
 ; CHECK-NOT: LCPI1_1:
 ; CHECK: .section
+
+; PIC: BB#1
+; PIC: ldr.n r2, LCPI1_0
+; PIC: add r2, pc
+; PIC: ldr r3, [r2]
+; PIC: ldr r3, [r3]
+; PIC: ldr r2, [r2]
+; PIC: LBB1_2
+; PIC: LCPI1_0:
+; PIC-NOT: LCPI1_1:
+; PIC: .section
   %.pre = load i32* @GV, align 4                  ; <i32> [#uses=1]
   br label %bb
 

Modified: llvm/branches/Apple/Zoidberg/test/CodeGen/X86/2009-10-08-MachineLICMBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Zoidberg/test/CodeGen/X86/2009-10-08-MachineLICMBug.ll?rev=89727&r1=89726&r2=89727&view=diff

==============================================================================
--- llvm/branches/Apple/Zoidberg/test/CodeGen/X86/2009-10-08-MachineLICMBug.ll (original)
+++ llvm/branches/Apple/Zoidberg/test/CodeGen/X86/2009-10-08-MachineLICMBug.ll Mon Nov 23 19:38:56 2009
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=i386-apple-darwin -relocation-model=pic -stats |& grep {machine-licm} | grep 1
+; RUN: llc < %s -mtriple=i386-apple-darwin -relocation-model=pic -stats |& grep {machine-licm} | grep 2
 ; rdar://7274692
 
 %0 = type { [125 x i32] }

Modified: llvm/branches/Apple/Zoidberg/test/CodeGen/X86/pic-load-remat.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Zoidberg/test/CodeGen/X86/pic-load-remat.ll?rev=89727&r1=89726&r2=89727&view=diff

==============================================================================
--- llvm/branches/Apple/Zoidberg/test/CodeGen/X86/pic-load-remat.ll (original)
+++ llvm/branches/Apple/Zoidberg/test/CodeGen/X86/pic-load-remat.ll Mon Nov 23 19:38:56 2009
@@ -1,10 +1,4 @@
 ; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+sse2 -relocation-model=pic | grep psllw | grep pb
-; XFAIL: *
-
-; This is XFAIL'd because MachineLICM is now hoisting all of the loads, and the pic
-; base appears killed in the entry block when remat is making its decisions. Remat's
-; simple heuristic decides against rematting because it doesn't want to extend the
-; live-range of the pic base; this isn't necessarily optimal.
 
 define void @f() nounwind  {
 entry:





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