[llvm-branch-commits] [llvm-branch] r88746 - in /llvm/branches/Apple/Leela: include/llvm/Target/ lib/CodeGen/ lib/Target/ARM/ lib/Target/X86/ test/CodeGen/ARM/
Evan Cheng
evan.cheng at apple.com
Fri Nov 13 19:04:11 PST 2009
Author: evancheng
Date: Fri Nov 13 21:04:10 2009
New Revision: 88746
URL: http://llvm.org/viewvc/llvm-project?rev=88746&view=rev
Log:
Merge 88745.
Added:
llvm/branches/Apple/Leela/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll
Modified:
llvm/branches/Apple/Leela/include/llvm/Target/TargetInstrInfo.h
llvm/branches/Apple/Leela/lib/CodeGen/PreAllocSplitting.cpp
llvm/branches/Apple/Leela/lib/CodeGen/SimpleRegisterCoalescing.cpp
llvm/branches/Apple/Leela/lib/CodeGen/TargetInstrInfoImpl.cpp
llvm/branches/Apple/Leela/lib/CodeGen/TwoAddressInstructionPass.cpp
llvm/branches/Apple/Leela/lib/CodeGen/VirtRegRewriter.cpp
llvm/branches/Apple/Leela/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm/branches/Apple/Leela/lib/Target/ARM/ARMBaseInstrInfo.h
llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrInfo.cpp
llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrInfo.h
llvm/branches/Apple/Leela/lib/Target/X86/X86InstrInfo.cpp
llvm/branches/Apple/Leela/lib/Target/X86/X86InstrInfo.h
Modified: llvm/branches/Apple/Leela/include/llvm/Target/TargetInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/include/llvm/Target/TargetInstrInfo.h?rev=88746&r1=88745&r2=88746&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/include/llvm/Target/TargetInstrInfo.h (original)
+++ llvm/branches/Apple/Leela/include/llvm/Target/TargetInstrInfo.h Fri Nov 13 21:04:10 2009
@@ -21,6 +21,7 @@
class MCAsmInfo;
class TargetRegisterClass;
+class TargetRegisterInfo;
class LiveVariables;
class CalleeSavedInfo;
class SDNode;
@@ -186,7 +187,8 @@
virtual void reMaterialize(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SubIdx,
- const MachineInstr *Orig) const = 0;
+ const MachineInstr *Orig,
+ const TargetRegisterInfo *TRI) const = 0;
/// convertToThreeAddress - This method must be implemented by targets that
/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
@@ -516,7 +518,8 @@
virtual void reMaterialize(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SubReg,
- const MachineInstr *Orig) const;
+ const MachineInstr *Orig,
+ const TargetRegisterInfo *TRI) const;
virtual bool isIdentical(const MachineInstr *MI,
const MachineInstr *Other,
const MachineRegisterInfo *MRI) const;
Modified: llvm/branches/Apple/Leela/lib/CodeGen/PreAllocSplitting.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/CodeGen/PreAllocSplitting.cpp?rev=88746&r1=88745&r2=88746&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/CodeGen/PreAllocSplitting.cpp (original)
+++ llvm/branches/Apple/Leela/lib/CodeGen/PreAllocSplitting.cpp Fri Nov 13 21:04:10 2009
@@ -907,7 +907,7 @@
if (KillPt == DefMI->getParent()->end())
return false;
- TII->reMaterialize(MBB, RestorePt, VReg, 0, DefMI);
+ TII->reMaterialize(MBB, RestorePt, VReg, 0, DefMI, TRI);
LIs->InsertMachineInstrInMaps(prior(RestorePt), RestoreIdx);
ReconstructLiveInterval(CurrLI);
Modified: llvm/branches/Apple/Leela/lib/CodeGen/SimpleRegisterCoalescing.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=88746&r1=88745&r2=88746&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/CodeGen/SimpleRegisterCoalescing.cpp (original)
+++ llvm/branches/Apple/Leela/lib/CodeGen/SimpleRegisterCoalescing.cpp Fri Nov 13 21:04:10 2009
@@ -707,7 +707,7 @@
}
MachineBasicBlock::iterator MII = next(MachineBasicBlock::iterator(CopyMI));
- tii_->reMaterialize(*MBB, MII, DstReg, DstSubIdx, DefMI);
+ tii_->reMaterialize(*MBB, MII, DstReg, DstSubIdx, DefMI, tri_);
MachineInstr *NewMI = prior(MII);
if (checkForDeadDef) {
Modified: llvm/branches/Apple/Leela/lib/CodeGen/TargetInstrInfoImpl.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/CodeGen/TargetInstrInfoImpl.cpp?rev=88746&r1=88745&r2=88746&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/CodeGen/TargetInstrInfoImpl.cpp (original)
+++ llvm/branches/Apple/Leela/lib/CodeGen/TargetInstrInfoImpl.cpp Fri Nov 13 21:04:10 2009
@@ -135,11 +135,16 @@
MachineBasicBlock::iterator I,
unsigned DestReg,
unsigned SubIdx,
- const MachineInstr *Orig) const {
+ const MachineInstr *Orig,
+ const TargetRegisterInfo *TRI) const {
MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
MachineOperand &MO = MI->getOperand(0);
- MO.setReg(DestReg);
- MO.setSubReg(SubIdx);
+ if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
+ MO.setReg(DestReg);
+ MO.setSubReg(SubIdx);
+ } else {
+ MO.setReg(TRI->getSubReg(DestReg, SubIdx));
+ }
MBB.insert(I, MI);
}
Modified: llvm/branches/Apple/Leela/lib/CodeGen/TwoAddressInstructionPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/CodeGen/TwoAddressInstructionPass.cpp?rev=88746&r1=88745&r2=88746&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/CodeGen/TwoAddressInstructionPass.cpp (original)
+++ llvm/branches/Apple/Leela/lib/CodeGen/TwoAddressInstructionPass.cpp Fri Nov 13 21:04:10 2009
@@ -1033,7 +1033,7 @@
isProfitableToReMat(regB, rc, mi, DefMI, mbbi, Dist)){
DEBUG(errs() << "2addr: REMATTING : " << *DefMI << "\n");
unsigned regASubIdx = mi->getOperand(DstIdx).getSubReg();
- TII->reMaterialize(*mbbi, mi, regA, regASubIdx, DefMI);
+ TII->reMaterialize(*mbbi, mi, regA, regASubIdx, DefMI, TRI);
ReMatRegs.set(regB);
++NumReMats;
} else {
Modified: llvm/branches/Apple/Leela/lib/CodeGen/VirtRegRewriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/CodeGen/VirtRegRewriter.cpp?rev=88746&r1=88745&r2=88746&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/CodeGen/VirtRegRewriter.cpp (original)
+++ llvm/branches/Apple/Leela/lib/CodeGen/VirtRegRewriter.cpp Fri Nov 13 21:04:10 2009
@@ -594,7 +594,7 @@
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI.getOperand(i);
- if (!MO.isReg() || !MO.isDef())
+ if (!MO.isReg() || !MO.getReg() || !MO.isDef())
continue;
unsigned Reg = MO.getReg();
RegKills.reset(Reg);
@@ -626,7 +626,7 @@
"Don't know how to remat instructions that define > 1 values!");
#endif
TII->reMaterialize(MBB, MII, DestReg,
- ReMatDefMI->getOperand(0).getSubReg(), ReMatDefMI);
+ ReMatDefMI->getOperand(0).getSubReg(), ReMatDefMI, TRI);
MachineInstr *NewMI = prior(MII);
for (unsigned i = 0, e = NewMI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = NewMI->getOperand(i);
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=88746&r1=88745&r2=88746&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/ARMBaseInstrInfo.cpp Fri Nov 13 21:04:10 2009
@@ -921,8 +921,15 @@
reMaterialize(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
unsigned DestReg, unsigned SubIdx,
- const MachineInstr *Orig) const {
+ const MachineInstr *Orig,
+ const TargetRegisterInfo *TRI) const {
DebugLoc dl = Orig->getDebugLoc();
+
+ if (SubIdx && TargetRegisterInfo::isPhysicalRegister(DestReg)) {
+ DestReg = TRI->getSubReg(DestReg, SubIdx);
+ SubIdx = 0;
+ }
+
unsigned Opcode = Orig->getOpcode();
switch (Opcode) {
default: {
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/ARMBaseInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/ARMBaseInstrInfo.h?rev=88746&r1=88745&r2=88746&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/ARMBaseInstrInfo.h (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/ARMBaseInstrInfo.h Fri Nov 13 21:04:10 2009
@@ -267,7 +267,8 @@
virtual void reMaterialize(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SubIdx,
- const MachineInstr *Orig) const;
+ const MachineInstr *Orig,
+ const TargetRegisterInfo *TRI) const;
virtual bool isIdentical(const MachineInstr *MI, const MachineInstr *Other,
const MachineRegisterInfo *MRI) const;
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrInfo.cpp?rev=88746&r1=88745&r2=88746&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrInfo.cpp (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrInfo.cpp Fri Nov 13 21:04:10 2009
@@ -81,8 +81,8 @@
void ARMInstrInfo::
reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
- unsigned DestReg, unsigned SubIdx,
- const MachineInstr *Orig) const {
+ unsigned DestReg, unsigned SubIdx, const MachineInstr *Orig,
+ const TargetRegisterInfo *TRI) const {
DebugLoc dl = Orig->getDebugLoc();
unsigned Opcode = Orig->getOpcode();
switch (Opcode) {
@@ -100,6 +100,6 @@
}
}
- return ARMBaseInstrInfo::reMaterialize(MBB, I, DestReg, SubIdx, Orig);
+ return ARMBaseInstrInfo::reMaterialize(MBB, I, DestReg, SubIdx, Orig, TRI);
}
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrInfo.h?rev=88746&r1=88745&r2=88746&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrInfo.h (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrInfo.h Fri Nov 13 21:04:10 2009
@@ -37,7 +37,8 @@
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SubIdx,
- const MachineInstr *Orig) const;
+ const MachineInstr *Orig,
+ const TargetRegisterInfo *TRI) const;
/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
/// such, whenever a client has an instance of instruction info, it should
Modified: llvm/branches/Apple/Leela/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/X86/X86InstrInfo.cpp?rev=88746&r1=88745&r2=88746&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/branches/Apple/Leela/lib/Target/X86/X86InstrInfo.cpp Fri Nov 13 21:04:10 2009
@@ -917,12 +917,13 @@
void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
unsigned DestReg, unsigned SubIdx,
- const MachineInstr *Orig) const {
+ const MachineInstr *Orig,
+ const TargetRegisterInfo *TRI) const {
DebugLoc DL = DebugLoc::getUnknownLoc();
if (I != MBB.end()) DL = I->getDebugLoc();
if (SubIdx && TargetRegisterInfo::isPhysicalRegister(DestReg)) {
- DestReg = RI.getSubReg(DestReg, SubIdx);
+ DestReg = TRI->getSubReg(DestReg, SubIdx);
SubIdx = 0;
}
Modified: llvm/branches/Apple/Leela/lib/Target/X86/X86InstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/X86/X86InstrInfo.h?rev=88746&r1=88745&r2=88746&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/X86/X86InstrInfo.h (original)
+++ llvm/branches/Apple/Leela/lib/Target/X86/X86InstrInfo.h Fri Nov 13 21:04:10 2009
@@ -455,7 +455,8 @@
AliasAnalysis *AA) const;
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SubIdx,
- const MachineInstr *Orig) const;
+ const MachineInstr *Orig,
+ const TargetRegisterInfo *TRI) const;
/// convertToThreeAddress - This method must be implemented by targets that
/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
Added: llvm/branches/Apple/Leela/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll?rev=88746&view=auto
==============================================================================
--- llvm/branches/Apple/Leela/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll (added)
+++ llvm/branches/Apple/Leela/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll Fri Nov 13 21:04:10 2009
@@ -0,0 +1,66 @@
+; RUN: llc -mcpu=cortex-a8 < %s | FileCheck %s
+; PR5423
+
+target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
+target triple = "armv7-eabi"
+
+define arm_aapcs_vfpcc void @foo() {
+entry:
+ %0 = load float* null, align 4 ; <float> [#uses=2]
+ %1 = fmul float %0, undef ; <float> [#uses=2]
+ %2 = fmul float 0.000000e+00, %1 ; <float> [#uses=2]
+ %3 = fmul float %0, %1 ; <float> [#uses=1]
+ %4 = fadd float 0.000000e+00, %3 ; <float> [#uses=1]
+ %5 = fsub float 1.000000e+00, %4 ; <float> [#uses=1]
+; CHECK: foo:
+; CHECK: fconsts s{{[0-9]+}}, #112
+ %6 = fsub float 1.000000e+00, undef ; <float> [#uses=2]
+ %7 = fsub float %2, undef ; <float> [#uses=1]
+ %8 = fsub float 0.000000e+00, undef ; <float> [#uses=3]
+ %9 = fadd float %2, undef ; <float> [#uses=3]
+ %10 = load float* undef, align 8 ; <float> [#uses=3]
+ %11 = fmul float %8, %10 ; <float> [#uses=1]
+ %12 = fadd float undef, %11 ; <float> [#uses=2]
+ %13 = fmul float undef, undef ; <float> [#uses=1]
+ %14 = fmul float %6, 0.000000e+00 ; <float> [#uses=1]
+ %15 = fadd float %13, %14 ; <float> [#uses=1]
+ %16 = fmul float %9, %10 ; <float> [#uses=1]
+ %17 = fadd float %15, %16 ; <float> [#uses=2]
+ %18 = fmul float 0.000000e+00, undef ; <float> [#uses=1]
+ %19 = fadd float %18, 0.000000e+00 ; <float> [#uses=1]
+ %20 = fmul float undef, %10 ; <float> [#uses=1]
+ %21 = fadd float %19, %20 ; <float> [#uses=1]
+ %22 = load float* undef, align 8 ; <float> [#uses=1]
+ %23 = fmul float %5, %22 ; <float> [#uses=1]
+ %24 = fadd float %23, undef ; <float> [#uses=1]
+ %25 = load float* undef, align 8 ; <float> [#uses=2]
+ %26 = fmul float %8, %25 ; <float> [#uses=1]
+ %27 = fadd float %24, %26 ; <float> [#uses=1]
+ %28 = fmul float %9, %25 ; <float> [#uses=1]
+ %29 = fadd float undef, %28 ; <float> [#uses=1]
+ %30 = fmul float %8, undef ; <float> [#uses=1]
+ %31 = fadd float undef, %30 ; <float> [#uses=1]
+ %32 = fmul float %6, undef ; <float> [#uses=1]
+ %33 = fadd float undef, %32 ; <float> [#uses=1]
+ %34 = fmul float %9, undef ; <float> [#uses=1]
+ %35 = fadd float %33, %34 ; <float> [#uses=1]
+ %36 = fmul float 0.000000e+00, undef ; <float> [#uses=1]
+ %37 = fmul float %7, undef ; <float> [#uses=1]
+ %38 = fadd float %36, %37 ; <float> [#uses=1]
+ %39 = fmul float undef, undef ; <float> [#uses=1]
+ %40 = fadd float %38, %39 ; <float> [#uses=1]
+ store float %12, float* undef, align 8
+ store float %17, float* undef, align 4
+ store float %21, float* undef, align 8
+ store float %27, float* undef, align 8
+ store float %29, float* undef, align 4
+ store float %31, float* undef, align 8
+ store float %40, float* undef, align 8
+ store float %12, float* null, align 8
+ %41 = fmul float %17, undef ; <float> [#uses=1]
+ %42 = fadd float %41, undef ; <float> [#uses=1]
+ %43 = fmul float %35, undef ; <float> [#uses=1]
+ %44 = fadd float %42, %43 ; <float> [#uses=1]
+ store float %44, float* null, align 4
+ unreachable
+}
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