[llvm-branch-commits] [llvm-branch] r88709 - in /llvm/branches/Apple/Leela: include/llvm/Target/Target.td lib/CodeGen/BranchFolding.cpp lib/CodeGen/BranchFolding.h test/CodeGen/X86/tail-opts.ll
Dan Gohman
gohman at apple.com
Fri Nov 13 14:10:18 PST 2009
Author: djg
Date: Fri Nov 13 16:10:18 2009
New Revision: 88709
URL: http://llvm.org/viewvc/llvm-project?rev=88709&view=rev
Log:
$ svn merge -c 86926 https://djg@llvm.org/svn/llvm-project/llvm/trunk
--- Merging r86926 into '.':
U lib/CodeGen/BranchFolding.cpp
$ svn merge -c 86928 https://djg@llvm.org/svn/llvm-project/llvm/trunk
--- Merging r86928 into '.':
G lib/CodeGen/BranchFolding.cpp
U lib/CodeGen/BranchFolding.h
$ svn merge -c 87009 https://djg@llvm.org/svn/llvm-project/llvm/trunk
--- Merging r87009 into '.':
U include/llvm/Target/Target.td
$ svn merge -c 88692 https://djg@llvm.org/svn/llvm-project/llvm/trunk
--- Merging r88692 into '.':
U test/CodeGen/X86/tail-opts.ll
G lib/CodeGen/BranchFolding.cpp
Modified:
llvm/branches/Apple/Leela/include/llvm/Target/Target.td
llvm/branches/Apple/Leela/lib/CodeGen/BranchFolding.cpp
llvm/branches/Apple/Leela/lib/CodeGen/BranchFolding.h
llvm/branches/Apple/Leela/test/CodeGen/X86/tail-opts.ll
Modified: llvm/branches/Apple/Leela/include/llvm/Target/Target.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/include/llvm/Target/Target.td?rev=88709&r1=88708&r2=88709&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/include/llvm/Target/Target.td (original)
+++ llvm/branches/Apple/Leela/include/llvm/Target/Target.td Fri Nov 13 16:10:18 2009
@@ -413,6 +413,7 @@
let AsmString = "";
let Namespace = "TargetInstrInfo";
let hasCtrlDep = 1;
+ let isNotDuplicable = 1;
}
def EH_LABEL : Instruction {
let OutOperandList = (ops);
@@ -420,6 +421,7 @@
let AsmString = "";
let Namespace = "TargetInstrInfo";
let hasCtrlDep = 1;
+ let isNotDuplicable = 1;
}
def GC_LABEL : Instruction {
let OutOperandList = (ops);
@@ -427,6 +429,7 @@
let AsmString = "";
let Namespace = "TargetInstrInfo";
let hasCtrlDep = 1;
+ let isNotDuplicable = 1;
}
def KILL : Instruction {
let OutOperandList = (ops);
Modified: llvm/branches/Apple/Leela/lib/CodeGen/BranchFolding.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/CodeGen/BranchFolding.cpp?rev=88709&r1=88708&r2=88709&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/CodeGen/BranchFolding.cpp (original)
+++ llvm/branches/Apple/Leela/lib/CodeGen/BranchFolding.cpp Fri Nov 13 16:10:18 2009
@@ -56,6 +56,20 @@
cl::desc("Min number of instructions to consider tail merging"),
cl::init(3), cl::Hidden);
+namespace {
+ /// BranchFolderPass - Wrap branch folder in a machine function pass.
+ class BranchFolderPass : public MachineFunctionPass,
+ public BranchFolder {
+ public:
+ static char ID;
+ explicit BranchFolderPass(bool defaultEnableTailMerge)
+ : MachineFunctionPass(&ID), BranchFolder(defaultEnableTailMerge) {}
+
+ virtual bool runOnMachineFunction(MachineFunction &MF);
+ virtual const char *getPassName() const { return "Control Flow Optimizer"; }
+ };
+}
+
char BranchFolderPass::ID = 0;
FunctionPass *llvm::createBranchFoldingPass(bool DefaultEnableTailMerge) {
@@ -380,7 +394,7 @@
RS->forward(prior(CurMBB.end()));
BitVector RegsLiveAtExit(TRI->getNumRegs());
RS->getRegsUsed(RegsLiveAtExit, false);
- for (unsigned int i=0, e=TRI->getNumRegs(); i!=e; i++)
+ for (unsigned int i = 0, e = TRI->getNumRegs(); i != e; i++)
if (RegsLiveAtExit[i])
NewMBB->addLiveIn(i);
}
@@ -505,21 +519,24 @@
return true;
// If both blocks have an unconditional branch temporarily stripped out,
- // treat that as an additional common instruction.
- if (MBB1 != PredBB && MBB2 != PredBB &&
+ // count that as an additional common instruction for the following
+ // heuristics.
+ unsigned EffectiveTailLen = CommonTailLen;
+ if (SuccBB && MBB1 != PredBB && MBB2 != PredBB &&
!MBB1->back().getDesc().isBarrier() &&
!MBB2->back().getDesc().isBarrier())
- --minCommonTailLength;
+ ++EffectiveTailLen;
// Check if the common tail is long enough to be worthwhile.
- if (CommonTailLen >= minCommonTailLength)
+ if (EffectiveTailLen >= minCommonTailLength)
return true;
- // If we are optimizing for code size, 1 instruction in common is enough if
- // we don't have to split a block. At worst we will be replacing a
- // fallthrough into the common tail with a branch, which at worst breaks
- // even with falling through into the duplicated common tail.
- if (MF->getFunction()->hasFnAttr(Attribute::OptimizeForSize) &&
+ // If we are optimizing for code size, 2 instructions in common is enough if
+ // we don't have to split a block. At worst we will be introducing 1 new
+ // branch instruction, which is likely to be smaller than the 2
+ // instructions that would be deleted in the merge.
+ if (EffectiveTailLen >= 2 &&
+ MF->getFunction()->hasFnAttr(Attribute::OptimizeForSize) &&
(I1 == MBB1->begin() || I2 == MBB2->begin()))
return true;
@@ -546,7 +563,7 @@
MPIterator HighestMPIter = prior(MergePotentials.end());
for (MPIterator CurMPIter = prior(MergePotentials.end()),
B = MergePotentials.begin();
- CurMPIter!=B && CurMPIter->getHash() == CurHash;
+ CurMPIter != B && CurMPIter->getHash() == CurHash;
--CurMPIter) {
for (MPIterator I = prior(CurMPIter); I->getHash() == CurHash ; --I) {
unsigned CommonTailLen;
@@ -596,9 +613,9 @@
/// only of the common tail. Create a block that does by splitting one.
unsigned BranchFolder::CreateCommonTailOnlyBlock(MachineBasicBlock *&PredBB,
unsigned maxCommonTailLength) {
- unsigned i, commonTailIndex;
+ unsigned commonTailIndex = 0;
unsigned TimeEstimate = ~0U;
- for (i=0, commonTailIndex=0; i<SameTails.size(); i++) {
+ for (unsigned i = 0, e = SameTails.size(); i != e; ++i) {
// Use PredBB if possible; that doesn't require a new branch.
if (SameTails[i].getBlock() == PredBB) {
commonTailIndex = i;
@@ -856,19 +873,19 @@
if (IBB->isLandingPad()) {
MachineFunction::iterator IP = PBB; IP++;
MachineBasicBlock* PredNextBB = NULL;
- if (IP!=MF.end())
+ if (IP != MF.end())
PredNextBB = IP;
if (TBB == NULL) {
- if (IBB!=PredNextBB) // fallthrough
+ if (IBB != PredNextBB) // fallthrough
continue;
} else if (FBB) {
- if (TBB!=IBB && FBB!=IBB) // cbr then ubr
+ if (TBB != IBB && FBB != IBB) // cbr then ubr
continue;
} else if (Cond.empty()) {
- if (TBB!=IBB) // ubr
+ if (TBB != IBB) // ubr
continue;
} else {
- if (TBB!=IBB && IBB!=PredNextBB) // cbr
+ if (TBB != IBB && IBB != PredNextBB) // cbr
continue;
}
}
Modified: llvm/branches/Apple/Leela/lib/CodeGen/BranchFolding.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/CodeGen/BranchFolding.h?rev=88709&r1=88708&r2=88709&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/CodeGen/BranchFolding.h (original)
+++ llvm/branches/Apple/Leela/lib/CodeGen/BranchFolding.h Fri Nov 13 16:10:18 2009
@@ -11,7 +11,6 @@
#define LLVM_CODEGEN_BRANCHFOLDING_HPP
#include "llvm/CodeGen/MachineBasicBlock.h"
-#include "llvm/CodeGen/MachineFunctionPass.h"
#include <vector>
namespace llvm {
@@ -20,6 +19,7 @@
class RegScavenger;
class TargetInstrInfo;
class TargetRegisterInfo;
+ template<typename T> class SmallVectorImpl;
class BranchFolder {
public:
@@ -119,19 +119,6 @@
MachineBasicBlock *TBB, MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond);
};
-
-
- /// BranchFolderPass - Wrap branch folder in a machine function pass.
- class BranchFolderPass : public MachineFunctionPass,
- public BranchFolder {
- public:
- static char ID;
- explicit BranchFolderPass(bool defaultEnableTailMerge)
- : MachineFunctionPass(&ID), BranchFolder(defaultEnableTailMerge) {}
-
- virtual bool runOnMachineFunction(MachineFunction &MF);
- virtual const char *getPassName() const { return "Control Flow Optimizer"; }
- };
}
#endif /* LLVM_CODEGEN_BRANCHFOLDING_HPP */
Modified: llvm/branches/Apple/Leela/test/CodeGen/X86/tail-opts.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/test/CodeGen/X86/tail-opts.ll?rev=88709&r1=88708&r2=88709&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/test/CodeGen/X86/tail-opts.ll (original)
+++ llvm/branches/Apple/Leela/test/CodeGen/X86/tail-opts.ll Fri Nov 13 16:10:18 2009
@@ -293,3 +293,116 @@
}
declare void @func()
+
+; one - One instruction may be tail-duplicated even with optsize.
+
+; CHECK: one:
+; CHECK: movl $0, XYZ(%rip)
+; CHECK: movl $0, XYZ(%rip)
+
+ at XYZ = external global i32
+
+define void @one() nounwind optsize {
+entry:
+ %0 = icmp eq i32 undef, 0
+ br i1 %0, label %bbx, label %bby
+
+bby:
+ switch i32 undef, label %bb7 [
+ i32 16, label %return
+ ]
+
+bb7:
+ volatile store i32 0, i32* @XYZ
+ unreachable
+
+bbx:
+ switch i32 undef, label %bb12 [
+ i32 128, label %return
+ ]
+
+bb12:
+ volatile store i32 0, i32* @XYZ
+ unreachable
+
+return:
+ ret void
+}
+
+; two - Same as one, but with two instructions in the common
+; tail instead of one. This is too much to be merged, given
+; the optsize attribute.
+
+; CHECK: two:
+; CHECK-NOT: XYZ
+; CHECK: movl $0, XYZ(%rip)
+; CHECK: movl $1, XYZ(%rip)
+; CHECK-NOT: XYZ
+; CHECK: ret
+
+define void @two() nounwind optsize {
+entry:
+ %0 = icmp eq i32 undef, 0
+ br i1 %0, label %bbx, label %bby
+
+bby:
+ switch i32 undef, label %bb7 [
+ i32 16, label %return
+ ]
+
+bb7:
+ volatile store i32 0, i32* @XYZ
+ volatile store i32 1, i32* @XYZ
+ unreachable
+
+bbx:
+ switch i32 undef, label %bb12 [
+ i32 128, label %return
+ ]
+
+bb12:
+ volatile store i32 0, i32* @XYZ
+ volatile store i32 1, i32* @XYZ
+ unreachable
+
+return:
+ ret void
+}
+
+; two_nosize - Same as two, but without the optsize attribute.
+; Now two instructions are enough to be tail-duplicated.
+
+; CHECK: two_nosize:
+; CHECK: movl $0, XYZ(%rip)
+; CHECK: movl $1, XYZ(%rip)
+; CHECK: movl $0, XYZ(%rip)
+; CHECK: movl $1, XYZ(%rip)
+
+define void @two_nosize() nounwind {
+entry:
+ %0 = icmp eq i32 undef, 0
+ br i1 %0, label %bbx, label %bby
+
+bby:
+ switch i32 undef, label %bb7 [
+ i32 16, label %return
+ ]
+
+bb7:
+ volatile store i32 0, i32* @XYZ
+ volatile store i32 1, i32* @XYZ
+ unreachable
+
+bbx:
+ switch i32 undef, label %bb12 [
+ i32 128, label %return
+ ]
+
+bb12:
+ volatile store i32 0, i32* @XYZ
+ volatile store i32 1, i32* @XYZ
+ unreachable
+
+return:
+ ret void
+}
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