[llvm-branch-commits] [llvm-branch] r86362 - in /llvm/branches/Apple/Leela-M1: lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/sse3.ll test/CodeGen/X86/vec_shuffle-3.ll

[Eric Christopher]

Author: echristo
Date: Sat Nov  7 02:51:11 2009
New Revision: 86362

URL: http://llvm.org/viewvc/llvm-project?rev=86362&view=rev
Log:
Merge from mainline...

rdar://7312668


Modified:
    llvm/branches/Apple/Leela-M1/lib/Target/X86/X86InstrSSE.td
    llvm/branches/Apple/Leela-M1/test/CodeGen/X86/sse3.ll
    llvm/branches/Apple/Leela-M1/test/CodeGen/X86/vec_shuffle-3.ll

Modified: llvm/branches/Apple/Leela-M1/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela-M1/lib/Target/X86/X86InstrSSE.td?rev=86362&r1=86361&r2=86362&view=diff

==============================================================================
--- llvm/branches/Apple/Leela-M1/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/branches/Apple/Leela-M1/lib/Target/X86/X86InstrSSE.td Sat Nov  7 02:51:11 2009
@@ -2085,7 +2085,7 @@
                      [(set VR128:$dst, (v4i32 (pshufd:$src2
                                              (bc_v4i32(memopv2i64 addr:$src1)),
                                              (undef))))]>;
-}                                             
+}
 
 // SSE2 with ImmT == Imm8 and XS prefix.
 def PSHUFHWri : Ii8<0x70, MRMSrcReg,
@@ -2874,7 +2874,7 @@
           (PALIGNR128rr VR128:$src2, VR128:$src1,
                         (SHUFFLE_get_palign_imm VR128:$src3))>,
       Requires<[HasSSSE3]>;
-}      
+}
 
 def : Pat<(X86pshufb VR128:$src, VR128:$mask),
           (PSHUFBrr128 VR128:$src, VR128:$mask)>, Requires<[HasSSSE3]>;
@@ -3051,15 +3051,15 @@
 
 let AddedComplexity = 20 in {
 // vector_shuffle v1, (load v2) <4, 5, 2, 3> using MOVLPS
-// vector_shuffle v1, (load v2) <0, 1, 4, 5> using MOVHPS
+// vector_shuffle v1, (load v2) <6, 7, 2, 3> using MOVHPS
 def : Pat<(v4f32 (movlp VR128:$src1, (load addr:$src2))),
           (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
 def : Pat<(v2f64 (movlp VR128:$src1, (load addr:$src2))),
           (MOVLPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
-def : Pat<(v4f32 (movhp VR128:$src1, (load addr:$src2))),
-          (MOVHPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE1]>;
-def : Pat<(v2f64 (movhp VR128:$src1, (load addr:$src2))),
-          (MOVHPDrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
+def : Pat<(v4f32 (movhlps (load addr:$src1), VR128:$src2)),
+          (MOVHPSrm VR128:$src2, addr:$src1)>, Requires<[HasSSE1]>;
+def : Pat<(v2f64 (movhlps (load addr:$src1), VR128:$src2)),
+          (MOVHPDrm VR128:$src2, addr:$src1)>, Requires<[HasSSE2]>;
 
 def : Pat<(v4i32 (movlp VR128:$src1, (load addr:$src2))),
           (MOVLPSrm VR128:$src1, addr:$src2)>, Requires<[HasSSE2]>;
@@ -3077,9 +3077,9 @@
           (MOVLPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
 def : Pat<(store (v2f64 (movlp (load addr:$src1), VR128:$src2)), addr:$src1),
           (MOVLPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
-def : Pat<(store (v4f32 (movhp (load addr:$src1), VR128:$src2)), addr:$src1),
+def : Pat<(store (v4f32 (movhlps (load addr:$src1), VR128:$src2)), addr:$src1),
           (MOVHPSmr addr:$src1, VR128:$src2)>, Requires<[HasSSE1]>;
-def : Pat<(store (v2f64 (movhp (load addr:$src1), VR128:$src2)), addr:$src1),
+def : Pat<(store (v2f64 (movhlps (load addr:$src1), VR128:$src2)), addr:$src1),
           (MOVHPDmr addr:$src1, VR128:$src2)>, Requires<[HasSSE2]>;
 
 def : Pat<(store (v4i32 (movlp (bc_v4i32 (loadv2i64 addr:$src1)), VR128:$src2)),

Modified: llvm/branches/Apple/Leela-M1/test/CodeGen/X86/sse3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela-M1/test/CodeGen/X86/sse3.ll?rev=86362&r1=86361&r2=86362&view=diff

==============================================================================
--- llvm/branches/Apple/Leela-M1/test/CodeGen/X86/sse3.ll (original)
+++ llvm/branches/Apple/Leela-M1/test/CodeGen/X86/sse3.ll Sat Nov  7 02:51:11 2009
@@ -145,7 +145,9 @@
 	ret void
 ; X64: 	t9:
 ; X64: 		movsd	(%rsi), %xmm0
-; X64: 		movhps	%xmm0, (%rdi)
+; X64:	        movaps  (%rdi), %xmm1
+; X64:	        movlhps %xmm0, %xmm1
+; X64:	        movaps  %xmm1, (%rdi)
 ; X64: 		ret
 }
 

Modified: llvm/branches/Apple/Leela-M1/test/CodeGen/X86/vec_shuffle-3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela-M1/test/CodeGen/X86/vec_shuffle-3.ll?rev=86362&r1=86361&r2=86362&view=diff

==============================================================================
--- llvm/branches/Apple/Leela-M1/test/CodeGen/X86/vec_shuffle-3.ll (original)
+++ llvm/branches/Apple/Leela-M1/test/CodeGen/X86/vec_shuffle-3.ll Sat Nov  7 02:51:11 2009
@@ -1,6 +1,6 @@
 ; RUN: llc < %s -march=x86 -mattr=+sse2 -o %t
 ; RUN: grep movlhps %t | count 1
-; RUN: grep movhlps %t | count 1
+; RUN: grep movhps %t | count 1
 
 define <4 x float> @test1(<4 x float>* %x, <4 x float>* %y) {
         %tmp = load <4 x float>* %y             ; <<4 x float>> [#uses=2]
@@ -18,4 +18,3 @@
         %tmp4 = shufflevector <4 x float> %tmp3, <4 x float> %tmp, <4 x i32> < i32 2, i32 3, i32 6, i32 7 >           ; <<4 x float>> [#uses=1]
         ret <4 x float> %tmp4
 }
-