[llvm-branch-commits] [llvm-branch] r86037 - in /llvm/branches/Apple/Leela: lib/CodeGen/ScheduleDAGInstrs.cpp lib/CodeGen/SimpleRegisterCoalescing.cpp test/CodeGen/X86/2009-11-04-SubregCoalescingBug.ll
Bill Wendling
isanbard at gmail.com
Wed Nov 4 11:05:44 PST 2009
Author: void
Date: Wed Nov 4 13:05:43 2009
New Revision: 86037
URL: http://llvm.org/viewvc/llvm-project?rev=86037&view=rev
Log:
$ svn merge -c -85934 https://llvm.org/svn/llvm-project/llvm/trunk
--- Reverse-merging r85934 into '.':
U lib/CodeGen/ScheduleDAGInstrs.cpp
Added:
llvm/branches/Apple/Leela/test/CodeGen/X86/2009-11-04-SubregCoalescingBug.ll
- copied unchanged from r86022, llvm/trunk/test/CodeGen/X86/2009-11-04-SubregCoalescingBug.ll
Modified:
llvm/branches/Apple/Leela/lib/CodeGen/ScheduleDAGInstrs.cpp
llvm/branches/Apple/Leela/lib/CodeGen/SimpleRegisterCoalescing.cpp
Modified: llvm/branches/Apple/Leela/lib/CodeGen/ScheduleDAGInstrs.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/CodeGen/ScheduleDAGInstrs.cpp?rev=86037&r1=86036&r2=86037&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/CodeGen/ScheduleDAGInstrs.cpp (original)
+++ llvm/branches/Apple/Leela/lib/CodeGen/ScheduleDAGInstrs.cpp Wed Nov 4 13:05:43 2009
@@ -98,9 +98,7 @@
/// information and it can be tracked to a normal reference to a known
/// object, return the Value for that object. Otherwise return null.
static const Value *getUnderlyingObjectForInstr(const MachineInstr *MI,
- const MachineFrameInfo *MFI,
- bool &MayAlias) {
- MayAlias = true;
+ const MachineFrameInfo *MFI) {
if (!MI->hasOneMemOperand() ||
!(*MI->memoperands_begin())->getValue() ||
(*MI->memoperands_begin())->isVolatile())
@@ -112,7 +110,6 @@
V = getUnderlyingObject(V);
if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V)) {
- MayAlias = PSV->mayAlias(MFI);
// For now, ignore PseudoSourceValues which may alias LLVM IR values
// because the code that uses this function has no way to cope with
// such aliases.
@@ -127,23 +124,6 @@
return 0;
}
-static bool mayUnderlyingObjectForInstrAlias(const MachineInstr *MI,
- const MachineFrameInfo *MFI) {
- if (!MI->hasOneMemOperand() ||
- !(*MI->memoperands_begin())->getValue() ||
- (*MI->memoperands_begin())->isVolatile())
- return true;
-
- const Value *V = (*MI->memoperands_begin())->getValue();
- if (!V)
- return true;
-
- V = getUnderlyingObject(V);
- if (const PseudoSourceValue *PSV = dyn_cast<PseudoSourceValue>(V))
- return PSV->mayAlias(MFI);
- return true;
-}
-
void ScheduleDAGInstrs::StartBlock(MachineBasicBlock *BB) {
if (MachineLoop *ML = MLI.getLoopFor(BB))
if (BB == ML->getLoopLatch()) {
@@ -382,9 +362,8 @@
// Unknown memory accesses. Assume the worst.
ChainMMO = 0;
} else if (TID.mayStore()) {
- bool MayAlias = true;
TrueMemOrderLatency = STORE_LOAD_LATENCY;
- if (const Value *V = getUnderlyingObjectForInstr(MI, MFI, MayAlias)) {
+ if (const Value *V = getUnderlyingObjectForInstr(MI, MFI)) {
// A store to a specific PseudoSourceValue. Add precise dependencies.
// Handle the def in MemDefs, if there is one.
std::map<const Value *, SUnit *>::iterator I = MemDefs.find(V);
@@ -404,26 +383,22 @@
/*Reg=*/0, /*isNormalMemory=*/true));
J->second.clear();
}
- if (MayAlias) {
- // Add dependencies from all the PendingLoads, since without
- // memoperands we must assume they alias anything.
- for (unsigned k = 0, m = PendingLoads.size(); k != m; ++k)
- PendingLoads[k]->addPred(SDep(SU, SDep::Order, TrueMemOrderLatency));
- // Add a general dependence too, if needed.
- if (Chain)
- Chain->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
- }
- } else if (MayAlias) {
+ // Add dependencies from all the PendingLoads, since without
+ // memoperands we must assume they alias anything.
+ for (unsigned k = 0, m = PendingLoads.size(); k != m; ++k)
+ PendingLoads[k]->addPred(SDep(SU, SDep::Order, TrueMemOrderLatency));
+ // Add a general dependence too, if needed.
+ if (Chain)
+ Chain->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
+ } else {
// Treat all other stores conservatively.
goto new_chain;
}
} else if (TID.mayLoad()) {
- bool MayAlias = true;
TrueMemOrderLatency = 0;
if (MI->isInvariantLoad(AA)) {
// Invariant load, no chain dependencies needed!
- } else if (const Value *V =
- getUnderlyingObjectForInstr(MI, MFI, MayAlias)) {
+ } else if (const Value *V = getUnderlyingObjectForInstr(MI, MFI)) {
// A load from a specific PseudoSourceValue. Add precise dependencies.
std::map<const Value *, SUnit *>::iterator I = MemDefs.find(V);
if (I != MemDefs.end())
@@ -439,19 +414,16 @@
// Treat volatile loads conservatively. Note that this includes
// cases where memoperand information is unavailable.
goto new_chain;
- } else if (MayAlias) {
- // A "MayAlias" load. Depend on the general chain, as well as on
+ } else {
+ // A normal load. Depend on the general chain, as well as on
// all stores. In the absense of MachineMemOperand information,
// we can't even assume that the load doesn't alias well-behaved
// memory locations.
if (Chain)
Chain->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
for (std::map<const Value *, SUnit *>::iterator I = MemDefs.begin(),
- E = MemDefs.end(); I != E; ++I) {
- SUnit *DefSU = I->second;
- if (mayUnderlyingObjectForInstrAlias(DefSU->getInstr(), MFI))
- DefSU->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
- }
+ E = MemDefs.end(); I != E; ++I)
+ I->second->addPred(SDep(SU, SDep::Order, /*Latency=*/0));
PendingLoads.push_back(SU);
}
}
Modified: llvm/branches/Apple/Leela/lib/CodeGen/SimpleRegisterCoalescing.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=86037&r1=86036&r2=86037&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/CodeGen/SimpleRegisterCoalescing.cpp (original)
+++ llvm/branches/Apple/Leela/lib/CodeGen/SimpleRegisterCoalescing.cpp Wed Nov 4 13:05:43 2009
@@ -1367,7 +1367,7 @@
if (SrcSubIdx)
SrcSubRC = SrcRC->getSubRegisterRegClass(SrcSubIdx);
assert(SrcSubRC && "Illegal subregister index");
- if (!SrcSubRC->contains(DstReg)) {
+ if (!SrcSubRC->contains(DstSubReg)) {
DEBUG(errs() << "\tIncompatible source regclass: "
<< tri_->getName(DstSubReg) << " not in "
<< SrcSubRC->getName() << ".\n");
@@ -1832,6 +1832,25 @@
return std::find(V.begin(), V.end(), Val) != V.end();
}
+static bool isValNoDefMove(const MachineInstr *MI, unsigned DR, unsigned SR,
+ const TargetInstrInfo *TII,
+ const TargetRegisterInfo *TRI) {
+ unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
+ if (TII->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx))
+ ;
+ else if (MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
+ DstReg = MI->getOperand(0).getReg();
+ SrcReg = MI->getOperand(1).getReg();
+ } else if (MI->getOpcode() == TargetInstrInfo::SUBREG_TO_REG ||
+ MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG) {
+ DstReg = MI->getOperand(0).getReg();
+ SrcReg = MI->getOperand(2).getReg();
+ } else
+ return false;
+ return (SrcReg == SR || TRI->isSuperRegister(SR, SrcReg)) &&
+ (DstReg == DR || TRI->isSuperRegister(DR, DstReg));
+}
+
/// RangeIsDefinedByCopyFromReg - Return true if the specified live range of
/// the specified live interval is defined by a copy from the specified
/// register.
@@ -1848,12 +1867,9 @@
// It's a sub-register live interval, we may not have precise information.
// Re-compute it.
MachineInstr *DefMI = li_->getInstructionFromIndex(LR->start);
- unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
- if (DefMI &&
- tii_->isMoveInstr(*DefMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
- DstReg == li.reg && SrcReg == Reg) {
+ if (DefMI && isValNoDefMove(DefMI, li.reg, Reg, tii_, tri_)) {
// Cache computed info.
- LR->valno->def = LR->start;
+ LR->valno->def = LR->start;
LR->valno->setCopy(DefMI);
return true;
}
More information about the llvm-branch-commits
mailing list