[llvm-branch-commits] [llvm-branch] r85841 - in /llvm/branches/Apple/Leela/lib/Target/ARM: ARMAddressingModes.h ARMCallingConv.td ARMISelLowering.cpp ARMInstrInfo.td
Bill Wendling
isanbard at gmail.com
Mon Nov 2 15:47:29 PST 2009
Author: void
Date: Mon Nov 2 17:47:28 2009
New Revision: 85841
URL: http://llvm.org/viewvc/llvm-project?rev=85841&view=rev
Log:
$ svn merge -c 84536 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r84536 into '.':
U lib/Target/ARM/ARMAddressingModes.h
$ svn merge -c 85235 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r85235 into '.':
U lib/Target/ARM/ARMCallingConv.td
$ svn merge -c 85297 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r85297 into '.':
U lib/Target/ARM/ARMInstrInfo.td
$ svn merge -c 85299 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r85299 into '.':
G lib/Target/ARM/ARMInstrInfo.td
$ svn merge -c 85381 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r85381 into '.':
U lib/Target/ARM/ARMISelLowering.cpp
$ svn merge -c 85610 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r85610 into '.':
G lib/Target/ARM/ARMISelLowering.cpp
Modified:
llvm/branches/Apple/Leela/lib/Target/ARM/ARMAddressingModes.h
llvm/branches/Apple/Leela/lib/Target/ARM/ARMCallingConv.td
llvm/branches/Apple/Leela/lib/Target/ARM/ARMISelLowering.cpp
llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrInfo.td
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/ARMAddressingModes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/ARMAddressingModes.h?rev=85841&r1=85840&r2=85841&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/ARMAddressingModes.h (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/ARMAddressingModes.h Mon Nov 2 17:47:28 2009
@@ -15,7 +15,6 @@
#define LLVM_TARGET_ARM_ARMADDRESSINGMODES_H
#include "llvm/CodeGen/SelectionDAGNodes.h"
-#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
#include <cassert>
@@ -38,7 +37,7 @@
static inline const char *getShiftOpcStr(ShiftOpc Op) {
switch (Op) {
- default: llvm_unreachable("Unknown shift opc!");
+ default: assert(0 && "Unknown shift opc!");
case ARM_AM::asr: return "asr";
case ARM_AM::lsl: return "lsl";
case ARM_AM::lsr: return "lsr";
@@ -71,7 +70,7 @@
static inline const char *getAMSubModeStr(AMSubMode Mode) {
switch (Mode) {
- default: llvm_unreachable("Unknown addressing sub-mode!");
+ default: assert(0 && "Unknown addressing sub-mode!");
case ARM_AM::ia: return "ia";
case ARM_AM::ib: return "ib";
case ARM_AM::da: return "da";
@@ -81,7 +80,7 @@
static inline const char *getAMSubModeAltStr(AMSubMode Mode, bool isLD) {
switch (Mode) {
- default: llvm_unreachable("Unknown addressing sub-mode!");
+ default: assert(0 && "Unknown addressing sub-mode!");
case ARM_AM::ia: return isLD ? "fd" : "ea";
case ARM_AM::ib: return isLD ? "ed" : "fa";
case ARM_AM::da: return isLD ? "fa" : "ed";
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/ARMCallingConv.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/ARMCallingConv.td?rev=85841&r1=85840&r2=85841&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/ARMCallingConv.td (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/ARMCallingConv.td Mon Nov 2 17:47:28 2009
@@ -68,6 +68,7 @@
"ArgFlags.getOrigAlign() != 8",
CCAssignToReg<[R0, R1, R2, R3]>>>,
+ CCIfType<[i32], CCIfAlign<"8", CCAssignToStack<4, 8>>>,
CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
CCIfType<[f64], CCAssignToStack<8, 8>>,
CCIfType<[v2f64], CCAssignToStack<16, 8>>
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/ARMISelLowering.cpp?rev=85841&r1=85840&r2=85841&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/ARMISelLowering.cpp Mon Nov 2 17:47:28 2009
@@ -494,6 +494,9 @@
case ARMISD::FMRRD: return "ARMISD::FMRRD";
case ARMISD::FMDRR: return "ARMISD::FMDRR";
+ case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
+ case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP";
+
case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
@@ -2067,7 +2070,7 @@
static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
assert(VT.isVector() && "Expected a vector type");
- // Always build ones vectors as <16 x i32> or <8 x i32> bitcasted to their
+ // Always build ones vectors as <16 x i8> or <8 x i8> bitcasted to their
// dest type. This ensures they get CSE'd.
SDValue Vec;
SDValue Cst = DAG.getTargetConstant(0xFF, MVT::i8);
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrInfo.td?rev=85841&r1=85840&r2=85841&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrInfo.td Mon Nov 2 17:47:28 2009
@@ -685,7 +685,9 @@
def BL : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
IIC_Br, "bl\t${func:call}",
[(ARMcall tglobaladdr:$func)]>,
- Requires<[IsARM, IsNotDarwin]>;
+ Requires<[IsARM, IsNotDarwin]> {
+ let Inst{31-28} = 0b1110;
+ }
def BL_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
IIC_Br, "bl", "\t${func:call}",
@@ -721,7 +723,9 @@
D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
def BLr9 : ABXI<0b1011, (outs), (ins i32imm:$func, variable_ops),
IIC_Br, "bl\t${func:call}",
- [(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsDarwin]>;
+ [(ARMcall tglobaladdr:$func)]>, Requires<[IsARM, IsDarwin]> {
+ let Inst{31-28} = 0b1110;
+ }
def BLr9_pred : ABI<0b1011, (outs), (ins i32imm:$func, variable_ops),
IIC_Br, "bl", "\t${func:call}",
@@ -1105,7 +1109,6 @@
def RSBri : AsI1<0b0011, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPFrm,
IIC_iALUi, "rsb", "\t$dst, $a, $b",
[(set GPR:$dst, (sub so_imm:$b, GPR:$a))]> {
- let Inst{20} = 0;
let Inst{25} = 1;
}
@@ -1114,7 +1117,6 @@
[(set GPR:$dst, (sub so_reg:$b, GPR:$a))]> {
let Inst{4} = 1;
let Inst{7} = 0;
- let Inst{20} = 0;
let Inst{25} = 0;
}
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