[llvm-branch-commits] [llvm-branch] r85710 - in /llvm/branches/Apple/Leela: lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMInstrNEON.td test/CodeGen/ARM/fmacs.ll test/CodeGen/ARM/fnmacs.ll test/CodeGen/ARM/long_shift.ll test/CodeGen/Thumb2/cross-rc-coalescing-2.ll test/CodeGen/Thumb2/thumb2-branch.ll test/CodeGen/Thumb2/thumb2-mov.ll test/CodeGen/Thumb2/thumb2-mov2.ll test/CodeGen/Thumb2/thumb2-mov3.ll test/CodeGen/Thumb2/thumb2-mov4.ll utils/buildit/build_llvm
Bill Wendling
isanbard at gmail.com
Sun Nov 1 01:44:30 PDT 2009
Author: void
Date: Sun Nov 1 02:44:29 2009
New Revision: 85710
URL: http://llvm.org/viewvc/llvm-project?rev=85710&view=rev
Log:
$ svn merge -c 85672 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r85672 into '.':
U utils/buildit/build_llvm
$ svn merge -c 85674 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r85674 into '.':
U test/CodeGen/ARM/long_shift.ll
U test/CodeGen/Thumb2/thumb2-branch.ll
$ svn merge -c 85673 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r85673 into '.':
G test/CodeGen/ARM/long_shift.ll
$ svn merge -c 85675 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r85675 into '.':
G test/CodeGen/ARM/long_shift.ll
U lib/Target/ARM/ARMISelLowering.cpp
$ svn merge -c 85685 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r85685 into '.':
G test/CodeGen/ARM/long_shift.ll
G lib/Target/ARM/ARMISelLowering.cpp
$ svn merge -c 85687 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r85687 into '.':
G test/CodeGen/ARM/long_shift.ll
G lib/Target/ARM/ARMISelLowering.cpp
$ svn merge -c 85689 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r85689 into '.':
G test/CodeGen/ARM/long_shift.ll
$ svn merge -c 85691 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r85691 into '.':
U test/CodeGen/Thumb2/thumb2-mov.ll
$ svn merge -c 85693 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r85693 into '.':
U test/CodeGen/Thumb2/thumb2-mov2.ll
$ svn merge -c 85694 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r85694 into '.':
G test/CodeGen/Thumb2/thumb2-mov2.ll
$ svn merge -c 85695 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r85695 into '.':
U test/CodeGen/Thumb2/thumb2-mov4.ll
$ svn merge -c 85696 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r85696 into '.':
G test/CodeGen/Thumb2/thumb2-mov.ll
D test/CodeGen/Thumb2/thumb2-mov2.ll
D test/CodeGen/Thumb2/thumb2-mov3.ll
D test/CodeGen/Thumb2/thumb2-mov4.ll
$ svn merge -c 85697 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r85697 into '.':
U test/CodeGen/ARM/fmacs.ll
U test/CodeGen/ARM/fnmacs.ll
U test/CodeGen/Thumb2/cross-rc-coalescing-2.ll
U lib/Target/ARM/ARMInstrNEON.td
Removed:
llvm/branches/Apple/Leela/test/CodeGen/Thumb2/thumb2-mov2.ll
llvm/branches/Apple/Leela/test/CodeGen/Thumb2/thumb2-mov3.ll
llvm/branches/Apple/Leela/test/CodeGen/Thumb2/thumb2-mov4.ll
Modified:
llvm/branches/Apple/Leela/lib/Target/ARM/ARMISelLowering.cpp
llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrNEON.td
llvm/branches/Apple/Leela/test/CodeGen/ARM/fmacs.ll
llvm/branches/Apple/Leela/test/CodeGen/ARM/fnmacs.ll
llvm/branches/Apple/Leela/test/CodeGen/ARM/long_shift.ll
llvm/branches/Apple/Leela/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll
llvm/branches/Apple/Leela/test/CodeGen/Thumb2/thumb2-branch.ll
llvm/branches/Apple/Leela/test/CodeGen/Thumb2/thumb2-mov.ll
llvm/branches/Apple/Leela/utils/buildit/build_llvm
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/ARMISelLowering.cpp?rev=85710&r1=85709&r2=85710&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/ARMISelLowering.cpp Sun Nov 1 02:44:29 2009
@@ -329,9 +329,9 @@
if (!Subtarget->hasV6Ops())
setOperationAction(ISD::MULHS, MVT::i32, Expand);
}
- setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
- setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
- setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
+ setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
+ setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
+ setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
setOperationAction(ISD::SRL, MVT::i64, Custom);
setOperationAction(ISD::SRA, MVT::i64, Custom);
@@ -2070,6 +2070,76 @@
return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
}
+/// LowerShiftRightParts - Lower SRA_PARTS, which returns two
+/// i32 values and take a 2 x i32 value to shift plus a shift amount.
+static SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG,
+ const ARMSubtarget *ST) {
+ assert(Op.getNumOperands() == 3 && "Not a double-shift!");
+ EVT VT = Op.getValueType();
+ unsigned VTBits = VT.getSizeInBits();
+ DebugLoc dl = Op.getDebugLoc();
+ SDValue ShOpLo = Op.getOperand(0);
+ SDValue ShOpHi = Op.getOperand(1);
+ SDValue ShAmt = Op.getOperand(2);
+ SDValue ARMCC;
+ unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
+
+ assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
+
+ SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
+ DAG.getConstant(VTBits, MVT::i32), ShAmt);
+ SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
+ SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
+ DAG.getConstant(VTBits, MVT::i32));
+ SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
+ SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
+ SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
+
+ SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
+ SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
+ ARMCC, DAG, ST->isThumb1Only(), dl);
+ SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
+ SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMCC,
+ CCR, Cmp);
+
+ SDValue Ops[2] = { Lo, Hi };
+ return DAG.getMergeValues(Ops, 2, dl);
+}
+
+/// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
+/// i32 values and take a 2 x i32 value to shift plus a shift amount.
+static SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG,
+ const ARMSubtarget *ST) {
+ assert(Op.getNumOperands() == 3 && "Not a double-shift!");
+ EVT VT = Op.getValueType();
+ unsigned VTBits = VT.getSizeInBits();
+ DebugLoc dl = Op.getDebugLoc();
+ SDValue ShOpLo = Op.getOperand(0);
+ SDValue ShOpHi = Op.getOperand(1);
+ SDValue ShAmt = Op.getOperand(2);
+ SDValue ARMCC;
+
+ assert(Op.getOpcode() == ISD::SHL_PARTS);
+ SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
+ DAG.getConstant(VTBits, MVT::i32), ShAmt);
+ SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
+ SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
+ DAG.getConstant(VTBits, MVT::i32));
+ SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
+ SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
+
+ SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
+ SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
+ SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
+ ARMCC, DAG, ST->isThumb1Only(), dl);
+ SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
+ SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMCC,
+ CCR, Cmp);
+
+ SDValue Ops[2] = { Lo, Hi };
+ return DAG.getMergeValues(Ops, 2, dl);
+}
+
static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
const ARMSubtarget *ST) {
EVT VT = N->getValueType(0);
@@ -2761,6 +2831,9 @@
case ISD::SHL:
case ISD::SRL:
case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
+ case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG, Subtarget);
+ case ISD::SRL_PARTS:
+ case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG, Subtarget);
case ISD::VSETCC: return LowerVSETCC(Op, DAG);
case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
Modified: llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrNEON.td?rev=85710&r1=85709&r2=85710&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/branches/Apple/Leela/lib/Target/ARM/ARMInstrNEON.td Sun Nov 1 02:44:29 2009
@@ -2841,13 +2841,16 @@
def : N3VDsPat<fmul, VMULfd_sfp>;
// Vector Multiply-Accumulate/Subtract used for single-precision FP
-let neverHasSideEffects = 1 in
-def VMLAfd_sfp : N3VDMulOps<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla.f32", v2f32,fmul,fadd>;
-def : N3VDMulOpsPat<fmul, fadd, VMLAfd_sfp>;
+// vml[as].f32 can cause 4-8 cycle stalls in following ASIMD instructions, so
+// we want to avoid them for now. e.g., alternating vmla/vadd instructions.
-let neverHasSideEffects = 1 in
-def VMLSfd_sfp : N3VDMulOps<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls.f32", v2f32,fmul,fsub>;
-def : N3VDMulOpsPat<fmul, fsub, VMLSfd_sfp>;
+//let neverHasSideEffects = 1 in
+//def VMLAfd_sfp : N3VDMulOps<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla.f32", v2f32,fmul,fadd>;
+//def : N3VDMulOpsPat<fmul, fadd, VMLAfd_sfp>;
+
+//let neverHasSideEffects = 1 in
+//def VMLSfd_sfp : N3VDMulOps<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls.f32", v2f32,fmul,fsub>;
+//def : N3VDMulOpsPat<fmul, fsub, VMLSfd_sfp>;
// Vector Absolute used for single-precision FP
let neverHasSideEffects = 1 in
Modified: llvm/branches/Apple/Leela/test/CodeGen/ARM/fmacs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/test/CodeGen/ARM/fmacs.ll?rev=85710&r1=85709&r2=85710&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/test/CodeGen/ARM/fmacs.ll (original)
+++ llvm/branches/Apple/Leela/test/CodeGen/ARM/fmacs.ll Sun Nov 1 02:44:29 2009
@@ -1,7 +1,7 @@
; RUN: llc < %s -march=arm -mattr=+vfp2 | grep -E {fmacs\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
-; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | grep -E {vmla.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1
+; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=1 | grep -E {vmul.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1
; RUN: llc < %s -march=arm -mattr=+neon -arm-use-neon-fp=0 | grep -E {fmacs\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
-; RUN: llc < %s -march=arm -mcpu=cortex-a8 | grep -E {vmla.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1
+; RUN: llc < %s -march=arm -mcpu=cortex-a8 | grep -E {vmul.f32\\W*d\[0-9\]+,\\W*d\[0-9\]+,\\W*d\[0-9\]+} | count 1
; RUN: llc < %s -march=arm -mcpu=cortex-a9 | grep -E {fmacs\\W*s\[0-9\]+,\\W*s\[0-9\]+,\\W*s\[0-9\]+} | count 1
define float @test(float %acc, float %a, float %b) {
Modified: llvm/branches/Apple/Leela/test/CodeGen/ARM/fnmacs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/test/CodeGen/ARM/fnmacs.ll?rev=85710&r1=85709&r2=85710&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/test/CodeGen/ARM/fnmacs.ll (original)
+++ llvm/branches/Apple/Leela/test/CodeGen/ARM/fnmacs.ll Sun Nov 1 02:44:29 2009
@@ -7,8 +7,10 @@
; VFP2: fnmacs
; NEON: fnmacs
-; NEONFP: vmls
+; NEONFP-NOT: vmls
; NEONFP-NOT: fcpys
+; NEONFP: vmul.f32
+; NEONFP: vsub.f32
; NEONFP: fmrs
%0 = fmul float %a, %b
Modified: llvm/branches/Apple/Leela/test/CodeGen/ARM/long_shift.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/test/CodeGen/ARM/long_shift.ll?rev=85710&r1=85709&r2=85710&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/test/CodeGen/ARM/long_shift.ll (original)
+++ llvm/branches/Apple/Leela/test/CodeGen/ARM/long_shift.ll Sun Nov 1 02:44:29 2009
@@ -1,10 +1,11 @@
-; RUN: llc < %s -march=arm > %t
-; RUN: grep rrx %t | count 1
-; RUN: grep __ashldi3 %t
-; RUN: grep __ashrdi3 %t
-; RUN: grep __lshrdi3 %t
+; RUN: llc < %s -march=arm | FileCheck %s
define i64 @f0(i64 %A, i64 %B) {
+; CHECK: f0
+; CHECK: movs r3, r3, lsr #1
+; CHECK-NEXT: mov r2, r2, rrx
+; CHECK-NEXT: subs r0, r0, r2
+; CHECK-NEXT: sbc r1, r1, r3
%tmp = bitcast i64 %A to i64
%tmp2 = lshr i64 %B, 1
%tmp3 = sub i64 %tmp, %tmp2
@@ -12,18 +13,34 @@
}
define i32 @f1(i64 %x, i64 %y) {
+; CHECK: f1
+; CHECK: mov r0, r0, lsl r2
%a = shl i64 %x, %y
%b = trunc i64 %a to i32
ret i32 %b
}
define i32 @f2(i64 %x, i64 %y) {
+; CHECK: f2
+; CHECK: mov r0, r0, lsr r2
+; CHECK-NEXT: rsb r3, r2, #32
+; CHECK-NEXT: sub r2, r2, #32
+; CHECK-NEXT: cmp r2, #0
+; CHECK-NEXT: orr r0, r0, r1, lsl r3
+; CHECK-NEXT: movge r0, r1, asr r2
%a = ashr i64 %x, %y
%b = trunc i64 %a to i32
ret i32 %b
}
define i32 @f3(i64 %x, i64 %y) {
+; CHECK: f3
+; CHECK: mov r0, r0, lsr r2
+; CHECK-NEXT: rsb r3, r2, #32
+; CHECK-NEXT: sub r2, r2, #32
+; CHECK-NEXT: cmp r2, #0
+; CHECK-NEXT: orr r0, r0, r1, lsl r3
+; CHECK-NEXT: movge r0, r1, lsr r2
%a = lshr i64 %x, %y
%b = trunc i64 %a to i32
ret i32 %b
Modified: llvm/branches/Apple/Leela/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll?rev=85710&r1=85709&r2=85710&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll (original)
+++ llvm/branches/Apple/Leela/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll Sun Nov 1 02:44:29 2009
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mcpu=cortex-a8 | grep fcpys | count 5
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mcpu=cortex-a8 | grep fcpys | count 4
define arm_apcscc void @fht(float* nocapture %fz, i16 signext %n) nounwind {
entry:
Modified: llvm/branches/Apple/Leela/test/CodeGen/Thumb2/thumb2-branch.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/test/CodeGen/Thumb2/thumb2-branch.ll?rev=85710&r1=85709&r2=85710&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/test/CodeGen/Thumb2/thumb2-branch.ll (original)
+++ llvm/branches/Apple/Leela/test/CodeGen/Thumb2/thumb2-branch.ll Sun Nov 1 02:44:29 2009
@@ -3,7 +3,7 @@
define void @f1(i32 %a, i32 %b, i32* %v) {
entry:
; CHECK: f1:
-; CHECK bne LBB
+; CHECK: bne LBB
%tmp = icmp eq i32 %a, %b ; <i1> [#uses=1]
br i1 %tmp, label %cond_true, label %return
@@ -18,7 +18,7 @@
define void @f2(i32 %a, i32 %b, i32* %v) {
entry:
; CHECK: f2:
-; CHECK bge LBB
+; CHECK: bge LBB
%tmp = icmp slt i32 %a, %b ; <i1> [#uses=1]
br i1 %tmp, label %cond_true, label %return
@@ -33,7 +33,7 @@
define void @f3(i32 %a, i32 %b, i32* %v) {
entry:
; CHECK: f3:
-; CHECK bhs LBB
+; CHECK: bhs LBB
%tmp = icmp ult i32 %a, %b ; <i1> [#uses=1]
br i1 %tmp, label %cond_true, label %return
@@ -48,7 +48,7 @@
define void @f4(i32 %a, i32 %b, i32* %v) {
entry:
; CHECK: f4:
-; CHECK blo LBB
+; CHECK: blo LBB
%tmp = icmp ult i32 %a, %b ; <i1> [#uses=1]
br i1 %tmp, label %return, label %cond_true
Modified: llvm/branches/Apple/Leela/test/CodeGen/Thumb2/thumb2-mov.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/test/CodeGen/Thumb2/thumb2-mov.ll?rev=85710&r1=85709&r2=85710&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/test/CodeGen/Thumb2/thumb2-mov.ll (original)
+++ llvm/branches/Apple/Leela/test/CodeGen/Thumb2/thumb2-mov.ll Sun Nov 1 02:44:29 2009
@@ -5,38 +5,40 @@
; var 2.1 - 0x00ab00ab
define i32 @t2_const_var2_1_ok_1(i32 %lhs) {
;CHECK: t2_const_var2_1_ok_1:
-;CHECK: #11206827
+;CHECK: add.w r0, r0, #11206827
%ret = add i32 %lhs, 11206827 ; 0x00ab00ab
ret i32 %ret
}
define i32 @t2_const_var2_1_ok_2(i32 %lhs) {
;CHECK: t2_const_var2_1_ok_2:
-;CHECK: #11206656
-;CHECK: #187
+;CHECK: add.w r0, r0, #11206656
+;CHECK: adds r0, #187
%ret = add i32 %lhs, 11206843 ; 0x00ab00bb
ret i32 %ret
}
define i32 @t2_const_var2_1_ok_3(i32 %lhs) {
;CHECK: t2_const_var2_1_ok_3:
-;CHECK: #11206827
-;CHECK: #16777216
+;CHECK: add.w r0, r0, #11206827
+;CHECK: add.w r0, r0, #16777216
%ret = add i32 %lhs, 27984043 ; 0x01ab00ab
ret i32 %ret
}
define i32 @t2_const_var2_1_ok_4(i32 %lhs) {
;CHECK: t2_const_var2_1_ok_4:
-;CHECK: #16777472
-;CHECK: #11206827
+;CHECK: add.w r0, r0, #16777472
+;CHECK: add.w r0, r0, #11206827
%ret = add i32 %lhs, 27984299 ; 0x01ab01ab
ret i32 %ret
}
define i32 @t2_const_var2_1_fail_1(i32 %lhs) {
;CHECK: t2_const_var2_1_fail_1:
-;CHECK: movt
+;CHECK: movw r1, #43777
+;CHECK: movt r1, #427
+;CHECK: add r0, r1
%ret = add i32 %lhs, 28027649 ; 0x01abab01
ret i32 %ret
}
@@ -44,37 +46,40 @@
; var 2.2 - 0xab00ab00
define i32 @t2_const_var2_2_ok_1(i32 %lhs) {
;CHECK: t2_const_var2_2_ok_1:
-;CHECK: #-1426019584
+;CHECK: add.w r0, r0, #-1426019584
%ret = add i32 %lhs, 2868947712 ; 0xab00ab00
ret i32 %ret
}
define i32 @t2_const_var2_2_ok_2(i32 %lhs) {
;CHECK: t2_const_var2_2_ok_2:
-;CHECK: #-1426063360
-;CHECK: #47616
+;CHECK: add.w r0, r0, #-1426063360
+;CHECK: add.w r0, r0, #47616
%ret = add i32 %lhs, 2868951552 ; 0xab00ba00
ret i32 %ret
}
define i32 @t2_const_var2_2_ok_3(i32 %lhs) {
;CHECK: t2_const_var2_2_ok_3:
-;CHECK: #-1426019584
+;CHECK: add.w r0, r0, #-1426019584
+;CHECK: adds r0, #16
%ret = add i32 %lhs, 2868947728 ; 0xab00ab10
ret i32 %ret
}
define i32 @t2_const_var2_2_ok_4(i32 %lhs) {
;CHECK: t2_const_var2_2_ok_4:
-;CHECK: #-1426019584
-;CHECK: #1048592
+;CHECK: add.w r0, r0, #-1426019584
+;CHECK: add.w r0, r0, #1048592
%ret = add i32 %lhs, 2869996304 ; 0xab10ab10
ret i32 %ret
}
define i32 @t2_const_var2_2_fail_1(i32 %lhs) {
;CHECK: t2_const_var2_2_fail_1:
-;CHECK: movt
+;CHECK: movw r1, #43792
+;CHECK: movt r1, #4267
+;CHECK: add r0, r1
%ret = add i32 %lhs, 279685904 ; 0x10abab10
ret i32 %ret
}
@@ -82,35 +87,43 @@
; var 2.3 - 0xabababab
define i32 @t2_const_var2_3_ok_1(i32 %lhs) {
;CHECK: t2_const_var2_3_ok_1:
-;CHECK: #-1414812757
+;CHECK: add.w r0, r0, #-1414812757
%ret = add i32 %lhs, 2880154539 ; 0xabababab
ret i32 %ret
}
define i32 @t2_const_var2_3_fail_1(i32 %lhs) {
;CHECK: t2_const_var2_3_fail_1:
-;CHECK: movt
+;CHECK: movw r1, #43962
+;CHECK: movt r1, #43947
+;CHECK: add r0, r1
%ret = add i32 %lhs, 2880154554 ; 0xabababba
ret i32 %ret
}
define i32 @t2_const_var2_3_fail_2(i32 %lhs) {
;CHECK: t2_const_var2_3_fail_2:
-;CHECK: movt
+;CHECK: movw r1, #47787
+;CHECK: movt r1, #43947
+;CHECK: add r0, r1
%ret = add i32 %lhs, 2880158379 ; 0xababbaab
ret i32 %ret
}
define i32 @t2_const_var2_3_fail_3(i32 %lhs) {
;CHECK: t2_const_var2_3_fail_3:
-;CHECK: movt
+;CHECK: movw r1, #43947
+;CHECK: movt r1, #43962
+;CHECK: add r0, r1
%ret = add i32 %lhs, 2881137579 ; 0xabbaabab
ret i32 %ret
}
define i32 @t2_const_var2_3_fail_4(i32 %lhs) {
;CHECK: t2_const_var2_3_fail_4:
-;CHECK: movt
+;CHECK: movw r1, #43947
+;CHECK: movt r1, #47787
+;CHECK: add r0, r1
%ret = add i32 %lhs, 3131812779 ; 0xbaababab
ret i32 %ret
}
@@ -118,36 +131,136 @@
; var 3 - 0x0F000000
define i32 @t2_const_var3_1_ok_1(i32 %lhs) {
;CHECK: t2_const_var3_1_ok_1:
-;CHECK: #251658240
+;CHECK: add.w r0, r0, #251658240
%ret = add i32 %lhs, 251658240 ; 0x0F000000
ret i32 %ret
}
define i32 @t2_const_var3_2_ok_1(i32 %lhs) {
;CHECK: t2_const_var3_2_ok_1:
-;CHECK: #3948544
+;CHECK: add.w r0, r0, #3948544
%ret = add i32 %lhs, 3948544 ; 0b00000000001111000100000000000000
ret i32 %ret
}
define i32 @t2_const_var3_2_ok_2(i32 %lhs) {
;CHECK: t2_const_var3_2_ok_2:
-;CHECK: #2097152
-;CHECK: #1843200
+;CHECK: add.w r0, r0, #2097152
+;CHECK: add.w r0, r0, #1843200
%ret = add i32 %lhs, 3940352 ; 0b00000000001111000010000000000000
ret i32 %ret
}
define i32 @t2_const_var3_3_ok_1(i32 %lhs) {
;CHECK: t2_const_var3_3_ok_1:
-;CHECK: #258
+;CHECK: add.w r0, r0, #258
%ret = add i32 %lhs, 258 ; 0b00000000000000000000000100000010
ret i32 %ret
}
define i32 @t2_const_var3_4_ok_1(i32 %lhs) {
;CHECK: t2_const_var3_4_ok_1:
-;CHECK: #-268435456
+;CHECK: add.w r0, r0, #-268435456
%ret = add i32 %lhs, 4026531840 ; 0xF0000000
ret i32 %ret
}
+
+define i32 @t2MOVTi16_ok_1(i32 %a) {
+; CHECK: t2MOVTi16_ok_1:
+; CHECK: movt r0, #1234
+ %1 = and i32 %a, 65535
+ %2 = shl i32 1234, 16
+ %3 = or i32 %1, %2
+
+ ret i32 %3
+}
+
+define i32 @t2MOVTi16_test_1(i32 %a) {
+; CHECK: t2MOVTi16_test_1:
+; CHECK: movt r0, #1234
+ %1 = shl i32 255, 8
+ %2 = shl i32 1234, 8
+ %3 = or i32 %1, 255 ; This gives us 0xFFFF in %3
+ %4 = shl i32 %2, 8 ; This gives us (1234 << 16) in %4
+ %5 = and i32 %a, %3
+ %6 = or i32 %4, %5
+
+ ret i32 %6
+}
+
+define i32 @t2MOVTi16_test_2(i32 %a) {
+; CHECK: t2MOVTi16_test_2:
+; CHECK: movt r0, #1234
+ %1 = shl i32 255, 8
+ %2 = shl i32 1234, 8
+ %3 = or i32 %1, 255 ; This gives us 0xFFFF in %3
+ %4 = shl i32 %2, 6
+ %5 = and i32 %a, %3
+ %6 = shl i32 %4, 2 ; This gives us (1234 << 16) in %6
+ %7 = or i32 %5, %6
+
+ ret i32 %7
+}
+
+define i32 @t2MOVTi16_test_3(i32 %a) {
+; CHECK: t2MOVTi16_test_3:
+; CHECK: movt r0, #1234
+ %1 = shl i32 255, 8
+ %2 = shl i32 1234, 8
+ %3 = or i32 %1, 255 ; This gives us 0xFFFF in %3
+ %4 = shl i32 %2, 6
+ %5 = and i32 %a, %3
+ %6 = shl i32 %4, 2 ; This gives us (1234 << 16) in %6
+ %7 = lshr i32 %6, 6
+ %8 = shl i32 %7, 6
+ %9 = or i32 %5, %8
+
+ ret i32 %8
+}
+
+; 171 = 0x000000ab
+define i32 @f1(i32 %a) {
+; CHECK: f1:
+; CHECK: movs r0, #171
+ %tmp = add i32 0, 171
+ ret i32 %tmp
+}
+
+; 1179666 = 0x00120012
+define i32 @f2(i32 %a) {
+; CHECK: f2:
+; CHECK: mov.w r0, #1179666
+ %tmp = add i32 0, 1179666
+ ret i32 %tmp
+}
+
+; 872428544 = 0x34003400
+define i32 @f3(i32 %a) {
+; CHECK: f3:
+; CHECK: mov.w r0, #872428544
+ %tmp = add i32 0, 872428544
+ ret i32 %tmp
+}
+
+; 1448498774 = 0x56565656
+define i32 @f4(i32 %a) {
+; CHECK: f4:
+; CHECK: mov.w r0, #1448498774
+ %tmp = add i32 0, 1448498774
+ ret i32 %tmp
+}
+
+; 66846720 = 0x03fc0000
+define i32 @f5(i32 %a) {
+; CHECK: f5:
+; CHECK: mov.w r0, #66846720
+ %tmp = add i32 0, 66846720
+ ret i32 %tmp
+}
+
+define i32 @f6(i32 %a) {
+;CHECK: f6
+;CHECK: movw r0, #65535
+ %tmp = add i32 0, 65535
+ ret i32 %tmp
+}
Removed: llvm/branches/Apple/Leela/test/CodeGen/Thumb2/thumb2-mov2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/test/CodeGen/Thumb2/thumb2-mov2.ll?rev=85709&view=auto
==============================================================================
--- llvm/branches/Apple/Leela/test/CodeGen/Thumb2/thumb2-mov2.ll (original)
+++ llvm/branches/Apple/Leela/test/CodeGen/Thumb2/thumb2-mov2.ll (removed)
@@ -1,73 +0,0 @@
-; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
-
-define i32 @t2MOVTi16_ok_1(i32 %a) {
-; CHECK: t2MOVTi16_ok_1:
-; CHECK: movt r0, #1234
- %1 = and i32 %a, 65535
- %2 = shl i32 1234, 16
- %3 = or i32 %1, %2
-
- ret i32 %3
-}
-
-define i32 @t2MOVTi16_test_1(i32 %a) {
-; CHECK: t2MOVTi16_test_1:
-; CHECK: movt r0, #1234
- %1 = shl i32 255, 8
- %2 = shl i32 1234, 8
- %3 = or i32 %1, 255 ; This give us 0xFFFF in %3
- %4 = shl i32 %2, 8 ; This gives us (1234 << 16) in %4
- %5 = and i32 %a, %3
- %6 = or i32 %4, %5
-
- ret i32 %6
-}
-
-define i32 @t2MOVTi16_test_2(i32 %a) {
-; CHECK: t2MOVTi16_test_2:
-; CHECK: movt r0, #1234
- %1 = shl i32 255, 8
- %2 = shl i32 1234, 8
- %3 = or i32 %1, 255 ; This give us 0xFFFF in %3
- %4 = shl i32 %2, 6
- %5 = and i32 %a, %3
- %6 = shl i32 %4, 2 ; This gives us (1234 << 16) in %6
- %7 = or i32 %5, %6
-
- ret i32 %7
-}
-
-define i32 @t2MOVTi16_test_3(i32 %a) {
-; CHECK: t2MOVTi16_test_3:
-; CHECK: movt r0, #1234
- %1 = shl i32 255, 8
- %2 = shl i32 1234, 8
- %3 = or i32 %1, 255 ; This give us 0xFFFF in %3
- %4 = shl i32 %2, 6
- %5 = and i32 %a, %3
- %6 = shl i32 %4, 2 ; This gives us (1234 << 16) in %6
- %7 = lshr i32 %6, 6
- %8 = shl i32 %7, 6
- %9 = or i32 %5, %8
-
- ret i32 %9
-}
-
-define i32 @t2MOVTi16_test_nomatch_1(i32 %a) {
-; CHECK: t2MOVTi16_test_nomatch_1:
-; CHECK: #8388608
-; CHECK: movw r1, #65535
-; CHECK-NEXT: movt r1, #154
-; CHECK: #1720320
- %1 = shl i32 255, 8
- %2 = shl i32 1234, 8
- %3 = or i32 %1, 255 ; This give us 0xFFFF in %3
- %4 = shl i32 %2, 6
- %5 = and i32 %a, %3
- %6 = shl i32 %4, 2 ; This gives us (1234 << 16) in %6
- %7 = lshr i32 %6, 3
- %8 = or i32 %5, %7
- ret i32 %8
-}
-
-
Removed: llvm/branches/Apple/Leela/test/CodeGen/Thumb2/thumb2-mov3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/test/CodeGen/Thumb2/thumb2-mov3.ll?rev=85709&view=auto
==============================================================================
--- llvm/branches/Apple/Leela/test/CodeGen/Thumb2/thumb2-mov3.ll (original)
+++ llvm/branches/Apple/Leela/test/CodeGen/Thumb2/thumb2-mov3.ll (removed)
@@ -1,41 +0,0 @@
-; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
-
-; 171 = 0x000000ab
-define i32 @f1(i32 %a) {
-; CHECK: f1:
-; CHECK: movs r0, #171
- %tmp = add i32 0, 171
- ret i32 %tmp
-}
-
-; 1179666 = 0x00120012
-define i32 @f2(i32 %a) {
-; CHECK: f2:
-; CHECK: mov.w r0, #1179666
- %tmp = add i32 0, 1179666
- ret i32 %tmp
-}
-
-; 872428544 = 0x34003400
-define i32 @f3(i32 %a) {
-; CHECK: f3:
-; CHECK: mov.w r0, #872428544
- %tmp = add i32 0, 872428544
- ret i32 %tmp
-}
-
-; 1448498774 = 0x56565656
-define i32 @f4(i32 %a) {
-; CHECK: f4:
-; CHECK: mov.w r0, #1448498774
- %tmp = add i32 0, 1448498774
- ret i32 %tmp
-}
-
-; 66846720 = 0x03fc0000
-define i32 @f5(i32 %a) {
-; CHECK: f5:
-; CHECK: mov.w r0, #66846720
- %tmp = add i32 0, 66846720
- ret i32 %tmp
-}
Removed: llvm/branches/Apple/Leela/test/CodeGen/Thumb2/thumb2-mov4.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/test/CodeGen/Thumb2/thumb2-mov4.ll?rev=85709&view=auto
==============================================================================
--- llvm/branches/Apple/Leela/test/CodeGen/Thumb2/thumb2-mov4.ll (original)
+++ llvm/branches/Apple/Leela/test/CodeGen/Thumb2/thumb2-mov4.ll (removed)
@@ -1,6 +0,0 @@
-; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep {movw\\W*r\[0-9\],\\W*#\[0-9\]*} | grep {#65535} | count 1
-
-define i32 @f6(i32 %a) {
- %tmp = add i32 0, 65535
- ret i32 %tmp
-}
Modified: llvm/branches/Apple/Leela/utils/buildit/build_llvm
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Leela/utils/buildit/build_llvm?rev=85710&r1=85709&r2=85710&view=diff
==============================================================================
--- llvm/branches/Apple/Leela/utils/buildit/build_llvm (original)
+++ llvm/branches/Apple/Leela/utils/buildit/build_llvm Sun Nov 1 02:44:29 2009
@@ -62,6 +62,7 @@
elif [ "x$RC_ProjectName" = "xllvmCore_EmbeddedHosted" ]; then
DT_HOME=$DEST_DIR/usr
DEST_ROOT="/Developer$DEST_ROOT"
+ HOST_SDKROOT=$SDKROOT
else
DT_HOME=$DEST_DIR/Developer/usr
DEST_ROOT="/Developer$DEST_ROOT"
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