[llvm-branch-commits] [llvm-branch] r71577 - in /llvm/branches/Apple/Dib: lib/CodeGen/LLVMTargetMachine.cpp lib/CodeGen/StackSlotColoring.cpp test/CodeGen/X86/stack-color-with-reg-2.ll test/CodeGen/X86/stack-color-with-reg.ll
Bill Wendling
isanbard at gmail.com
Tue May 12 11:58:16 PDT 2009
Author: void
Date: Tue May 12 13:58:16 2009
New Revision: 71577
URL: http://llvm.org/viewvc/llvm-project?rev=71577&view=rev
Log:
--- Merging r71574 into '.':
U test/CodeGen/X86/stack-color-with-reg.ll
A test/CodeGen/X86/stack-color-with-reg-2.ll
U lib/CodeGen/StackSlotColoring.cpp
U lib/CodeGen/LLVMTargetMachine.cpp
Fixed a stack slot coloring with reg bug: do not update implicit use / def when
doing forward / backward propagation.
Added:
llvm/branches/Apple/Dib/test/CodeGen/X86/stack-color-with-reg-2.ll
- copied unchanged from r71574, llvm/trunk/test/CodeGen/X86/stack-color-with-reg-2.ll
Modified:
llvm/branches/Apple/Dib/lib/CodeGen/LLVMTargetMachine.cpp
llvm/branches/Apple/Dib/lib/CodeGen/StackSlotColoring.cpp
llvm/branches/Apple/Dib/test/CodeGen/X86/stack-color-with-reg.ll
Modified: llvm/branches/Apple/Dib/lib/CodeGen/LLVMTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/LLVMTargetMachine.cpp?rev=71577&r1=71576&r2=71577&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/CodeGen/LLVMTargetMachine.cpp (original)
+++ llvm/branches/Apple/Dib/lib/CodeGen/LLVMTargetMachine.cpp Tue May 12 13:58:16 2009
@@ -193,8 +193,7 @@
// Perform stack slot coloring.
if (OptLevel != CodeGenOpt::None)
- PM.add(createStackSlotColoringPass(false));
- /*OptLevel >= CodeGenOpt::Aggressive*/
+ PM.add(createStackSlotColoringPass(OptLevel >= CodeGenOpt::Aggressive));
if (PrintMachineCode) // Print the register-allocated code
PM.add(createMachineFunctionPrinterPass(cerr));
Modified: llvm/branches/Apple/Dib/lib/CodeGen/StackSlotColoring.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/StackSlotColoring.cpp?rev=71577&r1=71576&r2=71577&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/CodeGen/StackSlotColoring.cpp (original)
+++ llvm/branches/Apple/Dib/lib/CodeGen/StackSlotColoring.cpp Tue May 12 13:58:16 2009
@@ -26,6 +26,7 @@
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/ADT/BitVector.h"
+#include "llvm/ADT/SmallSet.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include <vector>
@@ -129,6 +130,7 @@
unsigned OldReg, unsigned NewReg);
void UnfoldAndRewriteInstruction(MachineInstr *MI, int OldFI,
unsigned Reg, const TargetRegisterClass *RC,
+ SmallSet<unsigned, 4> &Defs,
MachineFunction &MF);
bool AllMemRefsCanBeUnfolded(int SS);
bool RemoveDeadStores(MachineBasicBlock* MBB);
@@ -391,20 +393,23 @@
return false;
// Rewrite all MO_FrameIndex operands.
+ SmallVector<SmallSet<unsigned, 4>, 4> NewDefs(MF.getNumBlockIDs());
for (unsigned SS = 0, SE = SSRefs.size(); SS != SE; ++SS) {
bool isReg = SlotIsReg[SS];
int NewFI = SlotMapping[SS];
if (NewFI == -1 || (NewFI == (int)SS && !isReg))
continue;
+ const TargetRegisterClass *RC = LS->getIntervalRegClass(SS);
SmallVector<MachineInstr*, 8> &RefMIs = SSRefs[SS];
for (unsigned i = 0, e = RefMIs.size(); i != e; ++i)
if (!isReg)
RewriteInstruction(RefMIs[i], SS, NewFI, MF);
else {
// Rewrite to use a register instead.
- const TargetRegisterClass *RC = LS->getIntervalRegClass(SS);
- UnfoldAndRewriteInstruction(RefMIs[i], SS, NewFI, RC, MF);
+ unsigned MBBId = RefMIs[i]->getParent()->getNumber();
+ SmallSet<unsigned, 4> &Defs = NewDefs[MBBId];
+ UnfoldAndRewriteInstruction(RefMIs[i], SS, NewFI, RC, Defs, MF);
}
}
@@ -481,11 +486,12 @@
if (MII == MBB->begin())
return false;
+ SmallVector<MachineOperand*, 4> Uses;
SmallVector<MachineOperand*, 4> Refs;
while (--MII != MBB->begin()) {
bool FoundDef = false; // Not counting 2address def.
- bool FoundUse = false;
- bool FoundKill = false;
+
+ Uses.clear();
const TargetInstrDesc &TID = MII->getDesc();
for (unsigned i = 0, e = MII->getNumOperands(); i != e; ++i) {
MachineOperand &MO = MII->getOperand(i);
@@ -495,15 +501,14 @@
if (Reg == 0)
continue;
if (Reg == OldReg) {
+ if (MO.isImplicit())
+ return false;
const TargetRegisterClass *RC = getInstrOperandRegClass(TRI, TID, i);
if (RC && !RC->contains(NewReg))
return false;
if (MO.isUse()) {
- FoundUse = true;
- if (MO.isKill())
- FoundKill = true;
- Refs.push_back(&MO);
+ Uses.push_back(&MO);
} else {
Refs.push_back(&MO);
if (!MII->isRegTiedToUseOperand(i))
@@ -516,11 +521,17 @@
return false;
}
}
+
if (FoundDef) {
+ // Found non-two-address def. Stop here.
for (unsigned i = 0, e = Refs.size(); i != e; ++i)
Refs[i]->setReg(NewReg);
return true;
}
+
+ // Two-address uses must be updated as well.
+ for (unsigned i = 0, e = Uses.size(); i != e; ++i)
+ Refs.push_back(Uses[i]);
}
return false;
}
@@ -547,7 +558,7 @@
if (Reg == 0)
continue;
if (Reg == OldReg) {
- if (MO.isDef())
+ if (MO.isDef() || MO.isImplicit())
return false;
const TargetRegisterClass *RC = getInstrOperandRegClass(TRI, TID, i);
@@ -573,10 +584,12 @@
/// UnfoldAndRewriteInstruction - Rewrite specified instruction by unfolding
/// folded memory references and replacing those references with register
/// references instead.
-void StackSlotColoring::UnfoldAndRewriteInstruction(MachineInstr *MI, int OldFI,
- unsigned Reg,
- const TargetRegisterClass *RC,
- MachineFunction &MF) {
+void
+StackSlotColoring::UnfoldAndRewriteInstruction(MachineInstr *MI, int OldFI,
+ unsigned Reg,
+ const TargetRegisterClass *RC,
+ SmallSet<unsigned, 4> &Defs,
+ MachineFunction &MF) {
MachineBasicBlock *MBB = MI->getParent();
if (unsigned DstReg = TII->isLoadFromStackSlot(MI, OldFI)) {
if (PropagateForward(MI, MBB, DstReg, Reg)) {
@@ -587,6 +600,13 @@
TII->copyRegToReg(*MBB, MI, DstReg, Reg, RC, RC);
++NumRegRepl;
}
+
+ if (!Defs.count(Reg)) {
+ // If this is the first use of Reg in this MBB and it wasn't previously
+ // defined in MBB, add it to livein.
+ MBB->addLiveIn(Reg);
+ Defs.insert(Reg);
+ }
} else if (unsigned SrcReg = TII->isStoreToStackSlot(MI, OldFI)) {
if (MI->killsRegister(SrcReg) && PropagateBackward(MI, MBB, SrcReg, Reg)) {
DOUT << "Eliminated store: ";
@@ -596,12 +616,24 @@
TII->copyRegToReg(*MBB, MI, Reg, SrcReg, RC, RC);
++NumRegRepl;
}
+
+ // Remember reg has been defined in MBB.
+ Defs.insert(Reg);
} else {
SmallVector<MachineInstr*, 4> NewMIs;
bool Success = TII->unfoldMemoryOperand(MF, MI, Reg, false, false, NewMIs);
assert(Success && "Failed to unfold!");
- MBB->insert(MI, NewMIs[0]);
+ MachineInstr *NewMI = NewMIs[0];
+ MBB->insert(MI, NewMI);
++NumRegRepl;
+
+ if (NewMI->readsRegister(Reg)) {
+ if (!Defs.count(Reg))
+ // If this is the first use of Reg in this MBB and it wasn't previously
+ // defined in MBB, add it to livein.
+ MBB->addLiveIn(Reg);
+ Defs.insert(Reg);
+ }
}
MBB->erase(MI);
}
Modified: llvm/branches/Apple/Dib/test/CodeGen/X86/stack-color-with-reg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/test/CodeGen/X86/stack-color-with-reg.ll?rev=71577&r1=71576&r2=71577&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/test/CodeGen/X86/stack-color-with-reg.ll (original)
+++ llvm/branches/Apple/Dib/test/CodeGen/X86/stack-color-with-reg.ll Tue May 12 13:58:16 2009
@@ -1,7 +1,6 @@
-; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin10 -relocation-model=pic -disable-fp-elim -O3 -stats -info-output-file - > %t
+; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin10 -relocation-model=pic -disable-fp-elim -color-ss-with-regs -stats -info-output-file - > %t
; RUN: grep stackcoloring %t | grep "loads eliminated"
; RUN: grep stackcoloring %t | grep "stores eliminated"
-; XFAIL: *
type { [62 x %struct.Bitvec*] } ; type %0
type { i8* } ; type %1
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