[llvm-branch-commits] [llvm-branch] r74063 - in /llvm/branches/Apple/Bender: lib/CodeGen/MachineInstr.cpp test/CodeGen/X86/inline-asm-tied.ll

[Bill Wendling]

Author: void
Date: Wed Jun 24 00:14:50 2009
New Revision: 74063

URL: http://llvm.org/viewvc/llvm-project?rev=74063&view=rev
Log:
--- Merging r74053 into '.':
A    test/CodeGen/X86/inline-asm-tied.ll
U    lib/CodeGen/MachineInstr.cpp

Fix support for inline asm input / output operand tying when operand spans
across multiple registers (e.g. two i64 operands in 32-bit mode).

Added:
    llvm/branches/Apple/Bender/test/CodeGen/X86/inline-asm-tied.ll
      - copied unchanged from r74053, llvm/trunk/test/CodeGen/X86/inline-asm-tied.ll
Modified:
    llvm/branches/Apple/Bender/lib/CodeGen/MachineInstr.cpp

Modified: llvm/branches/Apple/Bender/lib/CodeGen/MachineInstr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Bender/lib/CodeGen/MachineInstr.cpp?rev=74063&r1=74062&r2=74063&view=diff

==============================================================================
--- llvm/branches/Apple/Bender/lib/CodeGen/MachineInstr.cpp (original)
+++ llvm/branches/Apple/Bender/lib/CodeGen/MachineInstr.cpp Wed Jun 24 00:14:50 2009
@@ -716,31 +716,37 @@
     const MachineOperand &MO = getOperand(DefOpIdx);
     if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
       return false;
-    // Determine the actual operand no corresponding to this index.
+    // Determine the actual operand index that corresponds to this index.
     unsigned DefNo = 0;
+    unsigned DefPart = 0;
     for (unsigned i = 1, e = getNumOperands(); i < e; ) {
       const MachineOperand &FMO = getOperand(i);
       assert(FMO.isImm());
       // Skip over this def.
-      i += InlineAsm::getNumOperandRegisters(FMO.getImm()) + 1;
-      if (i > DefOpIdx)
+      unsigned NumOps = InlineAsm::getNumOperandRegisters(FMO.getImm());
+      unsigned PrevDef = i + 1;
+      i = PrevDef + NumOps;
+      if (i > DefOpIdx) {
+        DefPart = DefOpIdx - PrevDef;
         break;
+      }
       ++DefNo;
     }
-    for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
+    for (unsigned i = 1, e = getNumOperands(); i != e; ++i) {
       const MachineOperand &FMO = getOperand(i);
       if (!FMO.isImm())
         continue;
       if (i+1 >= e || !getOperand(i+1).isReg() || !getOperand(i+1).isUse())
         continue;
       unsigned Idx;
-      if (InlineAsm::isUseOperandTiedToDef(FMO.getImm(), Idx) && 
+      if (InlineAsm::isUseOperandTiedToDef(FMO.getImm(), Idx) &&
           Idx == DefNo) {
         if (UseOpIdx)
-          *UseOpIdx = (unsigned)i + 1;
+          *UseOpIdx = (unsigned)i + 1 + DefPart;
         return true;
       }
     }
+    return false;
   }
 
   assert(getOperand(DefOpIdx).isDef() && "DefOpIdx is not a def!");
@@ -765,10 +771,16 @@
     const MachineOperand &MO = getOperand(UseOpIdx);
     if (!MO.isReg() || !MO.isUse() || MO.getReg() == 0)
       return false;
-    assert(UseOpIdx > 0);
-    const MachineOperand &UFMO = getOperand(UseOpIdx-1);
-    if (!UFMO.isImm())
-      return false;  // Must be physreg uses.
+    int FlagIdx = UseOpIdx - 1;
+    if (FlagIdx < 1)
+      return false;
+    while (!getOperand(FlagIdx).isImm()) {
+      if (--FlagIdx == 0)
+        return false;
+    }
+    const MachineOperand &UFMO = getOperand(FlagIdx);
+    if (FlagIdx + InlineAsm::getNumOperandRegisters(UFMO.getImm()) < UseOpIdx)
+      return false;
     unsigned DefNo;
     if (InlineAsm::isUseOperandTiedToDef(UFMO.getImm(), DefNo)) {
       if (!DefOpIdx)
@@ -784,7 +796,7 @@
         DefIdx += InlineAsm::getNumOperandRegisters(FMO.getImm()) + 1;
         --DefNo;
       }
-      *DefOpIdx = DefIdx+1;
+      *DefOpIdx = DefIdx + UseOpIdx - FlagIdx;
       return true;
     }
     return false;