[llvm-branch-commits] [llvm-branch] r72877 - in /llvm/branches/Apple/Bender/lib/Target/X86: X86CodeEmitter.cpp X86InstrInfo.cpp X86InstrSSE.td
Bill Wendling
isanbard at gmail.com
Thu Jun 4 11:37:26 PDT 2009
Author: void
Date: Thu Jun 4 13:37:26 2009
New Revision: 72877
URL: http://llvm.org/viewvc/llvm-project?rev=72877&view=rev
Log:
Merge in 72556:
The MONITOR and MWAIT instructions have insufficient information for
decoding. Essentially, they both map to the same column in the "opcode
extensions for one- and two-byte opcodes" table in the x86 manual. The RawFrm
complicates decoding this.
Instead, use opcode 0x01, prefix 0x01, and form MRM1r. Then have the code
emitter special case these, a la [SML]FENCE.
Modified:
llvm/branches/Apple/Bender/lib/Target/X86/X86CodeEmitter.cpp
llvm/branches/Apple/Bender/lib/Target/X86/X86InstrInfo.cpp
llvm/branches/Apple/Bender/lib/Target/X86/X86InstrSSE.td
Modified: llvm/branches/Apple/Bender/lib/Target/X86/X86CodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Bender/lib/Target/X86/X86CodeEmitter.cpp?rev=72877&r1=72876&r2=72877&view=diff
==============================================================================
--- llvm/branches/Apple/Bender/lib/Target/X86/X86CodeEmitter.cpp (original)
+++ llvm/branches/Apple/Bender/lib/Target/X86/X86CodeEmitter.cpp Thu Jun 4 13:37:26 2009
@@ -338,8 +338,8 @@
unsigned BaseReg = Base.getReg();
// Is a SIB byte needed?
- if ((!Is64BitMode || DispForReloc) && IndexReg.getReg() == 0 &&
- (BaseReg == 0 || getX86RegNum(BaseReg) != N86::ESP)) {
+ if (IndexReg.getReg() == 0 && (!Is64BitMode || BaseReg != 0) &&
+ (BaseReg == 0 || getX86RegNum(BaseReg) != N86::ESP)) {
if (BaseReg == 0) { // Just a displacement?
// Emit special case [disp32] encoding
MCE.emitByte(ModRMByte(0, RegOpcodeField, 5));
@@ -670,13 +670,26 @@
case X86II::MRM6r: case X86II::MRM7r: {
MCE.emitByte(BaseOpcode);
- // Special handling of lfence and mfence.
+ // Special handling of lfence, mfence, monitor, and mwait.
if (Desc->getOpcode() == X86::LFENCE ||
- Desc->getOpcode() == X86::MFENCE)
+ Desc->getOpcode() == X86::MFENCE ||
+ Desc->getOpcode() == X86::MONITOR ||
+ Desc->getOpcode() == X86::MWAIT) {
emitRegModRMByte((Desc->TSFlags & X86II::FormMask)-X86II::MRM0r);
- else
+
+ switch (Desc->getOpcode()) {
+ default: break;
+ case X86::MONITOR:
+ MCE.emitByte(0xC8);
+ break;
+ case X86::MWAIT:
+ MCE.emitByte(0xC9);
+ break;
+ }
+ } else {
emitRegModRMByte(MI.getOperand(CurOp++).getReg(),
(Desc->TSFlags & X86II::FormMask)-X86II::MRM0r);
+ }
if (CurOp != NumOps) {
const MachineOperand &MO1 = MI.getOperand(CurOp++);
Modified: llvm/branches/Apple/Bender/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Bender/lib/Target/X86/X86InstrInfo.cpp?rev=72877&r1=72876&r2=72877&view=diff
==============================================================================
--- llvm/branches/Apple/Bender/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/branches/Apple/Bender/lib/Target/X86/X86InstrInfo.cpp Thu Jun 4 13:37:26 2009
@@ -2811,8 +2811,8 @@
unsigned BaseReg = Base.getReg();
// Is a SIB byte needed?
- if ((!Is64BitMode || DispForReloc) && IndexReg.getReg() == 0 &&
- (BaseReg == 0 || X86RegisterInfo::getX86RegNum(BaseReg) != N86::ESP)) {
+ if (IndexReg.getReg() == 0 && (!Is64BitMode || BaseReg != 0) &&
+ (BaseReg == 0 || X86RegisterInfo::getX86RegNum(BaseReg) != N86::ESP)) {
if (BaseReg == 0) { // Just a displacement?
// Emit special case [disp32] encoding
++FinalSize;
@@ -2864,7 +2864,7 @@
// Emit the lock opcode prefix as needed.
if (Desc->TSFlags & X86II::LOCK) ++FinalSize;
- // Emit segment overrid opcode prefix as needed.
+ // Emit segment override opcode prefix as needed.
switch (Desc->TSFlags & X86II::SegOvrMask) {
case X86II::FS:
case X86II::GS:
@@ -2922,7 +2922,7 @@
case X86II::T8: // 0F 38
++FinalSize;
break;
- case X86II::TA: // 0F 3A
+ case X86II::TA: // 0F 3A
++FinalSize;
break;
}
@@ -2932,6 +2932,9 @@
unsigned CurOp = 0;
if (NumOps > 1 && Desc->getOperandConstraint(1, TOI::TIED_TO) != -1)
CurOp++;
+ else if (NumOps > 2 && Desc->getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
+ // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
+ --NumOps;
switch (Desc->TSFlags & X86II::FormMask) {
default: assert(0 && "Unknown FormMask value in X86 MachineCodeEmitter!");
@@ -3022,7 +3025,7 @@
case X86II::MRMDestMem: {
++FinalSize;
FinalSize += getMemModRMByteSize(MI, CurOp, IsPIC, Is64BitMode);
- CurOp += 5;
+ CurOp += X86AddrNumOperands + 1;
if (CurOp != NumOps) {
++CurOp;
FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
@@ -3041,10 +3044,16 @@
break;
case X86II::MRMSrcMem: {
+ int AddrOperands;
+ if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
+ Opcode == X86::LEA16r || Opcode == X86::LEA32r)
+ AddrOperands = X86AddrNumOperands - 1; // No segment register
+ else
+ AddrOperands = X86AddrNumOperands;
++FinalSize;
FinalSize += getMemModRMByteSize(MI, CurOp+1, IsPIC, Is64BitMode);
- CurOp += 5;
+ CurOp += AddrOperands + 1;
if (CurOp != NumOps) {
++CurOp;
FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
@@ -3057,8 +3066,18 @@
case X86II::MRM4r: case X86II::MRM5r:
case X86II::MRM6r: case X86II::MRM7r:
++FinalSize;
- ++CurOp;
- FinalSize += sizeRegModRMByte();
+ if (Desc->getOpcode() == X86::LFENCE ||
+ Desc->getOpcode() == X86::MFENCE) {
+ // Special handling of lfence and mfence.
+ FinalSize += sizeRegModRMByte();
+ } else if (Desc->getOpcode() == X86::MONITOR ||
+ Desc->getOpcode() == X86::MWAIT) {
+ // Special handling of monitor and mwait.
+ FinalSize += sizeRegModRMByte() + 1; // +1 for the opcode.
+ } else {
+ ++CurOp;
+ FinalSize += sizeRegModRMByte();
+ }
if (CurOp != NumOps) {
const MachineOperand &MO1 = MI.getOperand(CurOp++);
@@ -3088,7 +3107,7 @@
++FinalSize;
FinalSize += getMemModRMByteSize(MI, CurOp, IsPIC, Is64BitMode);
- CurOp += 4;
+ CurOp += X86AddrNumOperands;
if (CurOp != NumOps) {
const MachineOperand &MO = MI.getOperand(CurOp++);
Modified: llvm/branches/Apple/Bender/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Bender/lib/Target/X86/X86InstrSSE.td?rev=72877&r1=72876&r2=72877&view=diff
==============================================================================
--- llvm/branches/Apple/Bender/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/branches/Apple/Bender/lib/Target/X86/X86InstrSSE.td Thu Jun 4 13:37:26 2009
@@ -2502,9 +2502,9 @@
}
// Thread synchronization
-def MONITOR : I<0xC8, RawFrm, (outs), (ins), "monitor",
+def MONITOR : I<0x01, MRM1r, (outs), (ins), "monitor",
[(int_x86_sse3_monitor EAX, ECX, EDX)]>,TB, Requires<[HasSSE3]>;
-def MWAIT : I<0xC9, RawFrm, (outs), (ins), "mwait",
+def MWAIT : I<0x01, MRM1r, (outs), (ins), "mwait",
[(int_x86_sse3_mwait ECX, EAX)]>, TB, Requires<[HasSSE3]>;
// vector_shuffle v1, <undef> <1, 1, 3, 3>
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