[llvm-branch-commits] [llvm-branch] r91372 - /llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMISelLowering.cpp

[Jim Grosbach]

Author: grosbach
Date: Mon Dec 14 18:16:24 2009
New Revision: 91372

URL: http://llvm.org/viewvc/llvm-project?rev=91372&view=rev
Log:
merge 91371

Modified:
    llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMISelLowering.cpp

Modified: llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMISelLowering.cpp?rev=91372&r1=91371&r2=91372&view=diff

==============================================================================
--- llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMISelLowering.cpp Mon Dec 14 18:16:24 2009
@@ -3182,9 +3182,15 @@
   //   fallthrough --> exitMBB
   BB = loopMBB;
   AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
-  if (BinOpcode)
-    AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
-                   addReg(dest).addReg(incr)).addReg(0);
+  if (BinOpcode) {
+    // operand order needs to go the other way for NAND
+    if (BinOpcode == ARM::BICrr || BinOpcode == ARM::t2BICrr)
+      AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
+                     addReg(incr).addReg(dest)).addReg(0);
+    else
+      AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
+                     addReg(dest).addReg(incr)).addReg(0);
+  }
 
   AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2)
                  .addReg(ptr));