[llvm-branch-commits] [llvm-branch] r91306 - in /llvm/branches/Apple/Zoidberg/lib/Target/ARM: ARMInstrFormats.td ARMInstrInfo.td

[Jim Grosbach]

Author: grosbach
Date: Mon Dec 14 12:31:48 2009
New Revision: 91306

URL: http://llvm.org/viewvc/llvm-project?rev=91306&view=rev
Log:
merge 91305

Modified:
    llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMInstrFormats.td
    llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMInstrInfo.td

Modified: llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMInstrFormats.td?rev=91306&r1=91305&r2=91306&view=diff

==============================================================================
--- llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMInstrFormats.td Mon Dec 14 12:31:48 2009
@@ -201,6 +201,19 @@
   let Pattern = pattern;
   list<Predicate> Predicates = [IsARM];
 }
+// A few are not predicable
+class InoP<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
+        IndexMode im, Format f, InstrItinClass itin, 
+        string opc, string asm, string cstr,
+        list<dag> pattern>
+  : InstARM<am, sz, im, f, GenericDomain, cstr, itin> {
+  let OutOperandList = oops;
+  let InOperandList = iops;
+  let AsmString   = !strconcat(opc, asm);
+  let Pattern = pattern;
+  let isPredicable = 0;
+  list<Predicate> Predicates = [IsARM];
+}
 
 // Same as I except it can optionally modify CPSR. Note it's modeled as
 // an input operand since by default it's a zero register. It will
@@ -241,6 +254,10 @@
           string asm, list<dag> pattern>
   : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
        asm, "", pattern>;
+class AInoP<dag oops, dag iops, Format f, InstrItinClass itin,
+         string opc, string asm, list<dag> pattern>
+  : InoP<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, itin,
+      opc, asm, "", pattern>;
 
 // Ctrl flow instructions
 class ABI<bits<4> opcod, dag oops, dag iops, InstrItinClass itin,

Modified: llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMInstrInfo.td?rev=91306&r1=91305&r2=91306&view=diff

==============================================================================
--- llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMInstrInfo.td Mon Dec 14 12:31:48 2009
@@ -1570,8 +1570,8 @@
 //
 
 // memory barriers protect the atomic sequences
-let isPredicable = 0, hasSideEffects = 1 in {
-def Int_MemBarrierV7 : AI<(outs), (ins),
+let hasSideEffects = 1 in {
+def Int_MemBarrierV7 : AInoP<(outs), (ins),
                         Pseudo, NoItinerary,
                         "dmb", "",
                         [(ARMMemBarrier)]>,
@@ -1581,7 +1581,7 @@
   let Inst{3-0} = 0b1111;
 }
 
-def Int_SyncBarrierV7 : AI<(outs), (ins),
+def Int_SyncBarrierV7 : AInoP<(outs), (ins),
                         Pseudo, NoItinerary,
                         "dsb", "",
                         [(ARMSyncBarrier)]>,