[llvm-branch-commits] [llvm-branch] r91054 - /llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMInstrInfo.td

[Jim Grosbach]

Author: grosbach
Date: Thu Dec 10 12:36:13 2009
New Revision: 91054

URL: http://llvm.org/viewvc/llvm-project?rev=91054&view=rev
Log:
merge 91053

Modified:
    llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMInstrInfo.td

Modified: llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMInstrInfo.td?rev=91054&r1=91053&r2=91054&view=diff

==============================================================================
--- llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMInstrInfo.td Thu Dec 10 12:36:13 2009
@@ -1570,18 +1570,26 @@
 //
 
 // memory barriers protect the atomic sequences
-let isBarrier = 1 in {
+let isBarrier = 1, isPredicable = 0 in {
 def Int_MemBarrierV7 : AI<(outs), (ins),
                         Pseudo, NoItinerary,
                         "dmb", "",
                         [(ARMMemBarrier)]>,
-                        Requires<[HasV7]>;
+                        Requires<[HasV7]> {
+  let Inst{31-4} = 0xf57ff05;
+  // FIXME: add support for options other than a full system DMB
+  let Inst{3-0} = 0b1111;
+}
 
 def Int_SyncBarrierV7 : AI<(outs), (ins),
                         Pseudo, NoItinerary,
                         "dsb", "",
                         [(ARMSyncBarrier)]>,
-                        Requires<[HasV7]>;
+                        Requires<[HasV7]> {
+  let Inst{31-4} = 0xf57ff04;
+  // FIXME: add support for options other than a full system DSB
+  let Inst{3-0} = 0b1111;
+}
 }
 
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