[llvm-branch-commits] [llvm-branch] r90351 - in /llvm/branches/Apple/Zoidberg: include/llvm/CodeGen/SelectionDAG.h lib/Analysis/ValueTracking.cpp lib/CodeGen/SelectionDAG/LegalizeTypes.cpp lib/CodeGen/SelectionDAG/LegalizeTypes.h lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp lib/CodeGen/SelectionDAG/SelectionDAG.cpp lib/Target/X86/X86ISelLowering.cpp test/Transforms/InstCombine/sext-misc.ll test/Transforms/InstCombine/sext.ll
Bill Wendling
isanbard at gmail.com
Wed Dec 2 13:52:36 PST 2009
Author: void
Date: Wed Dec 2 15:52:35 2009
New Revision: 90351
URL: http://llvm.org/viewvc/llvm-project?rev=90351&view=rev
Log:
$ svn merge -c 90108 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r90108 into '.':
U include/llvm/CodeGen/SelectionDAG.h
U lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
U lib/CodeGen/SelectionDAG/SelectionDAG.cpp
U lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
U lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
U lib/CodeGen/SelectionDAG/LegalizeTypes.h
U lib/Target/X86/X86ISelLowering.cpp
$ svn merge -c 90290 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r90290 into '.':
A test/Transforms/InstCombine/sext-2.ll
U lib/Analysis/ValueTracking.cpp
$ svn merge -c 90291 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r90291 into '.':
U test/Transforms/InstCombine/sext-misc.ll
$ svn merge -c 90292 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r90292 into '.':
A test/Transforms/InstCombine/sext.ll
D test/Transforms/InstCombine/sext-misc.ll
$ svn merge -c 90293 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r90293 into '.':
U test/Transforms/InstCombine/sext.ll
D test/Transforms/InstCombine/sext-2.ll
Added:
llvm/branches/Apple/Zoidberg/test/Transforms/InstCombine/sext.ll
- copied, changed from r90292, llvm/trunk/test/Transforms/InstCombine/sext.ll
Removed:
llvm/branches/Apple/Zoidberg/test/Transforms/InstCombine/sext-misc.ll
Modified:
llvm/branches/Apple/Zoidberg/include/llvm/CodeGen/SelectionDAG.h
llvm/branches/Apple/Zoidberg/lib/Analysis/ValueTracking.cpp
llvm/branches/Apple/Zoidberg/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
llvm/branches/Apple/Zoidberg/lib/CodeGen/SelectionDAG/LegalizeTypes.h
llvm/branches/Apple/Zoidberg/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
llvm/branches/Apple/Zoidberg/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
llvm/branches/Apple/Zoidberg/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/branches/Apple/Zoidberg/lib/Target/X86/X86ISelLowering.cpp
Modified: llvm/branches/Apple/Zoidberg/include/llvm/CodeGen/SelectionDAG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Zoidberg/include/llvm/CodeGen/SelectionDAG.h?rev=90351&r1=90350&r2=90351&view=diff
==============================================================================
--- llvm/branches/Apple/Zoidberg/include/llvm/CodeGen/SelectionDAG.h (original)
+++ llvm/branches/Apple/Zoidberg/include/llvm/CodeGen/SelectionDAG.h Wed Dec 2 15:52:35 2009
@@ -882,6 +882,14 @@
/// element of the result of the vector shuffle.
SDValue getShuffleScalarElt(const ShuffleVectorSDNode *N, unsigned Idx);
+ /// UnrollVectorOp - Utility function used by legalize and lowering to
+ /// "unroll" a vector operation by splitting out the scalars and operating
+ /// on each element individually. If the ResNE is 0, fully unroll the vector
+ /// op. If ResNE is less than the width of the vector op, unroll up to ResNE.
+ /// If the ResNE is greater than the width of the vector op, unroll the
+ /// vector op and fill the end of the resulting vector with UNDEFS.
+ SDValue UnrollVectorOp(SDNode *N, unsigned ResNE = 0);
+
private:
bool RemoveNodeFromCSEMaps(SDNode *N);
void AddModifiedNodeToCSEMaps(SDNode *N, DAGUpdateListener *UpdateListener);
Modified: llvm/branches/Apple/Zoidberg/lib/Analysis/ValueTracking.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Zoidberg/lib/Analysis/ValueTracking.cpp?rev=90351&r1=90350&r2=90351&view=diff
==============================================================================
--- llvm/branches/Apple/Zoidberg/lib/Analysis/ValueTracking.cpp (original)
+++ llvm/branches/Apple/Zoidberg/lib/Analysis/ValueTracking.cpp Wed Dec 2 15:52:35 2009
@@ -659,7 +659,7 @@
switch (Operator::getOpcode(V)) {
default: break;
case Instruction::SExt:
- Tmp = TyBits-cast<IntegerType>(U->getOperand(0)->getType())->getBitWidth();
+ Tmp = TyBits - U->getOperand(0)->getType()->getScalarSizeInBits();
return ComputeNumSignBits(U->getOperand(0), TD, Depth+1) + Tmp;
case Instruction::AShr:
Modified: llvm/branches/Apple/Zoidberg/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Zoidberg/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp?rev=90351&r1=90350&r2=90351&view=diff
==============================================================================
--- llvm/branches/Apple/Zoidberg/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp (original)
+++ llvm/branches/Apple/Zoidberg/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp Wed Dec 2 15:52:35 2009
@@ -918,6 +918,29 @@
return true;
}
+
+/// CustomWidenLowerNode - Widen the node's results with custom code provided
+/// by the target and return "true", or do nothing and return "false".
+bool DAGTypeLegalizer::CustomWidenLowerNode(SDNode *N, EVT VT) {
+ // See if the target wants to custom lower this node.
+ if (TLI.getOperationAction(N->getOpcode(), VT) != TargetLowering::Custom)
+ return false;
+
+ SmallVector<SDValue, 8> Results;
+ TLI.ReplaceNodeResults(N, Results, DAG);
+
+ if (Results.empty())
+ // The target didn't want to custom widen lower its result after all.
+ return false;
+
+ // Update the widening map.
+ assert(Results.size() == N->getNumValues() &&
+ "Custom lowering returned the wrong number of results!");
+ for (unsigned i = 0, e = Results.size(); i != e; ++i)
+ SetWidenedVector(SDValue(N, i), Results[i]);
+ return true;
+}
+
/// GetSplitDestVTs - Compute the VTs needed for the low/hi parts of a type
/// which is split into two not necessarily identical pieces.
void DAGTypeLegalizer::GetSplitDestVTs(EVT InVT, EVT &LoVT, EVT &HiVT) {
Modified: llvm/branches/Apple/Zoidberg/lib/CodeGen/SelectionDAG/LegalizeTypes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Zoidberg/lib/CodeGen/SelectionDAG/LegalizeTypes.h?rev=90351&r1=90350&r2=90351&view=diff
==============================================================================
--- llvm/branches/Apple/Zoidberg/lib/CodeGen/SelectionDAG/LegalizeTypes.h (original)
+++ llvm/branches/Apple/Zoidberg/lib/CodeGen/SelectionDAG/LegalizeTypes.h Wed Dec 2 15:52:35 2009
@@ -188,6 +188,7 @@
SDValue BitConvertVectorToIntegerVector(SDValue Op);
SDValue CreateStackStoreLoad(SDValue Op, EVT DestVT);
bool CustomLowerNode(SDNode *N, EVT VT, bool LegalizeResult);
+ bool CustomWidenLowerNode(SDNode *N, EVT VT);
SDValue GetVectorElementPointer(SDValue VecPtr, EVT EltVT, SDValue Index);
SDValue JoinIntegers(SDValue Lo, SDValue Hi);
SDValue LibCallify(RTLIB::Libcall LC, SDNode *N, bool isSigned);
Modified: llvm/branches/Apple/Zoidberg/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Zoidberg/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp?rev=90351&r1=90350&r2=90351&view=diff
==============================================================================
--- llvm/branches/Apple/Zoidberg/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp (original)
+++ llvm/branches/Apple/Zoidberg/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp Wed Dec 2 15:52:35 2009
@@ -54,9 +54,6 @@
SDValue LegalizeOp(SDValue Op);
// Assuming the node is legal, "legalize" the results
SDValue TranslateLegalizeResults(SDValue Op, SDValue Result);
- // Implements unrolling a generic vector operation, i.e. turning it into
- // scalar operations.
- SDValue UnrollVectorOp(SDValue Op);
// Implements unrolling a VSETCC.
SDValue UnrollVSETCC(SDValue Op);
// Implements expansion for FNEG; falls back to UnrollVectorOp if FSUB
@@ -211,7 +208,7 @@
else if (Node->getOpcode() == ISD::VSETCC)
Result = UnrollVSETCC(Op);
else
- Result = UnrollVectorOp(Op);
+ Result = DAG.UnrollVectorOp(Op.getNode());
break;
}
@@ -256,7 +253,7 @@
return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(),
Zero, Op.getOperand(0));
}
- return UnrollVectorOp(Op);
+ return DAG.UnrollVectorOp(Op.getNode());
}
SDValue VectorLegalizer::UnrollVSETCC(SDValue Op) {
@@ -282,56 +279,6 @@
return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], NumElems);
}
-/// UnrollVectorOp - We know that the given vector has a legal type, however
-/// the operation it performs is not legal, and the target has requested that
-/// the operation be expanded. "Unroll" the vector, splitting out the scalars
-/// and operating on each element individually.
-SDValue VectorLegalizer::UnrollVectorOp(SDValue Op) {
- EVT VT = Op.getValueType();
- assert(Op.getNode()->getNumValues() == 1 &&
- "Can't unroll a vector with multiple results!");
- unsigned NE = VT.getVectorNumElements();
- EVT EltVT = VT.getVectorElementType();
- DebugLoc dl = Op.getDebugLoc();
-
- SmallVector<SDValue, 8> Scalars;
- SmallVector<SDValue, 4> Operands(Op.getNumOperands());
- for (unsigned i = 0; i != NE; ++i) {
- for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
- SDValue Operand = Op.getOperand(j);
- EVT OperandVT = Operand.getValueType();
- if (OperandVT.isVector()) {
- // A vector operand; extract a single element.
- EVT OperandEltVT = OperandVT.getVectorElementType();
- Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
- OperandEltVT,
- Operand,
- DAG.getConstant(i, MVT::i32));
- } else {
- // A scalar operand; just use it as is.
- Operands[j] = Operand;
- }
- }
-
- switch (Op.getOpcode()) {
- default:
- Scalars.push_back(DAG.getNode(Op.getOpcode(), dl, EltVT,
- &Operands[0], Operands.size()));
- break;
- case ISD::SHL:
- case ISD::SRA:
- case ISD::SRL:
- case ISD::ROTL:
- case ISD::ROTR:
- Scalars.push_back(DAG.getNode(Op.getOpcode(), dl, EltVT, Operands[0],
- DAG.getShiftAmountOperand(Operands[1])));
- break;
- }
- }
-
- return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Scalars[0], Scalars.size());
-}
-
}
bool SelectionDAG::LegalizeVectors() {
Modified: llvm/branches/Apple/Zoidberg/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Zoidberg/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=90351&r1=90350&r2=90351&view=diff
==============================================================================
--- llvm/branches/Apple/Zoidberg/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (original)
+++ llvm/branches/Apple/Zoidberg/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Wed Dec 2 15:52:35 2009
@@ -1118,8 +1118,12 @@
DEBUG(errs() << "Widen node result " << ResNo << ": ";
N->dump(&DAG);
errs() << "\n");
- SDValue Res = SDValue();
+ // See if the target wants to custom widen this node.
+ if (CustomWidenLowerNode(N, N->getValueType(ResNo)))
+ return;
+
+ SDValue Res = SDValue();
switch (N->getOpcode()) {
default:
#ifndef NDEBUG
Modified: llvm/branches/Apple/Zoidberg/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Zoidberg/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=90351&r1=90350&r2=90351&view=diff
==============================================================================
--- llvm/branches/Apple/Zoidberg/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/branches/Apple/Zoidberg/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed Dec 2 15:52:35 2009
@@ -5807,6 +5807,66 @@
N->dump(G);
}
+SDValue SelectionDAG::UnrollVectorOp(SDNode *N, unsigned ResNE) {
+ assert(N->getNumValues() == 1 &&
+ "Can't unroll a vector with multiple results!");
+
+ EVT VT = N->getValueType(0);
+ unsigned NE = VT.getVectorNumElements();
+ EVT EltVT = VT.getVectorElementType();
+ DebugLoc dl = N->getDebugLoc();
+
+ SmallVector<SDValue, 8> Scalars;
+ SmallVector<SDValue, 4> Operands(N->getNumOperands());
+
+ // If ResNE is 0, fully unroll the vector op.
+ if (ResNE == 0)
+ ResNE = NE;
+ else if (NE > ResNE)
+ NE = ResNE;
+
+ unsigned i;
+ for (i= 0; i != NE; ++i) {
+ for (unsigned j = 0; j != N->getNumOperands(); ++j) {
+ SDValue Operand = N->getOperand(j);
+ EVT OperandVT = Operand.getValueType();
+ if (OperandVT.isVector()) {
+ // A vector operand; extract a single element.
+ EVT OperandEltVT = OperandVT.getVectorElementType();
+ Operands[j] = getNode(ISD::EXTRACT_VECTOR_ELT, dl,
+ OperandEltVT,
+ Operand,
+ getConstant(i, MVT::i32));
+ } else {
+ // A scalar operand; just use it as is.
+ Operands[j] = Operand;
+ }
+ }
+
+ switch (N->getOpcode()) {
+ default:
+ Scalars.push_back(getNode(N->getOpcode(), dl, EltVT,
+ &Operands[0], Operands.size()));
+ break;
+ case ISD::SHL:
+ case ISD::SRA:
+ case ISD::SRL:
+ case ISD::ROTL:
+ case ISD::ROTR:
+ Scalars.push_back(getNode(N->getOpcode(), dl, EltVT, Operands[0],
+ getShiftAmountOperand(Operands[1])));
+ break;
+ }
+ }
+
+ for (; i < ResNE; ++i)
+ Scalars.push_back(getUNDEF(EltVT));
+
+ return getNode(ISD::BUILD_VECTOR, dl,
+ EVT::getVectorVT(*getContext(), EltVT, ResNE),
+ &Scalars[0], Scalars.size());
+}
+
void SelectionDAG::dump() const {
errs() << "SelectionDAG has " << AllNodes.size() << " nodes:";
@@ -5962,3 +6022,4 @@
return false;
return true;
}
+
Modified: llvm/branches/Apple/Zoidberg/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Zoidberg/lib/Target/X86/X86ISelLowering.cpp?rev=90351&r1=90350&r2=90351&view=diff
==============================================================================
--- llvm/branches/Apple/Zoidberg/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/branches/Apple/Zoidberg/lib/Target/X86/X86ISelLowering.cpp Wed Dec 2 15:52:35 2009
@@ -975,6 +975,19 @@
computeRegisterProperties();
+ // Divide and reminder operations have no vector equivalent and can
+ // trap. Do a custom widening for these operations in which we never
+ // generate more divides/remainder than the original vector width.
+ for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
+ VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
+ if (!isTypeLegal((MVT::SimpleValueType)VT)) {
+ setOperationAction(ISD::SDIV, (MVT::SimpleValueType) VT, Custom);
+ setOperationAction(ISD::UDIV, (MVT::SimpleValueType) VT, Custom);
+ setOperationAction(ISD::SREM, (MVT::SimpleValueType) VT, Custom);
+ setOperationAction(ISD::UREM, (MVT::SimpleValueType) VT, Custom);
+ }
+ }
+
// FIXME: These should be based on subtarget info. Plus, the values should
// be smaller when we are in optimizing for size mode.
maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores
@@ -7170,6 +7183,14 @@
Results.push_back(edx.getValue(1));
return;
}
+ case ISD::SDIV:
+ case ISD::UDIV:
+ case ISD::SREM:
+ case ISD::UREM: {
+ EVT WidenVT = getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
+ Results.push_back(DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements()));
+ return;
+ }
case ISD::ATOMIC_CMP_SWAP: {
EVT T = N->getValueType(0);
assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap");
Removed: llvm/branches/Apple/Zoidberg/test/Transforms/InstCombine/sext-misc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Zoidberg/test/Transforms/InstCombine/sext-misc.ll?rev=90350&view=auto
==============================================================================
--- llvm/branches/Apple/Zoidberg/test/Transforms/InstCombine/sext-misc.ll (original)
+++ llvm/branches/Apple/Zoidberg/test/Transforms/InstCombine/sext-misc.ll (removed)
@@ -1,77 +0,0 @@
-; RUN: opt < %s -instcombine -S | not grep sext
-
-target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
-
-declare i32 @llvm.ctpop.i32(i32)
-declare i32 @llvm.ctlz.i32(i32)
-declare i32 @llvm.cttz.i32(i32)
-
-define i64 @foo(i32 %x) {
- %t = call i32 @llvm.ctpop.i32(i32 %x)
- %s = sext i32 %t to i64
- ret i64 %s
-}
-define i64 @boo(i32 %x) {
- %t = call i32 @llvm.ctlz.i32(i32 %x)
- %s = sext i32 %t to i64
- ret i64 %s
-}
-define i64 @zoo(i32 %x) {
- %t = call i32 @llvm.cttz.i32(i32 %x)
- %s = sext i32 %t to i64
- ret i64 %s
-}
-define i64 @coo(i32 %x) {
- %t = udiv i32 %x, 3
- %s = sext i32 %t to i64
- ret i64 %s
-}
-define i64 @moo(i32 %x) {
- %t = urem i32 %x, 30000
- %s = sext i32 %t to i64
- ret i64 %s
-}
-define i64 @yoo(i32 %x) {
- %u = lshr i32 %x, 3
- %t = mul i32 %u, 3
- %s = sext i32 %t to i64
- ret i64 %s
-}
-define i64 @voo(i32 %x) {
- %t = and i32 %x, 511
- %u = sub i32 20000, %t
- %s = sext i32 %u to i64
- ret i64 %s
-}
-define i32 @woo(i8 %a, i32 %f, i1 %p, i32* %z) {
- %d = lshr i32 %f, 24
- %e = select i1 %p, i32 %d, i32 0
- %s = trunc i32 %e to i16
- %n = sext i16 %s to i32
- ret i32 %n
-}
-
-; rdar://6013816
-define i16 @test(i16 %t, i1 %cond) nounwind {
-entry:
- br i1 %cond, label %T, label %F
-T:
- %t2 = sext i16 %t to i32
- br label %F
-
-F:
- %V = phi i32 [%t2, %T], [42, %entry]
- %W = trunc i32 %V to i16
- ret i16 %W
-}
-
-; PR2638
-define i32 @test2(i32 %i) nounwind {
-entry:
- %tmp12 = trunc i32 %i to i8 ; <i8> [#uses=1]
- %tmp16 = shl i8 %tmp12, 6 ; <i8> [#uses=1]
- %a = ashr i8 %tmp16, 6 ; <i8> [#uses=1]
- %b = sext i8 %a to i32 ; <i32> [#uses=1]
- ret i32 %b
-}
-
Copied: llvm/branches/Apple/Zoidberg/test/Transforms/InstCombine/sext.ll (from r90292, llvm/trunk/test/Transforms/InstCombine/sext.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Zoidberg/test/Transforms/InstCombine/sext.ll?p2=llvm/branches/Apple/Zoidberg/test/Transforms/InstCombine/sext.ll&p1=llvm/trunk/test/Transforms/InstCombine/sext.ll&r1=90292&r2=90351&rev=90351&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/sext.ll (original)
+++ llvm/branches/Apple/Zoidberg/test/Transforms/InstCombine/sext.ll Wed Dec 2 15:52:35 2009
@@ -114,3 +114,15 @@
; CHECK-NEXT: ret i32
}
+define void @test11(<2 x i16> %srcA, <2 x i16> %srcB, <2 x i16>* %dst) {
+ %cmp = icmp eq <2 x i16> %srcB, %srcA
+ %sext = sext <2 x i1> %cmp to <2 x i16>
+ %tmask = ashr <2 x i16> %sext, <i16 15, i16 15>
+ store <2 x i16> %tmask, <2 x i16>* %dst
+ ret void
+; CHECK: @test11
+; CHECK-NEXT: icmp eq
+; CHECK-NEXT: sext <2 x i1>
+; CHECK-NEXT: store <2 x i16>
+; CHECK-NEXT: ret
+}
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