[llvm-branch-commits] [llvm-branch] r90248 - in /llvm/branches/Apple/Zoidberg/lib/Target/ARM: ARMBaseInstrInfo.cpp ARMInstrFormats.td ARMInstrThumb.td

[Jim Grosbach]

Author: grosbach
Date: Tue Dec  1 12:24:45 2009
New Revision: 90248

URL: http://llvm.org/viewvc/llvm-project?rev=90248&view=rev
Log:
merge 90246

Modified:
    llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMBaseInstrInfo.cpp
    llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMInstrFormats.td
    llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMInstrThumb.td

Modified: llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=90248&r1=90247&r2=90248&view=diff

==============================================================================
--- llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMBaseInstrInfo.cpp Tue Dec  1 12:24:45 2009
@@ -467,6 +467,8 @@
       return MI->getOperand(2).getImm();
     case ARM::Int_eh_sjlj_setjmp:
       return 24;
+    case ARM::tInt_eh_sjlj_setjmp:
+      return 22;
     case ARM::t2Int_eh_sjlj_setjmp:
       return 22;
     case ARM::BR_JTr:

Modified: llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMInstrFormats.td?rev=90248&r1=90247&r2=90248&view=diff

==============================================================================
--- llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMInstrFormats.td Tue Dec  1 12:24:45 2009
@@ -967,6 +967,17 @@
   list<Predicate> Predicates = [IsThumb2];
 }
 
+class ThumbXI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
+               InstrItinClass itin,
+               string asm, string cstr, list<dag> pattern>
+  : InstARM<am, sz, IndexModeNone, ThumbFrm, GenericDomain, cstr, itin> {
+  let OutOperandList = oops;
+  let InOperandList = iops;
+  let AsmString   = asm;
+  let Pattern = pattern;
+  list<Predicate> Predicates = [IsThumb1Only];
+}
+
 class T2I<dag oops, dag iops, InstrItinClass itin,
           string opc, string asm, list<dag> pattern>
   : Thumb2I<oops, iops, AddrModeNone, Size4Bytes, itin, opc, asm, "", pattern>;

Modified: llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMInstrThumb.td?rev=90248&r1=90247&r2=90248&view=diff

==============================================================================
--- llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/branches/Apple/Zoidberg/lib/Target/ARM/ARMInstrThumb.td Tue Dec  1 12:24:45 2009
@@ -669,6 +669,35 @@
                [(set R0, ARMthread_pointer)]>;
 }
 
+// SJLJ Exception handling intrinsics
+//   eh_sjlj_setjmp() is an instruction sequence to store the return
+//   address and save #0 in R0 for the non-longjmp case.
+//   Since by its nature we may be coming from some other function to get
+//   here, and we're using the stack frame for the containing function to
+//   save/restore registers, we can't keep anything live in regs across
+//   the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
+//   when we get here from a longjmp(). We force everthing out of registers
+//   except for our own input by listing the relevant registers in Defs. By
+//   doing so, we also cause the prologue/epilogue code to actively preserve
+//   all of the callee-saved resgisters, which is exactly what we want.
+let Defs =
+  [ R0,  R1,  R2,  R3,  R4,  R5,  R6,  R7, R12 ] in {
+  def tInt_eh_sjlj_setjmp : ThumbXI<(outs), (ins GPR:$src),
+                              AddrModeNone, SizeSpecial, NoItinerary,
+                              "mov\tr12, r1\t@ begin eh.setjmp\n"
+                              "\tmov\tr1, sp\n"
+                              "\tstr\tr1, [$src, #8]\n"
+                              "\tadr\tr1, 0f\n"
+                              "\tadds\tr1, #1\n"
+                              "\tstr\tr1, [$src, #4]\n"
+                              "\tmov\tr1, r12\n"
+                              "\tmovs\tr0, #0\n"
+                              "\tb\t1f\n"
+                              ".align 2\n"
+                              "0:\tmovs\tr0, #1\t@ end eh.setjmp\n"
+                              "1:", "",
+                              [(set R0, (ARMeh_sjlj_setjmp GPR:$src))]>;
+}
 //===----------------------------------------------------------------------===//
 // Non-Instruction Patterns
 //