[llvm-branch-commits] [llvm-branch] r70508 - in /llvm/branches/Apple/Dib/lib/Target/X86: X86FastISel.cpp X86Instr64bit.td X86InstrInfo.cpp X86InstrInfo.td X86RegisterInfo.td
Bill Wendling
isanbard at gmail.com
Thu Apr 30 13:16:17 PDT 2009
Author: void
Date: Thu Apr 30 15:16:17 2009
New Revision: 70508
URL: http://llvm.org/viewvc/llvm-project?rev=70508&view=rev
Log:
--- Merging r70210 into '.':
U lib/Target/X86/X86Instr64bit.td
U lib/Target/X86/X86InstrInfo.td
U lib/Target/X86/X86FastISel.cpp
U lib/Target/X86/X86InstrInfo.cpp
U lib/Target/X86/X86RegisterInfo.td
--- Merging r70211 into '.':
G lib/Target/X86/X86InstrInfo.td
G lib/Target/X86/X86InstrInfo.cpp
G lib/Target/X86/X86RegisterInfo.td
Skipped 'test/CodeGen/X86/2009-04-29-RegAllocAssert.ll'
--- Merging r70461 into '.':
G lib/Target/X86/X86InstrInfo.td
--- Merging r70466 into '.':
G lib/Target/X86/X86InstrInfo.td
Modified:
llvm/branches/Apple/Dib/lib/Target/X86/X86FastISel.cpp
llvm/branches/Apple/Dib/lib/Target/X86/X86Instr64bit.td
llvm/branches/Apple/Dib/lib/Target/X86/X86InstrInfo.cpp
llvm/branches/Apple/Dib/lib/Target/X86/X86InstrInfo.td
llvm/branches/Apple/Dib/lib/Target/X86/X86RegisterInfo.td
Modified: llvm/branches/Apple/Dib/lib/Target/X86/X86FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/X86/X86FastISel.cpp?rev=70508&r1=70507&r2=70508&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/X86/X86FastISel.cpp (original)
+++ llvm/branches/Apple/Dib/lib/Target/X86/X86FastISel.cpp Thu Apr 30 15:16:17 2009
@@ -996,10 +996,10 @@
// Unhandled operand. Halt "fast" selection and bail.
return false;
- // First issue a copy to GR16_ or GR32_.
+ // First issue a copy to GR16_ABCD or GR32_ABCD.
unsigned CopyOpc = (SrcVT == MVT::i16) ? X86::MOV16rr : X86::MOV32rr;
const TargetRegisterClass *CopyRC = (SrcVT == MVT::i16)
- ? X86::GR16_RegisterClass : X86::GR32_RegisterClass;
+ ? X86::GR16_ABCDRegisterClass : X86::GR32_ABCDRegisterClass;
unsigned CopyReg = createResultReg(CopyRC);
BuildMI(MBB, DL, TII.get(CopyOpc), CopyReg).addReg(InputReg);
Modified: llvm/branches/Apple/Dib/lib/Target/X86/X86Instr64bit.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/X86/X86Instr64bit.td?rev=70508&r1=70507&r2=70508&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/X86/X86Instr64bit.td (original)
+++ llvm/branches/Apple/Dib/lib/Target/X86/X86Instr64bit.td Thu Apr 30 15:16:17 2009
@@ -1588,18 +1588,18 @@
(SUBREG_TO_REG
(i64 0),
(MOVZX32_NOREXrr8
- (EXTRACT_SUBREG (COPY_TO_REGCLASS GR64:$src, GR64_),
+ (EXTRACT_SUBREG (COPY_TO_REGCLASS GR64:$src, GR64_ABCD),
x86_subreg_8bit_hi)),
x86_subreg_32bit)>;
def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
(MOVZX32_NOREXrr8
- (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_),
+ (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
x86_subreg_8bit_hi))>,
Requires<[In64BitMode]>;
def : Pat<(srl_su GR16:$src, (i8 8)),
(EXTRACT_SUBREG
(MOVZX32_NOREXrr8
- (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_),
+ (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
x86_subreg_8bit_hi)),
x86_subreg_16bit)>,
Requires<[In64BitMode]>;
@@ -1608,18 +1608,18 @@
def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst),
(MOV8mr_NOREX
addr:$dst,
- (EXTRACT_SUBREG (COPY_TO_REGCLASS GR64:$src, GR64_),
+ (EXTRACT_SUBREG (COPY_TO_REGCLASS GR64:$src, GR64_ABCD),
x86_subreg_8bit_hi))>;
def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst),
(MOV8mr_NOREX
addr:$dst,
- (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_),
+ (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
x86_subreg_8bit_hi))>,
Requires<[In64BitMode]>;
def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst),
(MOV8mr_NOREX
addr:$dst,
- (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_),
+ (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
x86_subreg_8bit_hi))>,
Requires<[In64BitMode]>;
Modified: llvm/branches/Apple/Dib/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/X86/X86InstrInfo.cpp?rev=70508&r1=70507&r2=70508&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/branches/Apple/Dib/lib/Target/X86/X86InstrInfo.cpp Thu Apr 30 15:16:17 2009
@@ -1645,7 +1645,7 @@
/// isHReg - Test if the given register is a physical h register.
static bool isHReg(unsigned Reg) {
- return Reg == X86::AH || Reg == X86::BH || Reg == X86::CH || Reg == X86::DH;
+ return X86::GR8_ABCD_HRegClass.contains(Reg);
}
bool X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
@@ -1674,21 +1674,26 @@
} else if (CommonRC == &X86::GR16RegClass) {
Opc = X86::MOV16rr;
} else if (CommonRC == &X86::GR8RegClass) {
- // Copying two or from a physical H register on x86-64 requires a NOREX
+ // Copying to or from a physical H register on x86-64 requires a NOREX
// move. Otherwise use a normal move.
if ((isHReg(DestReg) || isHReg(SrcReg)) &&
TM.getSubtarget<X86Subtarget>().is64Bit())
Opc = X86::MOV8rr_NOREX;
else
Opc = X86::MOV8rr;
- } else if (CommonRC == &X86::GR64_RegClass) {
+ } else if (CommonRC == &X86::GR64_ABCDRegClass) {
Opc = X86::MOV64rr;
- } else if (CommonRC == &X86::GR32_RegClass) {
+ } else if (CommonRC == &X86::GR32_ABCDRegClass) {
Opc = X86::MOV32rr;
- } else if (CommonRC == &X86::GR16_RegClass) {
+ } else if (CommonRC == &X86::GR16_ABCDRegClass) {
Opc = X86::MOV16rr;
- } else if (CommonRC == &X86::GR8_RegClass) {
+ } else if (CommonRC == &X86::GR8_ABCD_LRegClass) {
Opc = X86::MOV8rr;
+ } else if (CommonRC == &X86::GR8_ABCD_HRegClass) {
+ if (TM.getSubtarget<X86Subtarget>().is64Bit())
+ Opc = X86::MOV8rr_NOREX;
+ else
+ Opc = X86::MOV8rr;
} else if (CommonRC == &X86::GR64_NOREXRegClass) {
Opc = X86::MOV64rr;
} else if (CommonRC == &X86::GR32_NOREXRegClass) {
@@ -1791,8 +1796,10 @@
return false;
}
-static unsigned getStoreRegOpcode(const TargetRegisterClass *RC,
- bool isStackAligned) {
+static unsigned getStoreRegOpcode(unsigned SrcReg,
+ const TargetRegisterClass *RC,
+ bool isStackAligned,
+ TargetMachine &TM) {
unsigned Opc = 0;
if (RC == &X86::GR64RegClass) {
Opc = X86::MOV64mr;
@@ -1801,15 +1808,26 @@
} else if (RC == &X86::GR16RegClass) {
Opc = X86::MOV16mr;
} else if (RC == &X86::GR8RegClass) {
- Opc = X86::MOV8mr;
- } else if (RC == &X86::GR64_RegClass) {
+ // Copying to or from a physical H register on x86-64 requires a NOREX
+ // move. Otherwise use a normal move.
+ if (isHReg(SrcReg) &&
+ TM.getSubtarget<X86Subtarget>().is64Bit())
+ Opc = X86::MOV8mr_NOREX;
+ else
+ Opc = X86::MOV8mr;
+ } else if (RC == &X86::GR64_ABCDRegClass) {
Opc = X86::MOV64mr;
- } else if (RC == &X86::GR32_RegClass) {
+ } else if (RC == &X86::GR32_ABCDRegClass) {
Opc = X86::MOV32mr;
- } else if (RC == &X86::GR16_RegClass) {
+ } else if (RC == &X86::GR16_ABCDRegClass) {
Opc = X86::MOV16mr;
- } else if (RC == &X86::GR8_RegClass) {
+ } else if (RC == &X86::GR8_ABCD_LRegClass) {
Opc = X86::MOV8mr;
+ } else if (RC == &X86::GR8_ABCD_HRegClass) {
+ if (TM.getSubtarget<X86Subtarget>().is64Bit())
+ Opc = X86::MOV8mr_NOREX;
+ else
+ Opc = X86::MOV8mr;
} else if (RC == &X86::GR64_NOREXRegClass) {
Opc = X86::MOV64mr;
} else if (RC == &X86::GR32_NOREXRegClass) {
@@ -1848,7 +1866,7 @@
const MachineFunction &MF = *MBB.getParent();
bool isAligned = (RI.getStackAlignment() >= 16) ||
RI.needsStackRealignment(MF);
- unsigned Opc = getStoreRegOpcode(RC, isAligned);
+ unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
DebugLoc DL = DebugLoc::getUnknownLoc();
if (MI != MBB.end()) DL = MI->getDebugLoc();
addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
@@ -1862,7 +1880,7 @@
SmallVectorImpl<MachineInstr*> &NewMIs) const {
bool isAligned = (RI.getStackAlignment() >= 16) ||
RI.needsStackRealignment(MF);
- unsigned Opc = getStoreRegOpcode(RC, isAligned);
+ unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
DebugLoc DL = DebugLoc::getUnknownLoc();
MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
for (unsigned i = 0, e = Addr.size(); i != e; ++i)
@@ -1871,8 +1889,10 @@
NewMIs.push_back(MIB);
}
-static unsigned getLoadRegOpcode(const TargetRegisterClass *RC,
- bool isStackAligned) {
+static unsigned getLoadRegOpcode(unsigned DestReg,
+ const TargetRegisterClass *RC,
+ bool isStackAligned,
+ const TargetMachine &TM) {
unsigned Opc = 0;
if (RC == &X86::GR64RegClass) {
Opc = X86::MOV64rm;
@@ -1881,15 +1901,26 @@
} else if (RC == &X86::GR16RegClass) {
Opc = X86::MOV16rm;
} else if (RC == &X86::GR8RegClass) {
- Opc = X86::MOV8rm;
- } else if (RC == &X86::GR64_RegClass) {
+ // Copying to or from a physical H register on x86-64 requires a NOREX
+ // move. Otherwise use a normal move.
+ if (isHReg(DestReg) &&
+ TM.getSubtarget<X86Subtarget>().is64Bit())
+ Opc = X86::MOV8rm_NOREX;
+ else
+ Opc = X86::MOV8rm;
+ } else if (RC == &X86::GR64_ABCDRegClass) {
Opc = X86::MOV64rm;
- } else if (RC == &X86::GR32_RegClass) {
+ } else if (RC == &X86::GR32_ABCDRegClass) {
Opc = X86::MOV32rm;
- } else if (RC == &X86::GR16_RegClass) {
+ } else if (RC == &X86::GR16_ABCDRegClass) {
Opc = X86::MOV16rm;
- } else if (RC == &X86::GR8_RegClass) {
+ } else if (RC == &X86::GR8_ABCD_LRegClass) {
Opc = X86::MOV8rm;
+ } else if (RC == &X86::GR8_ABCD_HRegClass) {
+ if (TM.getSubtarget<X86Subtarget>().is64Bit())
+ Opc = X86::MOV8rm_NOREX;
+ else
+ Opc = X86::MOV8rm;
} else if (RC == &X86::GR64_NOREXRegClass) {
Opc = X86::MOV64rm;
} else if (RC == &X86::GR32_NOREXRegClass) {
@@ -1928,7 +1959,7 @@
const MachineFunction &MF = *MBB.getParent();
bool isAligned = (RI.getStackAlignment() >= 16) ||
RI.needsStackRealignment(MF);
- unsigned Opc = getLoadRegOpcode(RC, isAligned);
+ unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
DebugLoc DL = DebugLoc::getUnknownLoc();
if (MI != MBB.end()) DL = MI->getDebugLoc();
addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
@@ -1940,7 +1971,7 @@
SmallVectorImpl<MachineInstr*> &NewMIs) const {
bool isAligned = (RI.getStackAlignment() >= 16) ||
RI.needsStackRealignment(MF);
- unsigned Opc = getLoadRegOpcode(RC, isAligned);
+ unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
DebugLoc DL = DebugLoc::getUnknownLoc();
MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
for (unsigned i = 0, e = Addr.size(); i != e; ++i)
@@ -2455,9 +2486,8 @@
MVT VT = *RC->vt_begin();
bool isAligned = (RI.getStackAlignment() >= 16) ||
RI.needsStackRealignment(MF);
- Load = DAG.getTargetNode(getLoadRegOpcode(RC, isAligned), dl,
- VT, MVT::Other,
- &AddrOps[0], AddrOps.size());
+ Load = DAG.getTargetNode(getLoadRegOpcode(0, RC, isAligned, TM), dl,
+ VT, MVT::Other, &AddrOps[0], AddrOps.size());
NewNodes.push_back(Load);
}
@@ -2489,8 +2519,10 @@
AddrOps.push_back(Chain);
bool isAligned = (RI.getStackAlignment() >= 16) ||
RI.needsStackRealignment(MF);
- SDNode *Store = DAG.getTargetNode(getStoreRegOpcode(DstRC, isAligned), dl,
- MVT::Other, &AddrOps[0], AddrOps.size());
+ SDNode *Store = DAG.getTargetNode(getStoreRegOpcode(0, DstRC,
+ isAligned, TM),
+ dl, MVT::Other,
+ &AddrOps[0], AddrOps.size());
NewNodes.push_back(Store);
}
Modified: llvm/branches/Apple/Dib/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/X86/X86InstrInfo.td?rev=70508&r1=70507&r2=70508&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/branches/Apple/Dib/lib/Target/X86/X86InstrInfo.td Thu Apr 30 15:16:17 2009
@@ -783,16 +783,22 @@
"mov{l}\t{$src, $dst|$dst, $src}",
[(store GR32:$src, addr:$dst)]>;
-// Versions of MOV8rr and MOV8mr that use i8mem_NOREX and GR8_NOREX so that they
-// can be used for copying and storing h registers, which can't be encoded when
-// a REX prefix is present.
+// Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so
+// that they can be used for copying and storing h registers, which can't be
+// encoded when a REX prefix is present.
let neverHasSideEffects = 1 in
def MOV8rr_NOREX : I<0x88, MRMDestReg,
(outs GR8_NOREX:$dst), (ins GR8_NOREX:$src),
"mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
+let mayStore = 1 in
def MOV8mr_NOREX : I<0x88, MRMDestMem,
(outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src),
"mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
+let mayLoad = 1,
+ canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in
+def MOV8rm_NOREX : I<0x8A, MRMSrcMem,
+ (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src),
+ "mov{b}\t{$src, $dst|$dst, $src} # NOREX", []>;
//===----------------------------------------------------------------------===//
// Fixed-Register Multiplication and Division Instructions...
@@ -2932,6 +2938,7 @@
(outs GR32_NOREX:$dst), (ins GR8:$src),
"movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
[]>, TB;
+let mayLoad = 1 in
def MOVZX32_NOREXrm8 : I<0xB6, MRMSrcMem,
(outs GR32_NOREX:$dst), (ins i8mem:$src),
"movz{bl|x}\t{$src, $dst|$dst, $src} # NOREX",
@@ -3363,12 +3370,12 @@
(MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, x86_subreg_16bit))>;
// r & (2^8-1) ==> movz
def : Pat<(and GR32:$src1, 0xff),
- (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src1, GR32_),
+ (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src1, GR32_ABCD),
x86_subreg_8bit))>,
Requires<[In32BitMode]>;
// r & (2^8-1) ==> movz
def : Pat<(and GR16:$src1, 0xff),
- (MOVZX16rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src1, GR16_),
+ (MOVZX16rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src1, GR16_ABCD),
x86_subreg_8bit))>,
Requires<[In32BitMode]>;
@@ -3376,11 +3383,11 @@
def : Pat<(sext_inreg GR32:$src, i16),
(MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit))>;
def : Pat<(sext_inreg GR32:$src, i8),
- (MOVSX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_),
+ (MOVSX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
x86_subreg_8bit))>,
Requires<[In32BitMode]>;
def : Pat<(sext_inreg GR16:$src, i8),
- (MOVSX16rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_),
+ (MOVSX16rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
x86_subreg_8bit))>,
Requires<[In32BitMode]>;
@@ -3388,32 +3395,32 @@
def : Pat<(i16 (trunc GR32:$src)),
(EXTRACT_SUBREG GR32:$src, x86_subreg_16bit)>;
def : Pat<(i8 (trunc GR32:$src)),
- (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_),
+ (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
x86_subreg_8bit)>,
Requires<[In32BitMode]>;
def : Pat<(i8 (trunc GR16:$src)),
- (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_),
+ (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
x86_subreg_8bit)>,
Requires<[In32BitMode]>;
// h-register tricks
def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
- (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_),
+ (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
x86_subreg_8bit_hi)>,
Requires<[In32BitMode]>;
def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
- (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_),
+ (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
x86_subreg_8bit_hi)>,
Requires<[In32BitMode]>;
def : Pat<(srl_su GR16:$src, (i8 8)),
(EXTRACT_SUBREG
(MOVZX32rr8
- (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_),
+ (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
x86_subreg_8bit_hi)),
x86_subreg_16bit)>,
Requires<[In32BitMode]>;
def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
- (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_),
+ (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
x86_subreg_8bit_hi))>,
Requires<[In32BitMode]>;
Modified: llvm/branches/Apple/Dib/lib/Target/X86/X86RegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/X86/X86RegisterInfo.td?rev=70508&r1=70507&r2=70508&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/X86/X86RegisterInfo.td (original)
+++ llvm/branches/Apple/Dib/lib/Target/X86/X86RegisterInfo.td Thu Apr 30 15:16:17 2009
@@ -461,21 +461,24 @@
}
-// GR8_, GR16_, GR32_, GR64_ - Subclasses of GR8, GR16, GR32, and GR64
-// which contain just the "a" "b", "c", and "d" registers. On x86-32,
-// GR16_ and GR32_ are classes for registers that support 8-bit subreg
-// operations. On x86-64, GR16_, GR32_, and GR64_ are classes for registers
-// that support 8-bit h-register operations.
-def GR8_ : RegisterClass<"X86", [i8], 8, [AL, CL, DL, BL]> {
+// GR8_ABCD_L, GR8_ABCD_H, GR16_ABCD, GR32_ABCD, GR64_ABCD - Subclasses of
+// GR8, GR16, GR32, and GR64 which contain just the "a" "b", "c", and "d"
+// registers. On x86-32, GR16_ABCD and GR32_ABCD are classes for registers
+// that support 8-bit subreg operations. On x86-64, GR16_ABCD, GR32_ABCD,
+// and GR64_ABCD are classes for registers that support 8-bit h-register
+// operations.
+def GR8_ABCD_L : RegisterClass<"X86", [i8], 8, [AL, CL, DL, BL]> {
+}
+def GR8_ABCD_H : RegisterClass<"X86", [i8], 8, [AH, CH, DH, BH]> {
}
-def GR16_ : RegisterClass<"X86", [i16], 16, [AX, CX, DX, BX]> {
- let SubRegClassList = [GR8_, GR8_];
+def GR16_ABCD : RegisterClass<"X86", [i16], 16, [AX, CX, DX, BX]> {
+ let SubRegClassList = [GR8_ABCD_L, GR8_ABCD_H];
}
-def GR32_ : RegisterClass<"X86", [i32], 32, [EAX, ECX, EDX, EBX]> {
- let SubRegClassList = [GR8_, GR8_, GR16_];
+def GR32_ABCD : RegisterClass<"X86", [i32], 32, [EAX, ECX, EDX, EBX]> {
+ let SubRegClassList = [GR8_ABCD_L, GR8_ABCD_H, GR16_ABCD];
}
-def GR64_ : RegisterClass<"X86", [i64], 64, [RAX, RCX, RDX, RBX]> {
- let SubRegClassList = [GR8_, GR8_, GR16_, GR32_];
+def GR64_ABCD : RegisterClass<"X86", [i64], 64, [RAX, RCX, RDX, RBX]> {
+ let SubRegClassList = [GR8_ABCD_L, GR8_ABCD_H, GR16_ABCD, GR32_ABCD];
}
// GR8_NOREX, GR16_NOREX, GR32_NOREX, GR64_NOREX - Subclasses of
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