[llvm-branch-commits] [llvm-branch] r70435 - in /llvm/branches/Apple/Dib: lib/CodeGen/SelectionDAG/LegalizeDAG.cpp lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/vec_shuffle-22.ll test/CodeGen/X86/vec_shuffle.ll
Bill Wendling
isanbard at gmail.com
Wed Apr 29 16:10:56 PDT 2009
Author: void
Date: Wed Apr 29 18:10:55 2009
New Revision: 70435
URL: http://llvm.org/viewvc/llvm-project?rev=70435&view=rev
Log:
--- Merging r70425 into '.':
U test/CodeGen/X86/vec_shuffle.ll
U test/CodeGen/X86/vec_shuffle-22.ll
U lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
U lib/Target/X86/X86InstrSSE.td
U lib/Target/X86/X86ISelLowering.cpp
Fix infinite recursion in the C++ code which handles movddup by making it
unnecessary.
Modified:
llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
llvm/branches/Apple/Dib/lib/Target/X86/X86ISelLowering.cpp
llvm/branches/Apple/Dib/lib/Target/X86/X86InstrSSE.td
llvm/branches/Apple/Dib/test/CodeGen/X86/vec_shuffle-22.ll
llvm/branches/Apple/Dib/test/CodeGen/X86/vec_shuffle.ll
Modified: llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=70435&r1=70434&r2=70435&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/branches/Apple/Dib/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed Apr 29 18:10:55 2009
@@ -3943,8 +3943,8 @@
MVT TVT = MVT::getVectorVT(EVT, NumElems);
if (TLI.isTypeLegal(TVT)) {
// Turn this into a bit convert of the vector input.
- Result = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0),
- LegalizeOp(Node->getOperand(0)));
+ Tmp1 = LegalizeOp(Node->getOperand(0));
+ Result = DAG.getNode(ISD::BIT_CONVERT, dl, Node->getValueType(0), Tmp1);
break;
} else if (NumElems == 1) {
// Turn this into a bit convert of the scalar input.
Modified: llvm/branches/Apple/Dib/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/X86/X86ISelLowering.cpp?rev=70435&r1=70434&r2=70435&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/branches/Apple/Dib/lib/Target/X86/X86ISelLowering.cpp Wed Apr 29 18:10:55 2009
@@ -2884,44 +2884,6 @@
return DAG.getNode(ISD::BIT_CONVERT, dl, VT, V1);
}
-/// isVectorLoad - Returns true if the node is a vector load, a scalar
-/// load that's promoted to vector, or a load bitcasted.
-static bool isVectorLoad(SDValue Op) {
- assert(Op.getValueType().isVector() && "Expected a vector type");
- if (Op.getOpcode() == ISD::SCALAR_TO_VECTOR ||
- Op.getOpcode() == ISD::BIT_CONVERT) {
- return isa<LoadSDNode>(Op.getOperand(0));
- }
- return isa<LoadSDNode>(Op);
-}
-
-
-/// CanonicalizeMovddup - Cannonicalize movddup shuffle to v2f64.
-///
-static SDValue CanonicalizeMovddup(ShuffleVectorSDNode *SV, SelectionDAG &DAG,
- bool HasSSE3) {
- // If we have sse3 and shuffle has more than one use or input is a load, then
- // use movddup. Otherwise, use movlhps.
- SDValue V1 = SV->getOperand(0);
-
- bool UseMovddup = HasSSE3 && (!SV->hasOneUse() || isVectorLoad(V1));
- MVT PVT = UseMovddup ? MVT::v2f64 : MVT::v4f32;
- MVT VT = SV->getValueType(0);
- if (VT == PVT)
- return SDValue(SV, 0);
-
- DebugLoc dl = SV->getDebugLoc();
- V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1);
- if (PVT.getVectorNumElements() == 2) {
- int Mask[2] = { 0, 0 };
- V1 = DAG.getVectorShuffle(PVT, dl, V1, DAG.getUNDEF(PVT), Mask);
- } else {
- int Mask[4] = { 0, 1, 0, 1 };
- V1 = DAG.getVectorShuffle(PVT, dl, V1, DAG.getUNDEF(PVT), Mask);
- }
- return DAG.getNode(ISD::BIT_CONVERT, dl, VT, V1);
-}
-
/// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified
/// vector of zero or undef vector. This produces a shuffle where the low
/// element of V2 is swizzled into the zero/undef vector, landing at element
@@ -3977,11 +3939,6 @@
if (isZeroShuffle(SVOp))
return getZeroVector(VT, Subtarget->hasSSE2(), DAG, dl);
- // Canonicalize movddup shuffles.
- if (V2IsUndef && Subtarget->hasSSE2() && VT.getSizeInBits() == 128 &&
- X86::isMOVDDUPMask(SVOp))
- return CanonicalizeMovddup(SVOp, DAG, Subtarget->hasSSE3());
-
// Promote splats to v4f32.
if (SVOp->isSplat()) {
if (isMMX || NumElems < 4)
Modified: llvm/branches/Apple/Dib/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/lib/Target/X86/X86InstrSSE.td?rev=70435&r1=70434&r2=70435&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/branches/Apple/Dib/lib/Target/X86/X86InstrSSE.td Wed Apr 29 18:10:55 2009
@@ -748,10 +748,12 @@
} // AddedComplexity
} // Constraints = "$src1 = $dst"
-let AddedComplexity = 20 in
+let AddedComplexity = 20 in {
def : Pat<(v4f32 (movddup VR128:$src, (undef))),
(MOVLHPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
-
+def : Pat<(v2i64 (movddup VR128:$src, (undef))),
+ (MOVLHPSrr VR128:$src, VR128:$src)>, Requires<[HasSSE1]>;
+}
@@ -2430,9 +2432,17 @@
def : Pat<(movddup (bc_v2f64 (v2i64 (scalar_to_vector (loadi64 addr:$src)))),
(undef)),
(MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
+
+let AddedComplexity = 5 in {
def : Pat<(movddup (memopv2f64 addr:$src), (undef)),
(MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
-
+def : Pat<(movddup (bc_v4f32 (memopv2f64 addr:$src)), (undef)),
+ (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
+def : Pat<(movddup (memopv2i64 addr:$src), (undef)),
+ (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
+def : Pat<(movddup (bc_v4i32 (memopv2i64 addr:$src)), (undef)),
+ (MOVDDUPrm addr:$src)>, Requires<[HasSSE3]>;
+}
// Arithmetic
let Constraints = "$src1 = $dst" in {
Modified: llvm/branches/Apple/Dib/test/CodeGen/X86/vec_shuffle-22.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/test/CodeGen/X86/vec_shuffle-22.ll?rev=70435&r1=70434&r2=70435&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/test/CodeGen/X86/vec_shuffle-22.ll (original)
+++ llvm/branches/Apple/Dib/test/CodeGen/X86/vec_shuffle-22.ll Wed Apr 29 18:10:55 2009
@@ -1,6 +1,9 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 | not grep shuf
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2,-sse3 | grep movlhps | count 2
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse3 | grep movddup | count 1
+; RUN: llvm-as < %s | llc -march=x86 -mcpu=pentium-m -o %t -f
+; RUN: grep movlhps %t | count 1
+; RUN: grep pshufd %t | count 1
+; RUN: llvm-as < %s | llc -march=x86 -mcpu=core2 -o %t -f
+; RUN: grep movlhps %t | count 1
+; RUN: grep movddup %t | count 1
define <4 x float> @t1(<4 x float> %a) nounwind {
entry:
Modified: llvm/branches/Apple/Dib/test/CodeGen/X86/vec_shuffle.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/branches/Apple/Dib/test/CodeGen/X86/vec_shuffle.ll?rev=70435&r1=70434&r2=70435&view=diff
==============================================================================
--- llvm/branches/Apple/Dib/test/CodeGen/X86/vec_shuffle.ll (original)
+++ llvm/branches/Apple/Dib/test/CodeGen/X86/vec_shuffle.ll Wed Apr 29 18:10:55 2009
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -o %t -f
+; RUN: llvm-as < %s | llc -march=x86 -mcpu=core2 -o %t -f
; RUN: grep shufp %t | count 1
; RUN: grep movupd %t | count 1
; RUN: grep pshufhw %t | count 1
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