[Lldb-commits] [lldb] [llvm] [lldb] [NOT FOR MERGE] Refactor RegisterContext from Process/Utility (PR #222964)
Minsoo Choo via lldb-commits
lldb-commits at lists.llvm.org
Thu Oct 15 18:51:53 PDT 2026
https://github.com/mchoo7 updated https://github.com/llvm/llvm-project/pull/222964
>From 43807d609a662950da132809acf27e5188381ac1 Mon Sep 17 00:00:00 2001
From: Minsoo Choo <minsoo at minsoo.io>
Date: Sun, 6 Sep 2026 00:58:17 -0400
Subject: [PATCH 1/5] [lldb] Rename common register metadata providers
---
.../LoongArch/EmulateInstructionLoongArch.cpp | 6 +-
.../RISCV/EmulateInstructionRISCV.cpp | 12 +-
.../AIX/NativeRegisterContextAIX_ppc64.cpp | 4 +-
.../RegisterContextFreeBSDKernelCore_arm.cpp | 2 +-
.../RegisterContextFreeBSDKernelCore_arm.h | 2 +-
...RegisterContextFreeBSDKernelCore_arm64.cpp | 2 +-
.../RegisterContextFreeBSDKernelCore_arm64.h | 2 +-
...gisterContextFreeBSDKernelCore_riscv64.cpp | 2 +-
...RegisterContextFreeBSDKernelCore_riscv64.h | 2 +-
.../ThreadFreeBSDKernelCore.cpp | 16 +-
.../NativeRegisterContextFreeBSD_arm.cpp | 28 ++--
.../NativeRegisterContextFreeBSD_arm.h | 4 +-
.../NativeRegisterContextFreeBSD_arm64.cpp | 28 ++--
.../NativeRegisterContextFreeBSD_arm64.h | 4 +-
.../Linux/NativeRegisterContextLinux_arm.cpp | 14 +-
.../Linux/NativeRegisterContextLinux_arm.h | 8 +-
.../NativeRegisterContextLinux_arm64.cpp | 38 ++---
.../Linux/NativeRegisterContextLinux_arm64.h | 10 +-
...NativeRegisterContextLinux_loongarch64.cpp | 18 +--
.../NativeRegisterContextLinux_loongarch64.h | 14 +-
.../NativeRegisterContextLinux_ppc64le.cpp | 4 +-
.../NativeRegisterContextLinux_riscv64.cpp | 18 +--
.../NativeRegisterContextLinux_riscv64.h | 10 +-
.../Plugins/Process/Utility/CMakeLists.txt | 16 +-
.../Utility/RegisterContextPOSIX_arm.cpp | 6 +-
.../Utility/RegisterContextPOSIX_arm.h | 8 +-
.../Utility/RegisterContextPOSIX_arm64.cpp | 6 +-
.../Utility/RegisterContextPOSIX_arm64.h | 8 +-
.../RegisterContextPOSIX_loongarch64.cpp | 10 +-
.../RegisterContextPOSIX_loongarch64.h | 8 +-
.../Utility/RegisterContextPOSIX_riscv32.cpp | 6 +-
.../Utility/RegisterContextPOSIX_riscv32.h | 8 +-
.../Utility/RegisterContextPOSIX_riscv64.cpp | 4 +-
.../Utility/RegisterContextPOSIX_riscv64.h | 8 +-
... => RegisterInfoCommonDynamic_riscv32.cpp} | 27 ++--
....h => RegisterInfoCommonDynamic_riscv32.h} | 10 +-
...SIX_arm.cpp => RegisterInfoCommon_arm.cpp} | 50 +++----
...foPOSIX_arm.h => RegisterInfoCommon_arm.h} | 12 +-
...arm64.cpp => RegisterInfoCommon_arm64.cpp} | 140 +++++++++---------
...SIX_arm64.h => RegisterInfoCommon_arm64.h} | 10 +-
...cpp => RegisterInfoCommon_loongarch64.cpp} | 54 +++----
...h64.h => RegisterInfoCommon_loongarch64.h} | 10 +-
...ppc64.cpp => RegisterInfoCommon_ppc64.cpp} | 14 +-
...SIX_ppc64.h => RegisterInfoCommon_ppc64.h} | 12 +-
...4le.cpp => RegisterInfoCommon_ppc64le.cpp} | 16 +-
...ppc64le.h => RegisterInfoCommon_ppc64le.h} | 10 +-
...v32.cpp => RegisterInfoCommon_riscv32.cpp} | 36 ++---
...riscv32.h => RegisterInfoCommon_riscv32.h} | 10 +-
...v64.cpp => RegisterInfoCommon_riscv64.cpp} | 34 ++---
...riscv64.h => RegisterInfoCommon_riscv64.h} | 10 +-
.../NativeRegisterContextWindows_arm.cpp | 4 +-
.../NativeRegisterContextWindows_arm64.cpp | 4 +-
.../NativeRegisterContextWindows_arm64.h | 2 +-
.../elf-core/RegisterContextPOSIXCore_arm.cpp | 2 +-
.../elf-core/RegisterContextPOSIXCore_arm.h | 2 +-
.../RegisterContextPOSIXCore_arm64.cpp | 28 ++--
.../elf-core/RegisterContextPOSIXCore_arm64.h | 2 +-
.../RegisterContextPOSIXCore_loongarch64.cpp | 4 +-
.../RegisterContextPOSIXCore_loongarch64.h | 4 +-
.../RegisterContextPOSIXCore_riscv32.cpp | 4 +-
.../RegisterContextPOSIXCore_riscv32.h | 6 +-
.../RegisterContextPOSIXCore_riscv64.cpp | 8 +-
.../RegisterContextPOSIXCore_riscv64.h | 4 +-
.../Process/elf-core/ThreadElfCore.cpp | 10 +-
.../Instruction/ARM64/TestAArch64Emulator.cpp | 4 +-
.../LoongArch/TestLoongArchEmulator.cpp | 6 +-
.../Instruction/RISCV/TestRISCVEmulator.cpp | 8 +-
.../Utility/RegisterInfoFreeBSDTest.cpp | 10 +-
.../source/Plugins/Process/Utility/BUILD.gn | 16 +-
69 files changed, 460 insertions(+), 459 deletions(-)
rename lldb/source/Plugins/Process/Utility/{RegisterInfoPOSIXDynamic_riscv32.cpp => RegisterInfoCommonDynamic_riscv32.cpp} (85%)
rename lldb/source/Plugins/Process/Utility/{RegisterInfoPOSIXDynamic_riscv32.h => RegisterInfoCommonDynamic_riscv32.h} (86%)
rename lldb/source/Plugins/Process/Utility/{RegisterInfoPOSIX_arm.cpp => RegisterInfoCommon_arm.cpp} (79%)
rename lldb/source/Plugins/Process/Utility/{RegisterInfoPOSIX_arm.h => RegisterInfoCommon_arm.h} (80%)
rename lldb/source/Plugins/Process/Utility/{RegisterInfoPOSIX_arm64.cpp => RegisterInfoCommon_arm64.cpp} (83%)
rename lldb/source/Plugins/Process/Utility/{RegisterInfoPOSIX_arm64.h => RegisterInfoCommon_arm64.h} (95%)
rename lldb/source/Plugins/Process/Utility/{RegisterInfoPOSIX_loongarch64.cpp => RegisterInfoCommon_loongarch64.cpp} (82%)
rename lldb/source/Plugins/Process/Utility/{RegisterInfoPOSIX_loongarch64.h => RegisterInfoCommon_loongarch64.h} (83%)
rename lldb/source/Plugins/Process/Utility/{RegisterInfoPOSIX_ppc64.cpp => RegisterInfoCommon_ppc64.cpp} (83%)
rename lldb/source/Plugins/Process/Utility/{RegisterInfoPOSIX_ppc64.h => RegisterInfoCommon_ppc64.h} (60%)
rename lldb/source/Plugins/Process/Utility/{RegisterInfoPOSIX_ppc64le.cpp => RegisterInfoCommon_ppc64le.cpp} (78%)
rename lldb/source/Plugins/Process/Utility/{RegisterInfoPOSIX_ppc64le.h => RegisterInfoCommon_ppc64le.h} (63%)
rename lldb/source/Plugins/Process/Utility/{RegisterInfoPOSIX_riscv32.cpp => RegisterInfoCommon_riscv32.cpp} (80%)
rename lldb/source/Plugins/Process/Utility/{RegisterInfoPOSIX_riscv32.h => RegisterInfoCommon_riscv32.h} (83%)
rename lldb/source/Plugins/Process/Utility/{RegisterInfoPOSIX_riscv64.cpp => RegisterInfoCommon_riscv64.cpp} (82%)
rename lldb/source/Plugins/Process/Utility/{RegisterInfoPOSIX_riscv64.h => RegisterInfoCommon_riscv64.h} (85%)
diff --git a/lldb/source/Plugins/Instruction/LoongArch/EmulateInstructionLoongArch.cpp b/lldb/source/Plugins/Instruction/LoongArch/EmulateInstructionLoongArch.cpp
index db32bf8a4dd51a..5090ddf0b6d1e9 100644
--- a/lldb/source/Plugins/Instruction/LoongArch/EmulateInstructionLoongArch.cpp
+++ b/lldb/source/Plugins/Instruction/LoongArch/EmulateInstructionLoongArch.cpp
@@ -11,7 +11,7 @@
#include "EmulateInstructionLoongArch.h"
#include "Plugins/Process/Utility/InstructionUtils.h"
-#include "Plugins/Process/Utility/RegisterInfoPOSIX_loongarch64.h"
+#include "Plugins/Process/Utility/RegisterInfoCommon_loongarch64.h"
#include "Plugins/Process/Utility/lldb-loongarch-register-enums.h"
#include "lldb/Core/Address.h"
#include "lldb/Core/PluginManager.h"
@@ -162,9 +162,9 @@ EmulateInstructionLoongArch::GetRegisterInfo(lldb::RegisterKind reg_kind,
}
const RegisterInfo *array =
- RegisterInfoPOSIX_loongarch64::GetRegisterInfoPtr(m_arch);
+ RegisterInfoCommon_loongarch64::GetRegisterInfoPtr(m_arch);
const uint32_t length =
- RegisterInfoPOSIX_loongarch64::GetRegisterInfoCount(m_arch);
+ RegisterInfoCommon_loongarch64::GetRegisterInfoCount(m_arch);
if (reg_index >= length || reg_kind != eRegisterKindLLDB)
return {};
diff --git a/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp b/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
index 1abedc050af639..ba6990ba235a7f 100644
--- a/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
+++ b/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
@@ -8,8 +8,8 @@
#include "EmulateInstructionRISCV.h"
#include "Plugins/Process/Utility/RegisterInfoInterface.h"
-#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv32.h"
-#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h"
+#include "Plugins/Process/Utility/RegisterInfoCommon_riscv32.h"
+#include "Plugins/Process/Utility/RegisterInfoCommon_riscv64.h"
#include "Plugins/Process/Utility/lldb-riscv-register-enums.h"
#include "RISCVCInstructions.h"
#include "RISCVInstructions.h"
@@ -1843,12 +1843,12 @@ EmulateInstructionRISCV::GetRegisterInfo(RegisterKind reg_kind,
std::unique_ptr<RegisterInfoInterface> reg_info;
switch (m_arch.GetTriple().getArch()) {
case llvm::Triple::riscv32:
- reg_info = std::make_unique<RegisterInfoPOSIX_riscv32>(
- m_arch, RegisterInfoPOSIX_riscv32::eRegsetMaskAll);
+ reg_info = std::make_unique<RegisterInfoCommon_riscv32>(
+ m_arch, RegisterInfoCommon_riscv32::eRegsetMaskAll);
break;
case llvm::Triple::riscv64:
- reg_info = std::make_unique<RegisterInfoPOSIX_riscv64>(
- m_arch, RegisterInfoPOSIX_riscv64::eRegsetMaskAll);
+ reg_info = std::make_unique<RegisterInfoCommon_riscv64>(
+ m_arch, RegisterInfoCommon_riscv64::eRegsetMaskAll);
break;
default:
assert(false && "unsupported triple");
diff --git a/lldb/source/Plugins/Process/AIX/NativeRegisterContextAIX_ppc64.cpp b/lldb/source/Plugins/Process/AIX/NativeRegisterContextAIX_ppc64.cpp
index 847a1b486a9980..0726e3ac779789 100644
--- a/lldb/source/Plugins/Process/AIX/NativeRegisterContextAIX_ppc64.cpp
+++ b/lldb/source/Plugins/Process/AIX/NativeRegisterContextAIX_ppc64.cpp
@@ -10,7 +10,7 @@
#include "NativeRegisterContextAIX_ppc64.h"
#include "NativeThreadAIX.h"
-#include "Plugins/Process/Utility/RegisterInfoPOSIX_ppc64.h"
+#include "Plugins/Process/Utility/RegisterInfoCommon_ppc64.h"
#include "lldb/Utility/RegisterValue.h"
using namespace lldb;
@@ -106,7 +106,7 @@ NativeRegisterContextAIX::CreateHostNativeRegisterContextAIX(
NativeRegisterContextAIX_ppc64::NativeRegisterContextAIX_ppc64(
const ArchSpec &target_arch, NativeThreadProtocol &native_thread)
: NativeRegisterContextRegisterInfo(
- native_thread, new RegisterInfoPOSIX_ppc64(target_arch)),
+ native_thread, new RegisterInfoCommon_ppc64(target_arch)),
NativeRegisterContextAIX(native_thread) {
switch (target_arch.GetMachine()) {
case llvm::Triple::ppc:
diff --git a/lldb/source/Plugins/Process/FreeBSD-Kernel-Core/RegisterContextFreeBSDKernelCore_arm.cpp b/lldb/source/Plugins/Process/FreeBSD-Kernel-Core/RegisterContextFreeBSDKernelCore_arm.cpp
index 1477cf75e9f6ff..621a7a314ab46c 100644
--- a/lldb/source/Plugins/Process/FreeBSD-Kernel-Core/RegisterContextFreeBSDKernelCore_arm.cpp
+++ b/lldb/source/Plugins/Process/FreeBSD-Kernel-Core/RegisterContextFreeBSDKernelCore_arm.cpp
@@ -22,7 +22,7 @@ using namespace lldb;
using namespace lldb_private;
RegisterContextFreeBSDKernelCore_arm::RegisterContextFreeBSDKernelCore_arm(
- Thread &thread, std::unique_ptr<RegisterInfoPOSIX_arm> register_info_up,
+ Thread &thread, std::unique_ptr<RegisterInfoCommon_arm> register_info_up,
lldb::addr_t pcb_addr)
: RegisterContextPOSIX_arm(thread, std::move(register_info_up)),
m_pcb_addr(pcb_addr) {}
diff --git a/lldb/source/Plugins/Process/FreeBSD-Kernel-Core/RegisterContextFreeBSDKernelCore_arm.h b/lldb/source/Plugins/Process/FreeBSD-Kernel-Core/RegisterContextFreeBSDKernelCore_arm.h
index cdd9f1b3288c18..8af593e9cbe5de 100644
--- a/lldb/source/Plugins/Process/FreeBSD-Kernel-Core/RegisterContextFreeBSDKernelCore_arm.h
+++ b/lldb/source/Plugins/Process/FreeBSD-Kernel-Core/RegisterContextFreeBSDKernelCore_arm.h
@@ -16,7 +16,7 @@ class RegisterContextFreeBSDKernelCore_arm : public RegisterContextPOSIX_arm {
public:
RegisterContextFreeBSDKernelCore_arm(
lldb_private::Thread &thread,
- std::unique_ptr<RegisterInfoPOSIX_arm> register_info_up,
+ std::unique_ptr<RegisterInfoCommon_arm> register_info_up,
lldb::addr_t pcb_addr);
bool ReadRegister(const lldb_private::RegisterInfo *reg_info,
diff --git a/lldb/source/Plugins/Process/FreeBSD-Kernel-Core/RegisterContextFreeBSDKernelCore_arm64.cpp b/lldb/source/Plugins/Process/FreeBSD-Kernel-Core/RegisterContextFreeBSDKernelCore_arm64.cpp
index 80a5e0cf13a7c4..3af209e406ae9a 100644
--- a/lldb/source/Plugins/Process/FreeBSD-Kernel-Core/RegisterContextFreeBSDKernelCore_arm64.cpp
+++ b/lldb/source/Plugins/Process/FreeBSD-Kernel-Core/RegisterContextFreeBSDKernelCore_arm64.cpp
@@ -27,7 +27,7 @@ using namespace lldb;
using namespace lldb_private;
RegisterContextFreeBSDKernelCore_arm64::RegisterContextFreeBSDKernelCore_arm64(
- Thread &thread, std::unique_ptr<RegisterInfoPOSIX_arm64> register_info_up,
+ Thread &thread, std::unique_ptr<RegisterInfoCommon_arm64> register_info_up,
lldb::addr_t pcb_addr)
: RegisterContextPOSIX_arm64(thread, std::move(register_info_up)),
m_pcb_addr(pcb_addr) {}
diff --git a/lldb/source/Plugins/Process/FreeBSD-Kernel-Core/RegisterContextFreeBSDKernelCore_arm64.h b/lldb/source/Plugins/Process/FreeBSD-Kernel-Core/RegisterContextFreeBSDKernelCore_arm64.h
index 873b77782c2489..3ad5ae7b88bae6 100644
--- a/lldb/source/Plugins/Process/FreeBSD-Kernel-Core/RegisterContextFreeBSDKernelCore_arm64.h
+++ b/lldb/source/Plugins/Process/FreeBSD-Kernel-Core/RegisterContextFreeBSDKernelCore_arm64.h
@@ -19,7 +19,7 @@ class RegisterContextFreeBSDKernelCore_arm64
public:
RegisterContextFreeBSDKernelCore_arm64(
lldb_private::Thread &thread,
- std::unique_ptr<RegisterInfoPOSIX_arm64> register_info_up,
+ std::unique_ptr<RegisterInfoCommon_arm64> register_info_up,
lldb::addr_t pcb_addr);
bool ReadRegister(const lldb_private::RegisterInfo *reg_info,
diff --git a/lldb/source/Plugins/Process/FreeBSD-Kernel-Core/RegisterContextFreeBSDKernelCore_riscv64.cpp b/lldb/source/Plugins/Process/FreeBSD-Kernel-Core/RegisterContextFreeBSDKernelCore_riscv64.cpp
index 52a2f91742c760..0d87a0d9c8ca84 100644
--- a/lldb/source/Plugins/Process/FreeBSD-Kernel-Core/RegisterContextFreeBSDKernelCore_riscv64.cpp
+++ b/lldb/source/Plugins/Process/FreeBSD-Kernel-Core/RegisterContextFreeBSDKernelCore_riscv64.cpp
@@ -23,7 +23,7 @@ using namespace lldb_private;
RegisterContextFreeBSDKernelCore_riscv64::
RegisterContextFreeBSDKernelCore_riscv64(
Thread &thread,
- std::unique_ptr<RegisterInfoPOSIX_riscv64> register_info_up,
+ std::unique_ptr<RegisterInfoCommon_riscv64> register_info_up,
lldb::addr_t pcb_addr)
: RegisterContextPOSIX_riscv64(thread, std::move(register_info_up)),
m_pcb_addr(pcb_addr) {}
diff --git a/lldb/source/Plugins/Process/FreeBSD-Kernel-Core/RegisterContextFreeBSDKernelCore_riscv64.h b/lldb/source/Plugins/Process/FreeBSD-Kernel-Core/RegisterContextFreeBSDKernelCore_riscv64.h
index 033671da8ff7da..cb96c5c989f2c1 100644
--- a/lldb/source/Plugins/Process/FreeBSD-Kernel-Core/RegisterContextFreeBSDKernelCore_riscv64.h
+++ b/lldb/source/Plugins/Process/FreeBSD-Kernel-Core/RegisterContextFreeBSDKernelCore_riscv64.h
@@ -17,7 +17,7 @@ class RegisterContextFreeBSDKernelCore_riscv64
public:
RegisterContextFreeBSDKernelCore_riscv64(
lldb_private::Thread &thread,
- std::unique_ptr<RegisterInfoPOSIX_riscv64> register_info_up,
+ std::unique_ptr<RegisterInfoCommon_riscv64> register_info_up,
lldb::addr_t pcb_addr);
bool ReadRegister(const lldb_private::RegisterInfo *reg_info,
diff --git a/lldb/source/Plugins/Process/FreeBSD-Kernel-Core/ThreadFreeBSDKernelCore.cpp b/lldb/source/Plugins/Process/FreeBSD-Kernel-Core/ThreadFreeBSDKernelCore.cpp
index 98b73e8de87ef8..4f0e7021d692db 100644
--- a/lldb/source/Plugins/Process/FreeBSD-Kernel-Core/ThreadFreeBSDKernelCore.cpp
+++ b/lldb/source/Plugins/Process/FreeBSD-Kernel-Core/ThreadFreeBSDKernelCore.cpp
@@ -14,10 +14,10 @@
#include "Plugins/Process/Utility/RegisterInfoFreeBSD_i386.h"
#include "Plugins/Process/Utility/RegisterInfoFreeBSD_x86_64.h"
-#include "Plugins/Process/Utility/RegisterInfoPOSIX_arm.h"
-#include "Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h"
-#include "Plugins/Process/Utility/RegisterInfoPOSIX_ppc64le.h"
-#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h"
+#include "Plugins/Process/Utility/RegisterInfoCommon_arm.h"
+#include "Plugins/Process/Utility/RegisterInfoCommon_arm64.h"
+#include "Plugins/Process/Utility/RegisterInfoCommon_ppc64le.h"
+#include "Plugins/Process/Utility/RegisterInfoCommon_riscv64.h"
#include "ProcessFreeBSDKernelCore.h"
#include "RegisterContextFreeBSDKernelCore_arm.h"
#include "RegisterContextFreeBSDKernelCore_arm64.h"
@@ -66,23 +66,23 @@ ThreadFreeBSDKernelCore::CreateRegisterContextForFrame(StackFrame *frame) {
case llvm::Triple::aarch64:
m_thread_reg_ctx_sp =
std::make_shared<RegisterContextFreeBSDKernelCore_arm64>(
- *this, std::make_unique<RegisterInfoPOSIX_arm64>(arch, 0),
+ *this, std::make_unique<RegisterInfoCommon_arm64>(arch, 0),
m_pcb_addr);
break;
case llvm::Triple::arm:
m_thread_reg_ctx_sp =
std::make_shared<RegisterContextFreeBSDKernelCore_arm>(
- *this, std::make_unique<RegisterInfoPOSIX_arm>(arch), m_pcb_addr);
+ *this, std::make_unique<RegisterInfoCommon_arm>(arch), m_pcb_addr);
break;
case llvm::Triple::ppc64le:
m_thread_reg_ctx_sp =
std::make_shared<RegisterContextFreeBSDKernelCore_ppc64le>(
- *this, new RegisterInfoPOSIX_ppc64le(arch), m_pcb_addr);
+ *this, new RegisterInfoCommon_ppc64le(arch), m_pcb_addr);
break;
case llvm::Triple::riscv64:
m_thread_reg_ctx_sp =
std::make_shared<RegisterContextFreeBSDKernelCore_riscv64>(
- *this, std::make_unique<RegisterInfoPOSIX_riscv64>(arch, 0),
+ *this, std::make_unique<RegisterInfoCommon_riscv64>(arch, 0),
m_pcb_addr);
break;
case llvm::Triple::x86:
diff --git a/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_arm.cpp b/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_arm.cpp
index cfee6e8e42c83e..fe4a6d3f104de0 100644
--- a/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_arm.cpp
+++ b/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_arm.cpp
@@ -15,7 +15,7 @@
#include "lldb/Utility/Status.h"
#include "Plugins/Process/FreeBSD/NativeProcessFreeBSD.h"
-#include "Plugins/Process/Utility/RegisterInfoPOSIX_arm.h"
+#include "Plugins/Process/Utility/RegisterInfoCommon_arm.h"
// clang-format off
#include <sys/param.h>
@@ -36,11 +36,11 @@ NativeRegisterContextFreeBSD::CreateHostNativeRegisterContextFreeBSD(
NativeRegisterContextFreeBSD_arm::NativeRegisterContextFreeBSD_arm(
const ArchSpec &target_arch, NativeThreadFreeBSD &native_thread)
: NativeRegisterContextRegisterInfo(
- native_thread, new RegisterInfoPOSIX_arm(target_arch)) {}
+ native_thread, new RegisterInfoCommon_arm(target_arch)) {}
-RegisterInfoPOSIX_arm &
+RegisterInfoCommon_arm &
NativeRegisterContextFreeBSD_arm::GetRegisterInfo() const {
- return static_cast<RegisterInfoPOSIX_arm &>(*m_register_info_interface_up);
+ return static_cast<RegisterInfoCommon_arm &>(*m_register_info_interface_up);
}
uint32_t NativeRegisterContextFreeBSD_arm::GetRegisterSetCount() const {
@@ -61,26 +61,26 @@ uint32_t NativeRegisterContextFreeBSD_arm::GetUserRegisterCount() const {
Status NativeRegisterContextFreeBSD_arm::ReadRegisterSet(uint32_t set) {
switch (set) {
- case RegisterInfoPOSIX_arm::GPRegSet:
+ case RegisterInfoCommon_arm::GPRegSet:
return NativeProcessFreeBSD::PtraceWrapper(PT_GETREGS, m_thread.GetID(),
m_reg_data.data());
- case RegisterInfoPOSIX_arm::FPRegSet:
+ case RegisterInfoCommon_arm::FPRegSet:
return NativeProcessFreeBSD::PtraceWrapper(
PT_GETVFPREGS, m_thread.GetID(),
- m_reg_data.data() + sizeof(RegisterInfoPOSIX_arm::GPR));
+ m_reg_data.data() + sizeof(RegisterInfoCommon_arm::GPR));
}
llvm_unreachable("NativeRegisterContextFreeBSD_arm::ReadRegisterSet");
}
Status NativeRegisterContextFreeBSD_arm::WriteRegisterSet(uint32_t set) {
switch (set) {
- case RegisterInfoPOSIX_arm::GPRegSet:
+ case RegisterInfoCommon_arm::GPRegSet:
return NativeProcessFreeBSD::PtraceWrapper(PT_SETREGS, m_thread.GetID(),
m_reg_data.data());
- case RegisterInfoPOSIX_arm::FPRegSet:
+ case RegisterInfoCommon_arm::FPRegSet:
return NativeProcessFreeBSD::PtraceWrapper(
PT_SETVFPREGS, m_thread.GetID(),
- m_reg_data.data() + sizeof(RegisterInfoPOSIX_arm::GPR));
+ m_reg_data.data() + sizeof(RegisterInfoCommon_arm::GPR));
}
llvm_unreachable("NativeRegisterContextFreeBSD_arm::WriteRegisterSet");
}
@@ -143,11 +143,11 @@ Status NativeRegisterContextFreeBSD_arm::ReadAllRegisterValues(
lldb::WritableDataBufferSP &data_sp) {
Status error;
- error = ReadRegisterSet(RegisterInfoPOSIX_arm::GPRegSet);
+ error = ReadRegisterSet(RegisterInfoCommon_arm::GPRegSet);
if (error.Fail())
return error;
- error = ReadRegisterSet(RegisterInfoPOSIX_arm::FPRegSet);
+ error = ReadRegisterSet(RegisterInfoCommon_arm::FPRegSet);
if (error.Fail())
return error;
@@ -188,11 +188,11 @@ Status NativeRegisterContextFreeBSD_arm::WriteAllRegisterValues(
}
::memcpy(m_reg_data.data(), src, m_reg_data.size());
- error = WriteRegisterSet(RegisterInfoPOSIX_arm::GPRegSet);
+ error = WriteRegisterSet(RegisterInfoCommon_arm::GPRegSet);
if (error.Fail())
return error;
- return WriteRegisterSet(RegisterInfoPOSIX_arm::FPRegSet);
+ return WriteRegisterSet(RegisterInfoCommon_arm::FPRegSet);
}
llvm::Error NativeRegisterContextFreeBSD_arm::CopyHardwareWatchpointsFrom(
diff --git a/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_arm.h b/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_arm.h
index b9537e6952f6c4..eecc6b89502efc 100644
--- a/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_arm.h
+++ b/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_arm.h
@@ -18,7 +18,7 @@
// clang-format on
#include "Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD.h"
-#include "Plugins/Process/Utility/RegisterInfoPOSIX_arm.h"
+#include "Plugins/Process/Utility/RegisterInfoCommon_arm.h"
#include <array>
@@ -57,7 +57,7 @@ class NativeRegisterContextFreeBSD_arm : public NativeRegisterContextFreeBSD {
Status ReadRegisterSet(uint32_t set);
Status WriteRegisterSet(uint32_t set);
- RegisterInfoPOSIX_arm &GetRegisterInfo() const;
+ RegisterInfoCommon_arm &GetRegisterInfo() const;
};
} // namespace process_freebsd
diff --git a/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_arm64.cpp b/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_arm64.cpp
index 1f2e0d5904148a..f30dd262ebf1ff 100644
--- a/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_arm64.cpp
+++ b/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_arm64.cpp
@@ -16,7 +16,7 @@
#include "Plugins/Process/FreeBSD/NativeProcessFreeBSD.h"
#include "Plugins/Process/POSIX/ProcessPOSIXLog.h"
-#include "Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h"
+#include "Plugins/Process/Utility/RegisterInfoCommon_arm64.h"
#include "Plugins/Process/Utility/RegisterTypeDetector_arm64.h"
// clang-format off
@@ -54,16 +54,16 @@ NativeRegisterContextFreeBSD::CreateHostNativeRegisterContextFreeBSD(
NativeRegisterContextFreeBSD_arm64::NativeRegisterContextFreeBSD_arm64(
const ArchSpec &target_arch, NativeThreadFreeBSD &native_thread)
: NativeRegisterContextRegisterInfo(
- native_thread, new RegisterInfoPOSIX_arm64(target_arch, 0)),
+ native_thread, new RegisterInfoCommon_arm64(target_arch, 0)),
m_read_dbreg(false) {
g_register_type_detector.UpdateRegisterInfo(
GetRegisterInfoInterface().GetRegisterInfo(),
GetRegisterInfoInterface().GetRegisterCount());
}
-RegisterInfoPOSIX_arm64 &
+RegisterInfoCommon_arm64 &
NativeRegisterContextFreeBSD_arm64::GetRegisterInfo() const {
- return static_cast<RegisterInfoPOSIX_arm64 &>(*m_register_info_interface_up);
+ return static_cast<RegisterInfoCommon_arm64 &>(*m_register_info_interface_up);
}
uint32_t NativeRegisterContextFreeBSD_arm64::GetRegisterSetCount() const {
@@ -84,26 +84,26 @@ uint32_t NativeRegisterContextFreeBSD_arm64::GetUserRegisterCount() const {
Status NativeRegisterContextFreeBSD_arm64::ReadRegisterSet(uint32_t set) {
switch (set) {
- case RegisterInfoPOSIX_arm64::GPRegSet:
+ case RegisterInfoCommon_arm64::GPRegSet:
return NativeProcessFreeBSD::PtraceWrapper(PT_GETREGS, m_thread.GetID(),
m_reg_data.data());
- case RegisterInfoPOSIX_arm64::FPRegSet:
+ case RegisterInfoCommon_arm64::FPRegSet:
return NativeProcessFreeBSD::PtraceWrapper(
PT_GETFPREGS, m_thread.GetID(),
- m_reg_data.data() + sizeof(RegisterInfoPOSIX_arm64::GPR));
+ m_reg_data.data() + sizeof(RegisterInfoCommon_arm64::GPR));
}
llvm_unreachable("NativeRegisterContextFreeBSD_arm64::ReadRegisterSet");
}
Status NativeRegisterContextFreeBSD_arm64::WriteRegisterSet(uint32_t set) {
switch (set) {
- case RegisterInfoPOSIX_arm64::GPRegSet:
+ case RegisterInfoCommon_arm64::GPRegSet:
return NativeProcessFreeBSD::PtraceWrapper(PT_SETREGS, m_thread.GetID(),
m_reg_data.data());
- case RegisterInfoPOSIX_arm64::FPRegSet:
+ case RegisterInfoCommon_arm64::FPRegSet:
return NativeProcessFreeBSD::PtraceWrapper(
PT_SETFPREGS, m_thread.GetID(),
- m_reg_data.data() + sizeof(RegisterInfoPOSIX_arm64::GPR));
+ m_reg_data.data() + sizeof(RegisterInfoCommon_arm64::GPR));
}
llvm_unreachable("NativeRegisterContextFreeBSD_arm64::WriteRegisterSet");
}
@@ -164,11 +164,11 @@ Status NativeRegisterContextFreeBSD_arm64::ReadAllRegisterValues(
lldb::WritableDataBufferSP &data_sp) {
Status error;
- error = ReadRegisterSet(RegisterInfoPOSIX_arm64::GPRegSet);
+ error = ReadRegisterSet(RegisterInfoCommon_arm64::GPRegSet);
if (error.Fail())
return error;
- error = ReadRegisterSet(RegisterInfoPOSIX_arm64::FPRegSet);
+ error = ReadRegisterSet(RegisterInfoCommon_arm64::FPRegSet);
if (error.Fail())
return error;
@@ -209,11 +209,11 @@ Status NativeRegisterContextFreeBSD_arm64::WriteAllRegisterValues(
}
::memcpy(m_reg_data.data(), src, m_reg_data.size());
- error = WriteRegisterSet(RegisterInfoPOSIX_arm64::GPRegSet);
+ error = WriteRegisterSet(RegisterInfoCommon_arm64::GPRegSet);
if (error.Fail())
return error;
- return WriteRegisterSet(RegisterInfoPOSIX_arm64::FPRegSet);
+ return WriteRegisterSet(RegisterInfoCommon_arm64::FPRegSet);
}
llvm::Error NativeRegisterContextFreeBSD_arm64::CopyHardwareWatchpointsFrom(
diff --git a/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_arm64.h b/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_arm64.h
index 20cbd643e95cfc..613cfb761e52f7 100644
--- a/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_arm64.h
+++ b/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_arm64.h
@@ -19,7 +19,7 @@
#include "Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD.h"
#include "Plugins/Process/Utility/NativeRegisterContextDBReg_arm64.h"
-#include "Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h"
+#include "Plugins/Process/Utility/RegisterInfoCommon_arm64.h"
#include <array>
@@ -69,7 +69,7 @@ class NativeRegisterContextFreeBSD_arm64
llvm::Error ReadHardwareDebugInfo() override;
llvm::Error WriteHardwareDebugRegs(DREGType hwbType) override;
- RegisterInfoPOSIX_arm64 &GetRegisterInfo() const;
+ RegisterInfoCommon_arm64 &GetRegisterInfo() const;
};
} // namespace process_freebsd
diff --git a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm.cpp b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm.cpp
index a44eb032b8dc19..515b9ed9f1dcdc 100644
--- a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm.cpp
+++ b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm.cpp
@@ -13,7 +13,7 @@
#include "Plugins/Process/Linux/NativeProcessLinux.h"
#include "Plugins/Process/Linux/Procfs.h"
#include "Plugins/Process/POSIX/ProcessPOSIXLog.h"
-#include "Plugins/Process/Utility/RegisterInfoPOSIX_arm.h"
+#include "Plugins/Process/Utility/RegisterInfoCommon_arm.h"
#include "lldb/Host/HostInfo.h"
#include "lldb/Utility/DataBufferHeap.h"
#include "lldb/Utility/Log.h"
@@ -75,7 +75,7 @@ NativeRegisterContextLinux_arm::NativeRegisterContextLinux_arm(
const ArchSpec &target_arch, NativeThreadProtocol &native_thread)
: NativeRegisterContextRegisterInfo(
native_thread,
- new RegisterInfoPOSIX_arm(target_arch, /*has_tls_reg=*/true)),
+ new RegisterInfoCommon_arm(target_arch, /*has_tls_reg=*/true)),
NativeRegisterContextLinux(native_thread) {
assert(target_arch.GetMachine() == llvm::Triple::arm);
@@ -89,8 +89,8 @@ NativeRegisterContextLinux_arm::NativeRegisterContextLinux_arm(
m_refresh_hwdebug_info = true;
}
-RegisterInfoPOSIX_arm &NativeRegisterContextLinux_arm::GetRegisterInfo() const {
- return static_cast<RegisterInfoPOSIX_arm &>(*m_register_info_interface_up);
+RegisterInfoCommon_arm &NativeRegisterContextLinux_arm::GetRegisterInfo() const {
+ return static_cast<RegisterInfoCommon_arm &>(*m_register_info_interface_up);
}
uint32_t NativeRegisterContextLinux_arm::GetRegisterSetCount() const {
@@ -293,21 +293,21 @@ Status NativeRegisterContextLinux_arm::WriteAllRegisterValues(
bool NativeRegisterContextLinux_arm::IsGPR(unsigned reg) const {
if (GetRegisterInfo().GetRegisterSetFromRegisterIndex(reg) ==
- RegisterInfoPOSIX_arm::GPRegSet)
+ RegisterInfoCommon_arm::GPRegSet)
return true;
return false;
}
bool NativeRegisterContextLinux_arm::IsFPR(unsigned reg) const {
if (GetRegisterInfo().GetRegisterSetFromRegisterIndex(reg) ==
- RegisterInfoPOSIX_arm::FPRegSet)
+ RegisterInfoCommon_arm::FPRegSet)
return true;
return false;
}
bool NativeRegisterContextLinux_arm::IsTLS(unsigned reg) const {
return GetRegisterInfo().GetRegisterSetFromRegisterIndex(reg) ==
- RegisterInfoPOSIX_arm::TLSRegSet;
+ RegisterInfoCommon_arm::TLSRegSet;
}
llvm::Error NativeRegisterContextLinux_arm::ReadHardwareDebugInfo() {
diff --git a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm.h b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm.h
index 3722f667b62c57..1fea0aa4baf38f 100644
--- a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm.h
+++ b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm.h
@@ -13,7 +13,7 @@
#include "Plugins/Process/Linux/NativeRegisterContextLinux.h"
#include "Plugins/Process/Utility/NativeRegisterContextDBReg_arm.h"
-#include "Plugins/Process/Utility/RegisterInfoPOSIX_arm.h"
+#include "Plugins/Process/Utility/RegisterInfoCommon_arm.h"
#include "Plugins/Process/Utility/lldb-arm-register-enums.h"
namespace lldb_private {
@@ -72,8 +72,8 @@ class NativeRegisterContextLinux_arm : public NativeRegisterContextLinux,
private:
uint32_t m_gpr_arm[k_num_gpr_registers_arm];
- RegisterInfoPOSIX_arm::FPU m_fpr;
- RegisterInfoPOSIX_arm::TLS m_tls;
+ RegisterInfoCommon_arm::FPU m_fpr;
+ RegisterInfoCommon_arm::TLS m_tls;
bool m_refresh_hwdebug_info;
@@ -92,7 +92,7 @@ class NativeRegisterContextLinux_arm : public NativeRegisterContextLinux,
uint32_t CalculateFprOffset(const RegisterInfo *reg_info) const;
- RegisterInfoPOSIX_arm &GetRegisterInfo() const;
+ RegisterInfoCommon_arm &GetRegisterInfo() const;
};
} // namespace process_linux
diff --git a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
index 1889cab95ab667..6a7a5d615a3a86 100644
--- a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
+++ b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
@@ -16,7 +16,7 @@
#include "Plugins/Process/Linux/Procfs.h"
#include "Plugins/Process/POSIX/ProcessPOSIXLog.h"
#include "Plugins/Process/Utility/MemoryTagManagerAArch64MTE.h"
-#include "Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h"
+#include "Plugins/Process/Utility/RegisterInfoCommon_arm64.h"
#include "Plugins/Process/Utility/RegisterTypeDetector_arm64.h"
#include "lldb/Host/HostInfo.h"
#include "lldb/Host/common/NativeProcessProtocol.h"
@@ -141,7 +141,7 @@ size_t NativeRegisterContextLinux_arm64::GetSetSize(
switch (set) {
case RegisterSetType::GPR:
// Returns sizeof arm64 GPR ptrace buffer, which is different
- // from GetGPRSize which returns sizeof RegisterInfoPOSIX_arm64::GPR.
+ // from GetGPRSize which returns sizeof RegisterInfoCommon_arm64::GPR.
return sizeof(m_gpr_arm64);
case RegisterSetType::FPR:
return sizeof(m_fpr);
@@ -234,7 +234,7 @@ NativeRegisterContextLinux::CreateHostNativeRegisterContextLinux(
native_thread.GetID(), ®set,
&ioVec, sizeof(sve_header))
.Success())
- opt_regsets.Set(RegisterInfoPOSIX_arm64::eRegsetMaskSVE);
+ opt_regsets.Set(RegisterInfoCommon_arm64::eRegsetMaskSVE);
// We may have the Scalable Matrix Extension (SME) which adds a
// streaming SVE mode. Systems can have SVE and/or SME.
@@ -244,7 +244,7 @@ NativeRegisterContextLinux::CreateHostNativeRegisterContextLinux(
native_thread.GetID(), ®set,
&ioVec, sizeof(sve_header))
.Success())
- opt_regsets.Set(RegisterInfoPOSIX_arm64::eRegsetMaskSSVE);
+ opt_regsets.Set(RegisterInfoCommon_arm64::eRegsetMaskSSVE);
sve::user_za_header za_header;
ioVec.iov_base = &za_header;
@@ -254,7 +254,7 @@ NativeRegisterContextLinux::CreateHostNativeRegisterContextLinux(
native_thread.GetID(), ®set,
&ioVec, sizeof(za_header))
.Success())
- opt_regsets.Set(RegisterInfoPOSIX_arm64::eRegsetMaskZA);
+ opt_regsets.Set(RegisterInfoCommon_arm64::eRegsetMaskZA);
// SME's ZT0 is a 512 bit register.
std::array<uint8_t, 64> zt_reg;
@@ -265,29 +265,29 @@ NativeRegisterContextLinux::CreateHostNativeRegisterContextLinux(
native_thread.GetID(), ®set,
&ioVec, zt_reg.size())
.Success())
- opt_regsets.Set(RegisterInfoPOSIX_arm64::eRegsetMaskZT);
+ opt_regsets.Set(RegisterInfoCommon_arm64::eRegsetMaskZT);
NativeProcessLinux &process = native_thread.GetProcess();
std::optional<uint64_t> auxv_at_hwcap =
process.GetAuxValue(AuxVector::AUXV_AT_HWCAP);
if (auxv_at_hwcap && (*auxv_at_hwcap & HWCAP_PACA))
- opt_regsets.Set(RegisterInfoPOSIX_arm64::eRegsetMaskPAuth);
+ opt_regsets.Set(RegisterInfoCommon_arm64::eRegsetMaskPAuth);
std::optional<uint64_t> auxv_at_hwcap2 =
process.GetAuxValue(AuxVector::AUXV_AT_HWCAP2);
if (auxv_at_hwcap2) {
if (*auxv_at_hwcap2 & HWCAP2_MTE)
- opt_regsets.Set(RegisterInfoPOSIX_arm64::eRegsetMaskMTE);
+ opt_regsets.Set(RegisterInfoCommon_arm64::eRegsetMaskMTE);
if (*auxv_at_hwcap2 & HWCAP2_FPMR)
- opt_regsets.Set(RegisterInfoPOSIX_arm64::eRegsetMaskFPMR);
+ opt_regsets.Set(RegisterInfoCommon_arm64::eRegsetMaskFPMR);
if (*auxv_at_hwcap & HWCAP_GCS)
- opt_regsets.Set(RegisterInfoPOSIX_arm64::eRegsetMaskGCS);
+ opt_regsets.Set(RegisterInfoCommon_arm64::eRegsetMaskGCS);
if (*auxv_at_hwcap2 & HWCAP2_POE)
- opt_regsets.Set(RegisterInfoPOSIX_arm64::eRegsetMaskPOE);
+ opt_regsets.Set(RegisterInfoCommon_arm64::eRegsetMaskPOE);
}
- opt_regsets.Set(RegisterInfoPOSIX_arm64::eRegsetMaskTLS);
+ opt_regsets.Set(RegisterInfoCommon_arm64::eRegsetMaskTLS);
std::optional<uint64_t> auxv_at_hwcap3 =
process.GetAuxValue(AuxVector::AUXV_AT_HWCAP3);
@@ -298,7 +298,7 @@ NativeRegisterContextLinux::CreateHostNativeRegisterContextLinux(
auxv_at_hwcap3.value_or(0));
auto register_info_up =
- std::make_unique<RegisterInfoPOSIX_arm64>(target_arch, opt_regsets);
+ std::make_unique<RegisterInfoCommon_arm64>(target_arch, opt_regsets);
return std::make_unique<NativeRegisterContextLinux_arm64>(
target_arch, native_thread, std::move(register_info_up));
}
@@ -310,12 +310,12 @@ NativeRegisterContextLinux::CreateHostNativeRegisterContextLinux(
llvm::Expected<ArchSpec>
NativeRegisterContextLinux::DetermineArchitecture(lldb::tid_t tid) {
return DetermineArchitectureViaGPR(
- tid, RegisterInfoPOSIX_arm64::GetGPRSizeStatic());
+ tid, RegisterInfoCommon_arm64::GetGPRSizeStatic());
}
NativeRegisterContextLinux_arm64::NativeRegisterContextLinux_arm64(
const ArchSpec &target_arch, NativeThreadProtocol &native_thread,
- std::unique_ptr<RegisterInfoPOSIX_arm64> register_info_up)
+ std::unique_ptr<RegisterInfoCommon_arm64> register_info_up)
: NativeRegisterContextRegisterInfo(native_thread,
register_info_up.release()),
NativeRegisterContextLinux(native_thread) {
@@ -337,9 +337,9 @@ NativeRegisterContextLinux_arm64::NativeRegisterContextLinux_arm64(
m_sve_state = SVEState::Disabled;
}
-RegisterInfoPOSIX_arm64 &
+RegisterInfoCommon_arm64 &
NativeRegisterContextLinux_arm64::GetRegisterInfo() const {
- return static_cast<RegisterInfoPOSIX_arm64 &>(*m_register_info_interface_up);
+ return static_cast<RegisterInfoCommon_arm64 &>(*m_register_info_interface_up);
}
uint32_t NativeRegisterContextLinux_arm64::GetRegisterSetCount() const {
@@ -1946,7 +1946,7 @@ void NativeRegisterContextLinux_arm64::ConfigureRegisterContext() {
// On every stop we configure SVE vector length by calling
// ConfigureVectorLengthSVE regardless of current SVEState of this thread.
- uint32_t vq = RegisterInfoPOSIX_arm64::eVectorQuadwordAArch64SVE;
+ uint32_t vq = RegisterInfoCommon_arm64::eVectorQuadwordAArch64SVE;
if (sve::vl_valid(m_sve_header.vl))
vq = sve::vq_from_vl(m_sve_header.vl);
@@ -1958,7 +1958,7 @@ void NativeRegisterContextLinux_arm64::ConfigureRegisterContext() {
if (!IsValid(RegisterSetType::ZA_HEADER)) {
Status error = ReadZAHeader();
if (error.Success()) {
- uint32_t vq = RegisterInfoPOSIX_arm64::eVectorQuadwordAArch64SVE;
+ uint32_t vq = RegisterInfoCommon_arm64::eVectorQuadwordAArch64SVE;
if (sve::vl_valid(m_za_header.vl))
vq = sve::vq_from_vl(m_za_header.vl);
diff --git a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
index 86a317c11505a1..8dfc1f54c5dbdf 100644
--- a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
+++ b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
@@ -14,7 +14,7 @@
#include "Plugins/Process/Linux/NativeRegisterContextLinux.h"
#include "Plugins/Process/Utility/LinuxPTraceDefines_arm64sve.h"
#include "Plugins/Process/Utility/NativeRegisterContextDBReg_arm64.h"
-#include "Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h"
+#include "Plugins/Process/Utility/RegisterInfoCommon_arm64.h"
#include "llvm/ADT/BitmaskEnum.h"
@@ -31,7 +31,7 @@ class NativeRegisterContextLinux_arm64
public:
NativeRegisterContextLinux_arm64(
const ArchSpec &target_arch, NativeThreadProtocol &native_thread,
- std::unique_ptr<RegisterInfoPOSIX_arm64> register_info_up);
+ std::unique_ptr<RegisterInfoCommon_arm64> register_info_up);
uint32_t GetRegisterSetCount() const override;
@@ -71,7 +71,7 @@ class NativeRegisterContextLinux_arm64
void *GetGPRBuffer() override { return &m_gpr_arm64; }
// GetGPRBufferSize returns sizeof arm64 GPR ptrace buffer, it is different
- // from GetGPRSize which returns sizeof RegisterInfoPOSIX_arm64::GPR.
+ // from GetGPRSize which returns sizeof RegisterInfoCommon_arm64::GPR.
size_t GetGPRBufferSize() { return sizeof(m_gpr_arm64); }
void *GetFPRBuffer() override { return &m_fpr; }
@@ -155,7 +155,7 @@ class NativeRegisterContextLinux_arm64
struct user_pt_regs m_gpr_arm64{};
/// Floating-point registers including extended register sets.
- RegisterInfoPOSIX_arm64::FPU m_fpr{};
+ RegisterInfoCommon_arm64::FPU m_fpr{};
SVEState m_sve_state = SVEState::Unknown;
struct sve::user_sve_header m_sve_header{};
@@ -263,7 +263,7 @@ class NativeRegisterContextLinux_arm64
uint32_t CalculateFprOffset(const RegisterInfo *reg_info,
bool streaming_fpsimd) const;
- RegisterInfoPOSIX_arm64 &GetRegisterInfo() const;
+ RegisterInfoCommon_arm64 &GetRegisterInfo() const;
void ConfigureRegisterContext();
diff --git a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_loongarch64.cpp b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_loongarch64.cpp
index 850a380b5cf3f8..ed5da5c4b61965 100644
--- a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_loongarch64.cpp
+++ b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_loongarch64.cpp
@@ -12,7 +12,7 @@
#include "Plugins/Process/Linux/NativeProcessLinux.h"
#include "Plugins/Process/Linux/Procfs.h"
-#include "Plugins/Process/Utility/RegisterInfoPOSIX_loongarch64.h"
+#include "Plugins/Process/Utility/RegisterInfoCommon_loongarch64.h"
#include "Plugins/Process/Utility/lldb-loongarch-register-enums.h"
#include "lldb/Host/HostInfo.h"
#include "lldb/Utility/DataBufferHeap.h"
@@ -84,7 +84,7 @@ NativeRegisterContextLinux::CreateHostNativeRegisterContextLinux(
switch (target_arch.GetMachine()) {
case llvm::Triple::loongarch64: {
Flags opt_regsets;
- auto register_info_up = std::make_unique<RegisterInfoPOSIX_loongarch64>(
+ auto register_info_up = std::make_unique<RegisterInfoCommon_loongarch64>(
target_arch, opt_regsets);
return std::make_unique<NativeRegisterContextLinux_loongarch64>(
target_arch, native_thread, std::move(register_info_up));
@@ -101,7 +101,7 @@ NativeRegisterContextLinux::DetermineArchitecture(lldb::tid_t tid) {
NativeRegisterContextLinux_loongarch64::NativeRegisterContextLinux_loongarch64(
const ArchSpec &target_arch, NativeThreadProtocol &native_thread,
- std::unique_ptr<RegisterInfoPOSIX_loongarch64> register_info_up)
+ std::unique_ptr<RegisterInfoCommon_loongarch64> register_info_up)
: NativeRegisterContextRegisterInfo(native_thread,
register_info_up.release()),
NativeRegisterContextLinux(native_thread) {
@@ -123,9 +123,9 @@ NativeRegisterContextLinux_loongarch64::NativeRegisterContextLinux_loongarch64(
m_lasx_is_valid = false;
}
-const RegisterInfoPOSIX_loongarch64 &
+const RegisterInfoCommon_loongarch64 &
NativeRegisterContextLinux_loongarch64::GetRegisterInfo() const {
- return static_cast<const RegisterInfoPOSIX_loongarch64 &>(
+ return static_cast<const RegisterInfoCommon_loongarch64 &>(
NativeRegisterContextRegisterInfo::GetRegisterInfoInterface());
}
@@ -369,22 +369,22 @@ Status NativeRegisterContextLinux_loongarch64::WriteAllRegisterValues(
bool NativeRegisterContextLinux_loongarch64::IsGPR(unsigned reg) const {
return GetRegisterInfo().GetRegisterSetFromRegisterIndex(reg) ==
- RegisterInfoPOSIX_loongarch64::GPRegSet;
+ RegisterInfoCommon_loongarch64::GPRegSet;
}
bool NativeRegisterContextLinux_loongarch64::IsFPR(unsigned reg) const {
return GetRegisterInfo().GetRegisterSetFromRegisterIndex(reg) ==
- RegisterInfoPOSIX_loongarch64::FPRegSet;
+ RegisterInfoCommon_loongarch64::FPRegSet;
}
bool NativeRegisterContextLinux_loongarch64::IsLSX(unsigned reg) const {
return GetRegisterInfo().GetRegisterSetFromRegisterIndex(reg) ==
- RegisterInfoPOSIX_loongarch64::LSXRegSet;
+ RegisterInfoCommon_loongarch64::LSXRegSet;
}
bool NativeRegisterContextLinux_loongarch64::IsLASX(unsigned reg) const {
return GetRegisterInfo().GetRegisterSetFromRegisterIndex(reg) ==
- RegisterInfoPOSIX_loongarch64::LASXRegSet;
+ RegisterInfoCommon_loongarch64::LASXRegSet;
}
Status NativeRegisterContextLinux_loongarch64::ReadGPR() {
diff --git a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_loongarch64.h b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_loongarch64.h
index 2b2bb7d29d82f1..fc6bb05211c7da 100644
--- a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_loongarch64.h
+++ b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_loongarch64.h
@@ -13,7 +13,7 @@
#include "Plugins/Process/Linux/NativeRegisterContextLinux.h"
#include "Plugins/Process/Utility/NativeRegisterContextDBReg_loongarch.h"
-#include "Plugins/Process/Utility/RegisterInfoPOSIX_loongarch64.h"
+#include "Plugins/Process/Utility/RegisterInfoCommon_loongarch64.h"
#include <asm/ptrace.h>
@@ -28,7 +28,7 @@ class NativeRegisterContextLinux_loongarch64
public:
NativeRegisterContextLinux_loongarch64(
const ArchSpec &target_arch, NativeThreadProtocol &native_thread,
- std::unique_ptr<RegisterInfoPOSIX_loongarch64> register_info_up);
+ std::unique_ptr<RegisterInfoCommon_loongarch64> register_info_up);
uint32_t GetRegisterSetCount() const override;
@@ -85,10 +85,10 @@ class NativeRegisterContextLinux_loongarch64
bool m_lasx_is_valid;
bool m_refresh_hwdebug_info;
- RegisterInfoPOSIX_loongarch64::GPR m_gpr;
- RegisterInfoPOSIX_loongarch64::FPR m_fpr;
- RegisterInfoPOSIX_loongarch64::LSX m_lsx;
- RegisterInfoPOSIX_loongarch64::LASX m_lasx;
+ RegisterInfoCommon_loongarch64::GPR m_gpr;
+ RegisterInfoCommon_loongarch64::FPR m_fpr;
+ RegisterInfoCommon_loongarch64::LSX m_lsx;
+ RegisterInfoCommon_loongarch64::LASX m_lasx;
bool IsGPR(unsigned reg) const;
@@ -104,7 +104,7 @@ class NativeRegisterContextLinux_loongarch64
uint32_t CalculateLasxOffset(const RegisterInfo *reg_info) const;
- const RegisterInfoPOSIX_loongarch64 &GetRegisterInfo() const;
+ const RegisterInfoCommon_loongarch64 &GetRegisterInfo() const;
llvm::Error ReadHardwareDebugInfo() override;
diff --git a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_ppc64le.cpp b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_ppc64le.cpp
index efa169b3917391..b58954510a40ba 100644
--- a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_ppc64le.cpp
+++ b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_ppc64le.cpp
@@ -16,7 +16,7 @@
#include "Plugins/Process/Linux/NativeProcessLinux.h"
#include "Plugins/Process/Linux/Procfs.h"
#include "Plugins/Process/POSIX/ProcessPOSIXLog.h"
-#include "Plugins/Process/Utility/RegisterInfoPOSIX_ppc64le.h"
+#include "Plugins/Process/Utility/RegisterInfoCommon_ppc64le.h"
#include "lldb/Host/HostInfo.h"
#include "lldb/Host/common/NativeProcessProtocol.h"
#include "lldb/Utility/DataBufferHeap.h"
@@ -131,7 +131,7 @@ NativeRegisterContextLinux::DetermineArchitecture(lldb::tid_t tid) {
NativeRegisterContextLinux_ppc64le::NativeRegisterContextLinux_ppc64le(
const ArchSpec &target_arch, NativeThreadProtocol &native_thread)
: NativeRegisterContextRegisterInfo(
- native_thread, new RegisterInfoPOSIX_ppc64le(target_arch)),
+ native_thread, new RegisterInfoCommon_ppc64le(target_arch)),
NativeRegisterContextLinux(native_thread) {
if (target_arch.GetMachine() != llvm::Triple::ppc64le) {
llvm_unreachable("Unhandled target architecture.");
diff --git a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_riscv64.cpp b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_riscv64.cpp
index d58755b92d0632..43cc522eff0367 100644
--- a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_riscv64.cpp
+++ b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_riscv64.cpp
@@ -12,7 +12,7 @@
#include "Plugins/Process/Linux/NativeProcessLinux.h"
#include "Plugins/Process/Linux/Procfs.h"
-#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h"
+#include "Plugins/Process/Utility/RegisterInfoCommon_riscv64.h"
#include "Plugins/Process/Utility/lldb-riscv-register-enums.h"
#include "lldb/Host/HostInfo.h"
#include "lldb/Utility/DataBufferHeap.h"
@@ -39,9 +39,9 @@ NativeRegisterContextLinux::CreateHostNativeRegisterContextLinux(
const ArchSpec &target_arch, NativeThreadLinux &native_thread) {
switch (target_arch.GetMachine()) {
case llvm::Triple::riscv64: {
- Flags opt_regsets(RegisterInfoPOSIX_riscv64::eRegsetMaskDefault);
+ Flags opt_regsets(RegisterInfoCommon_riscv64::eRegsetMaskDefault);
- RegisterInfoPOSIX_riscv64::FPR fpr;
+ RegisterInfoCommon_riscv64::FPR fpr;
struct iovec ioVec;
ioVec.iov_base = &fpr;
ioVec.iov_len = sizeof(fpr);
@@ -51,11 +51,11 @@ NativeRegisterContextLinux::CreateHostNativeRegisterContextLinux(
native_thread.GetID(), ®set,
&ioVec, sizeof(fpr))
.Success()) {
- opt_regsets.Set(RegisterInfoPOSIX_riscv64::eRegsetMaskFP);
+ opt_regsets.Set(RegisterInfoCommon_riscv64::eRegsetMaskFP);
}
auto register_info_up =
- std::make_unique<RegisterInfoPOSIX_riscv64>(target_arch, opt_regsets);
+ std::make_unique<RegisterInfoCommon_riscv64>(target_arch, opt_regsets);
return std::make_unique<NativeRegisterContextLinux_riscv64>(
target_arch, native_thread, std::move(register_info_up));
}
@@ -71,7 +71,7 @@ NativeRegisterContextLinux::DetermineArchitecture(lldb::tid_t tid) {
NativeRegisterContextLinux_riscv64::NativeRegisterContextLinux_riscv64(
const ArchSpec &target_arch, NativeThreadProtocol &native_thread,
- std::unique_ptr<RegisterInfoPOSIX_riscv64> register_info_up)
+ std::unique_ptr<RegisterInfoCommon_riscv64> register_info_up)
: NativeRegisterContextRegisterInfo(native_thread,
register_info_up.release()),
NativeRegisterContextLinux(native_thread) {
@@ -82,9 +82,9 @@ NativeRegisterContextLinux_riscv64::NativeRegisterContextLinux_riscv64(
m_fpu_is_valid = false;
}
-const RegisterInfoPOSIX_riscv64 &
+const RegisterInfoCommon_riscv64 &
NativeRegisterContextLinux_riscv64::GetRegisterInfo() const {
- return static_cast<const RegisterInfoPOSIX_riscv64 &>(
+ return static_cast<const RegisterInfoCommon_riscv64 &>(
NativeRegisterContextRegisterInfo::GetRegisterInfoInterface());
}
@@ -286,7 +286,7 @@ size_t NativeRegisterContextLinux_riscv64::GetRegContextSize() {
bool NativeRegisterContextLinux_riscv64::IsGPR(unsigned reg) const {
return GetRegisterInfo().GetRegisterSetFromRegisterIndex(reg) ==
- RegisterInfoPOSIX_riscv64::GPRegSet;
+ RegisterInfoCommon_riscv64::GPRegSet;
}
bool NativeRegisterContextLinux_riscv64::IsFPR(unsigned reg) const {
diff --git a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_riscv64.h b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_riscv64.h
index d5cc50131cdc30..d5df762c9bee63 100644
--- a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_riscv64.h
+++ b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_riscv64.h
@@ -12,7 +12,7 @@
#define lldb_NativeRegisterContextLinux_riscv64_h
#include "Plugins/Process/Linux/NativeRegisterContextLinux.h"
-#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h"
+#include "Plugins/Process/Utility/RegisterInfoCommon_riscv64.h"
#include <asm/ptrace.h>
@@ -25,7 +25,7 @@ class NativeRegisterContextLinux_riscv64 : public NativeRegisterContextLinux {
public:
NativeRegisterContextLinux_riscv64(
const ArchSpec &target_arch, NativeThreadProtocol &native_thread,
- std::unique_ptr<RegisterInfoPOSIX_riscv64> register_info_up);
+ std::unique_ptr<RegisterInfoCommon_riscv64> register_info_up);
uint32_t GetRegisterSetCount() const override;
@@ -71,9 +71,9 @@ class NativeRegisterContextLinux_riscv64 : public NativeRegisterContextLinux {
bool m_gpr_is_valid;
bool m_fpu_is_valid;
- RegisterInfoPOSIX_riscv64::GPR m_gpr;
+ RegisterInfoCommon_riscv64::GPR m_gpr;
- RegisterInfoPOSIX_riscv64::FPR m_fpr;
+ RegisterInfoCommon_riscv64::FPR m_fpr;
size_t GetRegContextSize();
@@ -83,7 +83,7 @@ class NativeRegisterContextLinux_riscv64 : public NativeRegisterContextLinux {
uint32_t CalculateFprOffset(const RegisterInfo *reg_info) const;
- const RegisterInfoPOSIX_riscv64 &GetRegisterInfo() const;
+ const RegisterInfoCommon_riscv64 &GetRegisterInfo() const;
};
} // namespace process_linux
diff --git a/lldb/source/Plugins/Process/Utility/CMakeLists.txt b/lldb/source/Plugins/Process/Utility/CMakeLists.txt
index cd2e19d5d5e302..43bd2848c34b59 100644
--- a/lldb/source/Plugins/Process/Utility/CMakeLists.txt
+++ b/lldb/source/Plugins/Process/Utility/CMakeLists.txt
@@ -18,14 +18,14 @@ add_lldb_library(lldbRegister NO_PLUGIN_DEPENDENCIES
RegisterInfoWindows_x86_64.cpp
RegisterTypeDetector_arm64.cpp
RegisterInfos_x86_64_with_base_shared.cpp
- RegisterInfoPOSIX_arm.cpp
- RegisterInfoPOSIX_arm64.cpp
- RegisterInfoPOSIX_loongarch64.cpp
- RegisterInfoPOSIX_ppc64le.cpp
- RegisterInfoPOSIX_ppc64.cpp
- RegisterInfoPOSIX_riscv32.cpp
- RegisterInfoPOSIX_riscv64.cpp
- RegisterInfoPOSIXDynamic_riscv32.cpp
+ RegisterInfoCommon_arm.cpp
+ RegisterInfoCommon_arm64.cpp
+ RegisterInfoCommon_loongarch64.cpp
+ RegisterInfoCommon_ppc64le.cpp
+ RegisterInfoCommon_ppc64.cpp
+ RegisterInfoCommon_riscv32.cpp
+ RegisterInfoCommon_riscv64.cpp
+ RegisterInfoCommonDynamic_riscv32.cpp
LINK_COMPONENTS
Support
diff --git a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_arm.cpp b/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_arm.cpp
index 684176bccdf0c1..e2b3ae899ba400 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_arm.cpp
+++ b/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_arm.cpp
@@ -27,21 +27,21 @@ using namespace lldb_private;
bool RegisterContextPOSIX_arm::IsGPR(unsigned reg) {
if (m_register_info_up->GetRegisterSetFromRegisterIndex(reg) ==
- RegisterInfoPOSIX_arm::GPRegSet)
+ RegisterInfoCommon_arm::GPRegSet)
return true;
return false;
}
bool RegisterContextPOSIX_arm::IsFPR(unsigned reg) {
if (m_register_info_up->GetRegisterSetFromRegisterIndex(reg) ==
- RegisterInfoPOSIX_arm::FPRegSet)
+ RegisterInfoCommon_arm::FPRegSet)
return true;
return false;
}
RegisterContextPOSIX_arm::RegisterContextPOSIX_arm(
lldb_private::Thread &thread,
- std::unique_ptr<RegisterInfoPOSIX_arm> register_info)
+ std::unique_ptr<RegisterInfoCommon_arm> register_info)
: lldb_private::RegisterContext(thread, 0),
m_register_info_up(std::move(register_info)) {}
diff --git a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_arm.h b/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_arm.h
index 099c37d46f4965..4b21cfbb93d904 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_arm.h
+++ b/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_arm.h
@@ -10,7 +10,7 @@
#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTPOSIX_ARM_H
#include "RegisterInfoInterface.h"
-#include "RegisterInfoPOSIX_arm.h"
+#include "RegisterInfoCommon_arm.h"
#include "lldb/Target/RegisterContext.h"
#include "lldb/Utility/Log.h"
@@ -18,7 +18,7 @@ class RegisterContextPOSIX_arm : public lldb_private::RegisterContext {
public:
RegisterContextPOSIX_arm(
lldb_private::Thread &thread,
- std::unique_ptr<RegisterInfoPOSIX_arm> register_info);
+ std::unique_ptr<RegisterInfoCommon_arm> register_info);
~RegisterContextPOSIX_arm() override;
@@ -43,7 +43,7 @@ class RegisterContextPOSIX_arm : public lldb_private::RegisterContext {
const char *GetRegisterName(unsigned reg);
protected:
- std::unique_ptr<RegisterInfoPOSIX_arm> m_register_info_up;
+ std::unique_ptr<RegisterInfoCommon_arm> m_register_info_up;
virtual const lldb_private::RegisterInfo *GetRegisterInfo();
@@ -51,7 +51,7 @@ class RegisterContextPOSIX_arm : public lldb_private::RegisterContext {
bool IsFPR(unsigned reg);
- size_t GetFPUSize() { return sizeof(RegisterInfoPOSIX_arm::FPU); }
+ size_t GetFPUSize() { return sizeof(RegisterInfoCommon_arm::FPU); }
virtual bool ReadGPR() = 0;
virtual bool ReadFPR() = 0;
diff --git a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_arm64.cpp b/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_arm64.cpp
index ecff3bfd6c8987..efc7b705c7ca0d 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_arm64.cpp
+++ b/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_arm64.cpp
@@ -27,14 +27,14 @@ using namespace lldb_private;
bool RegisterContextPOSIX_arm64::IsGPR(unsigned reg) {
if (m_register_info_up->GetRegisterSetFromRegisterIndex(reg) ==
- RegisterInfoPOSIX_arm64::GPRegSet)
+ RegisterInfoCommon_arm64::GPRegSet)
return true;
return false;
}
bool RegisterContextPOSIX_arm64::IsFPR(unsigned reg) {
if (m_register_info_up->GetRegisterSetFromRegisterIndex(reg) ==
- RegisterInfoPOSIX_arm64::FPRegSet)
+ RegisterInfoCommon_arm64::FPRegSet)
return true;
return false;
}
@@ -73,7 +73,7 @@ bool RegisterContextPOSIX_arm64::IsPOE(unsigned reg) const {
RegisterContextPOSIX_arm64::RegisterContextPOSIX_arm64(
lldb_private::Thread &thread,
- std::unique_ptr<RegisterInfoPOSIX_arm64> register_info)
+ std::unique_ptr<RegisterInfoCommon_arm64> register_info)
: lldb_private::RegisterContext(thread, 0),
m_register_info_up(std::move(register_info)) {}
diff --git a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_arm64.h b/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_arm64.h
index eba02cdd136995..6137030a577116 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_arm64.h
+++ b/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_arm64.h
@@ -10,7 +10,7 @@
#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTPOSIX_ARM64_H
#include "RegisterInfoInterface.h"
-#include "RegisterInfoPOSIX_arm64.h"
+#include "RegisterInfoCommon_arm64.h"
#include "lldb/Target/RegisterContext.h"
#include "lldb/Utility/Log.h"
@@ -18,7 +18,7 @@ class RegisterContextPOSIX_arm64 : public lldb_private::RegisterContext {
public:
RegisterContextPOSIX_arm64(
lldb_private::Thread &thread,
- std::unique_ptr<RegisterInfoPOSIX_arm64> register_info);
+ std::unique_ptr<RegisterInfoCommon_arm64> register_info);
~RegisterContextPOSIX_arm64() override;
@@ -43,7 +43,7 @@ class RegisterContextPOSIX_arm64 : public lldb_private::RegisterContext {
const char *GetRegisterName(unsigned reg);
protected:
- std::unique_ptr<RegisterInfoPOSIX_arm64> m_register_info_up;
+ std::unique_ptr<RegisterInfoCommon_arm64> m_register_info_up;
virtual const lldb_private::RegisterInfo *GetRegisterInfo();
@@ -51,7 +51,7 @@ class RegisterContextPOSIX_arm64 : public lldb_private::RegisterContext {
bool IsFPR(unsigned reg);
- size_t GetFPUSize() { return sizeof(RegisterInfoPOSIX_arm64::FPU); }
+ size_t GetFPUSize() { return sizeof(RegisterInfoCommon_arm64::FPU); }
bool IsSVE(unsigned reg) const;
bool IsPAuth(unsigned reg) const;
diff --git a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_loongarch64.cpp b/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_loongarch64.cpp
index 3306fb20dae9b8..d60f79b6b8f6ed 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_loongarch64.cpp
+++ b/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_loongarch64.cpp
@@ -23,7 +23,7 @@ using namespace lldb_private;
RegisterContextPOSIX_loongarch64::RegisterContextPOSIX_loongarch64(
lldb_private::Thread &thread,
- std::unique_ptr<RegisterInfoPOSIX_loongarch64> register_info)
+ std::unique_ptr<RegisterInfoCommon_loongarch64> register_info)
: lldb_private::RegisterContext(thread, 0),
m_register_info_up(std::move(register_info)) {}
@@ -73,20 +73,20 @@ RegisterContextPOSIX_loongarch64::GetRegisterInfo() {
bool RegisterContextPOSIX_loongarch64::IsGPR(unsigned int reg) {
return m_register_info_up->GetRegisterSetFromRegisterIndex(reg) ==
- RegisterInfoPOSIX_loongarch64::GPRegSet;
+ RegisterInfoCommon_loongarch64::GPRegSet;
}
bool RegisterContextPOSIX_loongarch64::IsFPR(unsigned int reg) {
return m_register_info_up->GetRegisterSetFromRegisterIndex(reg) ==
- RegisterInfoPOSIX_loongarch64::FPRegSet;
+ RegisterInfoCommon_loongarch64::FPRegSet;
}
bool RegisterContextPOSIX_loongarch64::IsLSX(unsigned int reg) {
return m_register_info_up->GetRegisterSetFromRegisterIndex(reg) ==
- RegisterInfoPOSIX_loongarch64::LSXRegSet;
+ RegisterInfoCommon_loongarch64::LSXRegSet;
}
bool RegisterContextPOSIX_loongarch64::IsLASX(unsigned int reg) {
return m_register_info_up->GetRegisterSetFromRegisterIndex(reg) ==
- RegisterInfoPOSIX_loongarch64::LASXRegSet;
+ RegisterInfoCommon_loongarch64::LASXRegSet;
}
diff --git a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_loongarch64.h b/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_loongarch64.h
index dca24e4b585bf4..7f63a6e95d9ab4 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_loongarch64.h
+++ b/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_loongarch64.h
@@ -10,7 +10,7 @@
#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTPOSIX_LOONGARCH64_H
#include "RegisterInfoInterface.h"
-#include "RegisterInfoPOSIX_loongarch64.h"
+#include "RegisterInfoCommon_loongarch64.h"
#include "lldb-loongarch-register-enums.h"
#include "lldb/Target/RegisterContext.h"
#include "lldb/Utility/Log.h"
@@ -19,7 +19,7 @@ class RegisterContextPOSIX_loongarch64 : public lldb_private::RegisterContext {
public:
RegisterContextPOSIX_loongarch64(
lldb_private::Thread &thread,
- std::unique_ptr<RegisterInfoPOSIX_loongarch64> register_info);
+ std::unique_ptr<RegisterInfoCommon_loongarch64> register_info);
~RegisterContextPOSIX_loongarch64() override;
@@ -42,7 +42,7 @@ class RegisterContextPOSIX_loongarch64 : public lldb_private::RegisterContext {
const lldb_private::RegisterSet *GetRegisterSet(size_t set) override;
protected:
- std::unique_ptr<RegisterInfoPOSIX_loongarch64> m_register_info_up;
+ std::unique_ptr<RegisterInfoCommon_loongarch64> m_register_info_up;
virtual const lldb_private::RegisterInfo *GetRegisterInfo();
@@ -54,7 +54,7 @@ class RegisterContextPOSIX_loongarch64 : public lldb_private::RegisterContext {
bool IsLASX(unsigned reg);
- size_t GetFPRSize() { return sizeof(RegisterInfoPOSIX_loongarch64::FPR); }
+ size_t GetFPRSize() { return sizeof(RegisterInfoCommon_loongarch64::FPR); }
uint32_t GetRegNumFCSR() const { return fpr_fcsr_loongarch; }
diff --git a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_riscv32.cpp b/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_riscv32.cpp
index 64064f86cea046..1a0b0b9aaad39d 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_riscv32.cpp
+++ b/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_riscv32.cpp
@@ -22,7 +22,7 @@ using namespace lldb_private;
RegisterContextPOSIX_riscv32::RegisterContextPOSIX_riscv32(
lldb_private::Thread &thread,
- std::unique_ptr<RegisterInfoPOSIX_riscv32> register_info)
+ std::unique_ptr<RegisterInfoCommon_riscv32> register_info)
: lldb_private::RegisterContext(thread, 0),
m_register_info_up(std::move(register_info)) {}
@@ -72,10 +72,10 @@ RegisterContextPOSIX_riscv32::GetRegisterInfo() {
bool RegisterContextPOSIX_riscv32::IsGPR(unsigned int reg) {
return m_register_info_up->GetRegisterSetFromRegisterIndex(reg) ==
- RegisterInfoPOSIX_riscv32::eRegsetMaskDefault;
+ RegisterInfoCommon_riscv32::eRegsetMaskDefault;
}
bool RegisterContextPOSIX_riscv32::IsFPR(unsigned int reg) {
return m_register_info_up->GetRegisterSetFromRegisterIndex(reg) ==
- RegisterInfoPOSIX_riscv32::eRegsetMaskFP;
+ RegisterInfoCommon_riscv32::eRegsetMaskFP;
}
diff --git a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_riscv32.h b/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_riscv32.h
index 0c25ce11f5754c..3fa948f0f82212 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_riscv32.h
+++ b/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_riscv32.h
@@ -10,7 +10,7 @@
#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTPOSIX_RISCV32_H
#include "RegisterInfoInterface.h"
-#include "RegisterInfoPOSIX_riscv32.h"
+#include "RegisterInfoCommon_riscv32.h"
#include "lldb-riscv-register-enums.h"
#include "lldb/Target/RegisterContext.h"
#include "lldb/Utility/Log.h"
@@ -19,7 +19,7 @@ class RegisterContextPOSIX_riscv32 : public lldb_private::RegisterContext {
public:
RegisterContextPOSIX_riscv32(
lldb_private::Thread &thread,
- std::unique_ptr<RegisterInfoPOSIX_riscv32> register_info);
+ std::unique_ptr<RegisterInfoCommon_riscv32> register_info);
~RegisterContextPOSIX_riscv32() override;
@@ -42,7 +42,7 @@ class RegisterContextPOSIX_riscv32 : public lldb_private::RegisterContext {
const lldb_private::RegisterSet *GetRegisterSet(size_t set) override;
protected:
- std::unique_ptr<RegisterInfoPOSIX_riscv32> m_register_info_up;
+ std::unique_ptr<RegisterInfoCommon_riscv32> m_register_info_up;
virtual const lldb_private::RegisterInfo *GetRegisterInfo();
@@ -50,7 +50,7 @@ class RegisterContextPOSIX_riscv32 : public lldb_private::RegisterContext {
bool IsFPR(unsigned reg);
- size_t GetFPRSize() { return sizeof(RegisterInfoPOSIX_riscv32::FPR); }
+ size_t GetFPRSize() { return sizeof(RegisterInfoCommon_riscv32::FPR); }
uint32_t GetRegNumFCSR() const { return fpr_fcsr_riscv; }
diff --git a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_riscv64.cpp b/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_riscv64.cpp
index bbcfb9eae10034..c69b7e02b45ba6 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_riscv64.cpp
+++ b/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_riscv64.cpp
@@ -23,7 +23,7 @@ using namespace lldb_private;
RegisterContextPOSIX_riscv64::RegisterContextPOSIX_riscv64(
lldb_private::Thread &thread,
- std::unique_ptr<RegisterInfoPOSIX_riscv64> register_info)
+ std::unique_ptr<RegisterInfoCommon_riscv64> register_info)
: lldb_private::RegisterContext(thread, 0),
m_register_info_up(std::move(register_info)) {}
@@ -73,7 +73,7 @@ RegisterContextPOSIX_riscv64::GetRegisterInfo() {
bool RegisterContextPOSIX_riscv64::IsGPR(unsigned int reg) {
return m_register_info_up->GetRegisterSetFromRegisterIndex(reg) ==
- RegisterInfoPOSIX_riscv64::GPRegSet;
+ RegisterInfoCommon_riscv64::GPRegSet;
}
bool RegisterContextPOSIX_riscv64::IsFPR(unsigned int reg) {
diff --git a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_riscv64.h b/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_riscv64.h
index 2431ed6ab8c6db..417bb4f808f035 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_riscv64.h
+++ b/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_riscv64.h
@@ -10,7 +10,7 @@
#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTPOSIX_RISCV64_H
#include "RegisterInfoInterface.h"
-#include "RegisterInfoPOSIX_riscv64.h"
+#include "RegisterInfoCommon_riscv64.h"
#include "lldb-riscv-register-enums.h"
#include "lldb/Target/RegisterContext.h"
#include "lldb/Utility/Log.h"
@@ -19,7 +19,7 @@ class RegisterContextPOSIX_riscv64 : public lldb_private::RegisterContext {
public:
RegisterContextPOSIX_riscv64(
lldb_private::Thread &thread,
- std::unique_ptr<RegisterInfoPOSIX_riscv64> register_info);
+ std::unique_ptr<RegisterInfoCommon_riscv64> register_info);
~RegisterContextPOSIX_riscv64() override;
@@ -42,7 +42,7 @@ class RegisterContextPOSIX_riscv64 : public lldb_private::RegisterContext {
const lldb_private::RegisterSet *GetRegisterSet(size_t set) override;
protected:
- std::unique_ptr<RegisterInfoPOSIX_riscv64> m_register_info_up;
+ std::unique_ptr<RegisterInfoCommon_riscv64> m_register_info_up;
virtual const lldb_private::RegisterInfo *GetRegisterInfo();
@@ -50,7 +50,7 @@ class RegisterContextPOSIX_riscv64 : public lldb_private::RegisterContext {
bool IsFPR(unsigned reg);
- size_t GetFPRSize() { return sizeof(RegisterInfoPOSIX_riscv64::FPR); }
+ size_t GetFPRSize() { return sizeof(RegisterInfoCommon_riscv64::FPR); }
uint32_t GetRegNumFCSR() const { return fpr_fcsr_riscv; }
diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIXDynamic_riscv32.cpp b/lldb/source/Plugins/Process/Utility/RegisterInfoCommonDynamic_riscv32.cpp
similarity index 85%
rename from lldb/source/Plugins/Process/Utility/RegisterInfoPOSIXDynamic_riscv32.cpp
rename to lldb/source/Plugins/Process/Utility/RegisterInfoCommonDynamic_riscv32.cpp
index 673e3d42fd491f..0fc22c04d26db8 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIXDynamic_riscv32.cpp
+++ b/lldb/source/Plugins/Process/Utility/RegisterInfoCommonDynamic_riscv32.cpp
@@ -6,7 +6,7 @@
//
//===----------------------------------------------------------------------===//
-#include "RegisterInfoPOSIXDynamic_riscv32.h"
+#include "RegisterInfoCommonDynamic_riscv32.h"
#include "lldb-riscv-register-enums.h"
#include "lldb/lldb-defines.h"
@@ -22,16 +22,16 @@
#include "Plugins/Process/Utility/RegisterInfos_riscv32.h"
#undef DECLARE_REGISTER_INFOS_RISCV32_STRUCT
-RegisterInfoPOSIXDynamic_riscv32::RegisterInfoPOSIXDynamic_riscv32(
+RegisterInfoCommonDynamic_riscv32::RegisterInfoCommonDynamic_riscv32(
const lldb_private::ArchSpec &target_arch)
: lldb_private::RegisterInfoAndSetInterface(target_arch),
m_target_arch(target_arch) {}
-uint32_t RegisterInfoPOSIXDynamic_riscv32::GetRegisterCount() const {
+uint32_t RegisterInfoCommonDynamic_riscv32::GetRegisterCount() const {
return m_dyn_reg_infos.GetNumRegisters();
}
-size_t RegisterInfoPOSIXDynamic_riscv32::GetGPRSize() const {
+size_t RegisterInfoCommonDynamic_riscv32::GetGPRSize() const {
for (uint32_t set_idx = 0; set_idx < GetRegisterSetCount(); ++set_idx) {
const lldb_private::RegisterSet *set =
m_dyn_reg_infos.GetRegisterSet(set_idx);
@@ -41,7 +41,7 @@ size_t RegisterInfoPOSIXDynamic_riscv32::GetGPRSize() const {
return 0;
}
-size_t RegisterInfoPOSIXDynamic_riscv32::GetFPRSize() const {
+size_t RegisterInfoCommonDynamic_riscv32::GetFPRSize() const {
for (uint32_t set_idx = 0; set_idx < GetRegisterSetCount(); ++set_idx) {
const lldb_private::RegisterSet *set =
m_dyn_reg_infos.GetRegisterSet(set_idx);
@@ -52,18 +52,18 @@ size_t RegisterInfoPOSIXDynamic_riscv32::GetFPRSize() const {
}
const lldb_private::RegisterInfo *
-RegisterInfoPOSIXDynamic_riscv32::GetRegisterInfo() const {
+RegisterInfoCommonDynamic_riscv32::GetRegisterInfo() const {
return &*m_dyn_reg_infos
.registers<lldb_private::DynamicRegisterInfo::
reg_collection_const_range>()
.begin();
}
-size_t RegisterInfoPOSIXDynamic_riscv32::GetRegisterSetCount() const {
+size_t RegisterInfoCommonDynamic_riscv32::GetRegisterSetCount() const {
return m_dyn_reg_infos.GetNumRegisterSets();
}
-size_t RegisterInfoPOSIXDynamic_riscv32::GetRegisterSetFromRegisterIndex(
+size_t RegisterInfoCommonDynamic_riscv32::GetRegisterSetFromRegisterIndex(
uint32_t reg_index) const {
for (size_t set_index = 0; set_index < m_dyn_reg_infos.GetNumRegisterSets();
++set_index) {
@@ -77,24 +77,24 @@ size_t RegisterInfoPOSIXDynamic_riscv32::GetRegisterSetFromRegisterIndex(
}
const lldb_private::RegisterSet *
-RegisterInfoPOSIXDynamic_riscv32::GetRegisterSet(size_t set_index) const {
+RegisterInfoCommonDynamic_riscv32::GetRegisterSet(size_t set_index) const {
if (set_index < GetRegisterSetCount())
return m_dyn_reg_infos.GetRegisterSet(set_index);
return nullptr;
}
-size_t RegisterInfoPOSIXDynamic_riscv32::SetRegisterInfo(
+size_t RegisterInfoCommonDynamic_riscv32::SetRegisterInfo(
std::vector<lldb_private::DynamicRegisterInfo::Register> regs) {
return m_dyn_reg_infos.SetRegisterInfo(std::move(regs), m_target_arch);
}
const lldb_private::RegisterInfo *
-RegisterInfoPOSIXDynamic_riscv32::GetRegisterInfo(
+RegisterInfoCommonDynamic_riscv32::GetRegisterInfo(
llvm::StringRef reg_name) const {
return m_dyn_reg_infos.GetRegisterInfo(reg_name);
}
-void RegisterInfoPOSIXDynamic_riscv32::BuildCSRegInfos(
+void RegisterInfoCommonDynamic_riscv32::BuildCSRegInfos(
llvm::ArrayRef<std::string> features,
llvm::SmallVectorImpl<lldb_private::RegisterInfo> &cs_reg_infos) {
cs_reg_infos.clear();
@@ -143,7 +143,7 @@ void RegisterInfoPOSIXDynamic_riscv32::BuildCSRegInfos(
ConfigureCSRegInfos(feature, cs_reg_infos);
}
-void RegisterInfoPOSIXDynamic_riscv32::ConfigureCSRegInfos(
+void RegisterInfoCommonDynamic_riscv32::ConfigureCSRegInfos(
llvm::StringRef feature,
llvm::SmallVectorImpl<lldb_private::RegisterInfo> &cs_reg_infos) {
// Initialized on first use so that the patch set does not depend on the
@@ -151,6 +151,7 @@ void RegisterInfoPOSIXDynamic_riscv32::ConfigureCSRegInfos(
static const llvm::StringMap<llvm::ArrayRef<lldb_private::RegisterInfo>>
g_register_infos_riscv32_csr_patches = {
{"default", llvm::ArrayRef(g_register_infos_riscv32_csr_patch)},
+ {"xqci", llvm::ArrayRef(g_register_infos_riscv32_csr_xqci_patch)},
{"xqciint",
llvm::ArrayRef(g_register_infos_riscv32_csr_xqciint_patch)}};
diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIXDynamic_riscv32.h b/lldb/source/Plugins/Process/Utility/RegisterInfoCommonDynamic_riscv32.h
similarity index 86%
rename from lldb/source/Plugins/Process/Utility/RegisterInfoPOSIXDynamic_riscv32.h
rename to lldb/source/Plugins/Process/Utility/RegisterInfoCommonDynamic_riscv32.h
index adbe318178a669..c02662de68dd2c 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIXDynamic_riscv32.h
+++ b/lldb/source/Plugins/Process/Utility/RegisterInfoCommonDynamic_riscv32.h
@@ -6,8 +6,8 @@
//
//===----------------------------------------------------------------------===//
-#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOPOSIXDYNAMIC_RISCV32_H
-#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOPOSIXDYNAMIC_RISCV32_H
+#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOCOMMONDYNAMIC_RISCV32_H
+#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOCOMMONDYNAMIC_RISCV32_H
#include "RegisterInfoAndSetInterface.h"
#include "lldb/Target/DynamicRegisterInfo.h"
@@ -17,10 +17,10 @@
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringRef.h"
-class RegisterInfoPOSIXDynamic_riscv32
+class RegisterInfoCommonDynamic_riscv32
: public lldb_private::RegisterInfoAndSetInterface {
public:
- RegisterInfoPOSIXDynamic_riscv32(const lldb_private::ArchSpec &target_arch);
+ RegisterInfoCommonDynamic_riscv32(const lldb_private::ArchSpec &target_arch);
size_t GetGPRSize() const override;
@@ -67,4 +67,4 @@ class RegisterInfoPOSIXDynamic_riscv32
llvm::SmallVectorImpl<lldb_private::RegisterInfo> &cs_reg_infos);
};
-#endif // LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOPOSIXDYNAMIC_RISCV32_H
+#endif // LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOCOMMONDYNAMIC_RISCV32_H
diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm.cpp b/lldb/source/Plugins/Process/Utility/RegisterInfoCommon_arm.cpp
similarity index 79%
rename from lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm.cpp
rename to lldb/source/Plugins/Process/Utility/RegisterInfoCommon_arm.cpp
index 021ea56325e779..9cc43bb384984b 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm.cpp
+++ b/lldb/source/Plugins/Process/Utility/RegisterInfoCommon_arm.cpp
@@ -1,10 +1,10 @@
-//===-- RegisterInfoPOSIX_arm.cpp -----------------------------------------===//
+//===----------------------------------------------------------------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
#include <cassert>
#include <cstddef>
@@ -13,37 +13,37 @@
#include "lldb/lldb-defines.h"
#include "llvm/Support/Compiler.h"
-#include "RegisterInfoPOSIX_arm.h"
+#include "RegisterInfoCommon_arm.h"
using namespace lldb;
using namespace lldb_private;
// Based on RegisterContextDarwin_arm.cpp
#define GPR_OFFSET(idx) ((idx)*4)
-#define FPU_OFFSET(idx) ((idx)*4 + sizeof(RegisterInfoPOSIX_arm::GPR))
+#define FPU_OFFSET(idx) ((idx)*4 + sizeof(RegisterInfoCommon_arm::GPR))
#define FPSCR_OFFSET \
- (LLVM_EXTENSION offsetof(RegisterInfoPOSIX_arm::FPU, fpscr) + \
- sizeof(RegisterInfoPOSIX_arm::GPR))
+ (LLVM_EXTENSION offsetof(RegisterInfoCommon_arm::FPU, fpscr) + \
+ sizeof(RegisterInfoCommon_arm::GPR))
#define TLS_OFFSET \
- (sizeof(RegisterInfoPOSIX_arm::GPR) + sizeof(RegisterInfoPOSIX_arm::FPU))
+ (sizeof(RegisterInfoCommon_arm::GPR) + sizeof(RegisterInfoCommon_arm::FPU))
#define EXC_OFFSET(idx) \
- ((idx) * 4 + sizeof(RegisterInfoPOSIX_arm::GPR) + \
- sizeof(RegisterInfoPOSIX_arm::FPU) + sizeof(RegisterInfoPOSIX_arm::TLS))
+ ((idx) * 4 + sizeof(RegisterInfoCommon_arm::GPR) + \
+ sizeof(RegisterInfoCommon_arm::FPU) + sizeof(RegisterInfoCommon_arm::TLS))
#define DBG_OFFSET(reg) \
- ((LLVM_EXTENSION offsetof(RegisterInfoPOSIX_arm::DBG, reg) + \
- sizeof(RegisterInfoPOSIX_arm::GPR) + sizeof(RegisterInfoPOSIX_arm::FPU) + \
- sizeof(RegisterInfoPOSIX_arm::TLS) + sizeof(RegisterInfoPOSIX_arm::EXC)))
+ ((LLVM_EXTENSION offsetof(RegisterInfoCommon_arm::DBG, reg) + \
+ sizeof(RegisterInfoCommon_arm::GPR) + sizeof(RegisterInfoCommon_arm::FPU) + \
+ sizeof(RegisterInfoCommon_arm::TLS) + sizeof(RegisterInfoCommon_arm::EXC)))
#define DEFINE_DBG(reg, i) \
- #reg, NULL, sizeof(((RegisterInfoPOSIX_arm::DBG *) NULL)->reg[i]), \
+ #reg, NULL, sizeof(((RegisterInfoCommon_arm::DBG *) NULL)->reg[i]), \
DBG_OFFSET(reg[i]), eEncodingUint, eFormatHex, \
{LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \
LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \
dbg_##reg##i }, \
NULL, NULL, NULL,
#define REG_CONTEXT_SIZE \
- (sizeof(RegisterInfoPOSIX_arm::GPR) + sizeof(RegisterInfoPOSIX_arm::FPU) + \
- sizeof(RegisterInfoPOSIX_arm::EXC))
+ (sizeof(RegisterInfoCommon_arm::GPR) + sizeof(RegisterInfoCommon_arm::FPU) + \
+ sizeof(RegisterInfoCommon_arm::EXC))
// Include RegisterInfos_arm to declare our g_register_infos_arm structure.
#define DECLARE_REGISTER_INFOS_ARM_STRUCT
@@ -163,32 +163,32 @@ static const RegisterSet g_reg_sets_arm[k_num_register_sets_with_tls] = {
{"Thread Local Storage Registers", "tls", k_num_tls_registers,
g_tls_regnums_arm}};
-RegisterInfoPOSIX_arm::RegisterInfoPOSIX_arm(
+RegisterInfoCommon_arm::RegisterInfoCommon_arm(
const lldb_private::ArchSpec &target_arch, bool has_tls_reg)
: lldb_private::RegisterInfoAndSetInterface(target_arch),
m_register_info_p(GetRegisterInfoPtr(target_arch)),
m_register_info_count(GetRegisterInfoCount(target_arch)),
m_has_tls_reg(has_tls_reg) {}
-size_t RegisterInfoPOSIX_arm::GetGPRSize() const {
- return sizeof(struct RegisterInfoPOSIX_arm::GPR);
+size_t RegisterInfoCommon_arm::GetGPRSize() const {
+ return sizeof(struct RegisterInfoCommon_arm::GPR);
}
-size_t RegisterInfoPOSIX_arm::GetFPRSize() const {
- return sizeof(struct RegisterInfoPOSIX_arm::FPU);
+size_t RegisterInfoCommon_arm::GetFPRSize() const {
+ return sizeof(struct RegisterInfoCommon_arm::FPU);
}
const lldb_private::RegisterInfo *
-RegisterInfoPOSIX_arm::GetRegisterInfo() const {
+RegisterInfoCommon_arm::GetRegisterInfo() const {
return m_register_info_p;
}
-size_t RegisterInfoPOSIX_arm::GetRegisterSetCount() const {
+size_t RegisterInfoCommon_arm::GetRegisterSetCount() const {
return m_has_tls_reg ? k_num_register_sets_with_tls
: k_num_register_sets_without_tls;
}
-size_t RegisterInfoPOSIX_arm::GetRegisterSetFromRegisterIndex(
+size_t RegisterInfoCommon_arm::GetRegisterSetFromRegisterIndex(
uint32_t reg_index) const {
if (reg_index <= gpr_cpsr)
return GPRegSet;
@@ -200,12 +200,12 @@ size_t RegisterInfoPOSIX_arm::GetRegisterSetFromRegisterIndex(
}
const lldb_private::RegisterSet *
-RegisterInfoPOSIX_arm::GetRegisterSet(size_t set_index) const {
+RegisterInfoCommon_arm::GetRegisterSet(size_t set_index) const {
if (set_index < GetRegisterSetCount())
return &g_reg_sets_arm[set_index];
return nullptr;
}
-uint32_t RegisterInfoPOSIX_arm::GetRegisterCount() const {
+uint32_t RegisterInfoCommon_arm::GetRegisterCount() const {
return m_register_info_count;
}
diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm.h b/lldb/source/Plugins/Process/Utility/RegisterInfoCommon_arm.h
similarity index 80%
rename from lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm.h
rename to lldb/source/Plugins/Process/Utility/RegisterInfoCommon_arm.h
index 0695b0afd858ed..26e30f3aebe4c0 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm.h
+++ b/lldb/source/Plugins/Process/Utility/RegisterInfoCommon_arm.h
@@ -1,4 +1,4 @@
-//===-- RegisterInfoPOSIX_arm.h ---------------------------------*- C++ -*-===//
+//===----------------------------------------------------------------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
@@ -6,14 +6,14 @@
//
//===----------------------------------------------------------------------===//
-#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOPOSIX_ARM_H
-#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOPOSIX_ARM_H
+#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOCOMMON_ARM_H
+#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOCOMMON_ARM_H
#include "RegisterInfoAndSetInterface.h"
#include "lldb/Target/RegisterContext.h"
#include "lldb/lldb-private.h"
-class RegisterInfoPOSIX_arm : public lldb_private::RegisterInfoAndSetInterface {
+class RegisterInfoCommon_arm : public lldb_private::RegisterInfoAndSetInterface {
public:
enum { GPRegSet = 0, FPRegSet, TLSRegSet };
@@ -51,7 +51,7 @@ class RegisterInfoPOSIX_arm : public lldb_private::RegisterInfoAndSetInterface {
uint32_t wcr[16];
};
- RegisterInfoPOSIX_arm(const lldb_private::ArchSpec &target_arch,
+ RegisterInfoCommon_arm(const lldb_private::ArchSpec &target_arch,
bool has_tls_reg = false);
size_t GetGPRSize() const override;
@@ -77,4 +77,4 @@ class RegisterInfoPOSIX_arm : public lldb_private::RegisterInfoAndSetInterface {
bool m_has_tls_reg;
};
-#endif // LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOPOSIX_ARM_H
+#endif // LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOCOMMON_ARM_H
diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp b/lldb/source/Plugins/Process/Utility/RegisterInfoCommon_arm64.cpp
similarity index 83%
rename from lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
rename to lldb/source/Plugins/Process/Utility/RegisterInfoCommon_arm64.cpp
index 0a6424eec0096b..62d2cdacaff13b 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.cpp
+++ b/lldb/source/Plugins/Process/Utility/RegisterInfoCommon_arm64.cpp
@@ -1,10 +1,10 @@
-//===-- RegisterInfoPOSIX_arm64.cpp ---------------------------------------===//
+//===----------------------------------------------------------------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
#include <cassert>
#include <cstddef>
@@ -13,17 +13,17 @@
#include "lldb/lldb-defines.h"
#include "llvm/Support/Compiler.h"
-#include "RegisterInfoPOSIX_arm64.h"
+#include "RegisterInfoCommon_arm64.h"
// Based on RegisterContextDarwin_arm64.cpp
#define GPR_OFFSET(idx) ((idx)*8)
#define GPR_OFFSET_NAME(reg) \
- (LLVM_EXTENSION offsetof(RegisterInfoPOSIX_arm64::GPR, reg))
+ (LLVM_EXTENSION offsetof(RegisterInfoCommon_arm64::GPR, reg))
-#define FPU_OFFSET(idx) ((idx)*16 + sizeof(RegisterInfoPOSIX_arm64::GPR))
+#define FPU_OFFSET(idx) ((idx)*16 + sizeof(RegisterInfoCommon_arm64::GPR))
#define FPU_OFFSET_NAME(reg) \
- (LLVM_EXTENSION offsetof(RegisterInfoPOSIX_arm64::FPU, reg) + \
- sizeof(RegisterInfoPOSIX_arm64::GPR))
+ (LLVM_EXTENSION offsetof(RegisterInfoCommon_arm64::FPU, reg) + \
+ sizeof(RegisterInfoCommon_arm64::GPR))
// This information is based on AArch64 with SVE architecture reference manual.
// AArch64 with SVE has 32 Z and 16 P vector registers. There is also an FFR
@@ -39,32 +39,32 @@
// vector length requires register context to update sizes of SVE Z, P and FFR.
// Also register context needs to update byte offsets of all registers affected
// by the change in vector length.
-#define SVE_REGS_DEFAULT_OFFSET_LINUX sizeof(RegisterInfoPOSIX_arm64::GPR)
+#define SVE_REGS_DEFAULT_OFFSET_LINUX sizeof(RegisterInfoCommon_arm64::GPR)
#define SVE_OFFSET_VG SVE_REGS_DEFAULT_OFFSET_LINUX
#define EXC_OFFSET_NAME(reg) \
- (LLVM_EXTENSION offsetof(RegisterInfoPOSIX_arm64::EXC, reg) + \
- sizeof(RegisterInfoPOSIX_arm64::GPR) + \
- sizeof(RegisterInfoPOSIX_arm64::FPU))
+ (LLVM_EXTENSION offsetof(RegisterInfoCommon_arm64::EXC, reg) + \
+ sizeof(RegisterInfoCommon_arm64::GPR) + \
+ sizeof(RegisterInfoCommon_arm64::FPU))
#define DBG_OFFSET_NAME(reg) \
- (LLVM_EXTENSION offsetof(RegisterInfoPOSIX_arm64::DBG, reg) + \
- sizeof(RegisterInfoPOSIX_arm64::GPR) + \
- sizeof(RegisterInfoPOSIX_arm64::FPU) + \
- sizeof(RegisterInfoPOSIX_arm64::EXC))
+ (LLVM_EXTENSION offsetof(RegisterInfoCommon_arm64::DBG, reg) + \
+ sizeof(RegisterInfoCommon_arm64::GPR) + \
+ sizeof(RegisterInfoCommon_arm64::FPU) + \
+ sizeof(RegisterInfoCommon_arm64::EXC))
#define DEFINE_DBG(reg, i) \
#reg, NULL, \
- sizeof(((RegisterInfoPOSIX_arm64::DBG *) NULL)->reg[i]), \
+ sizeof(((RegisterInfoCommon_arm64::DBG *) NULL)->reg[i]), \
DBG_OFFSET_NAME(reg[i]), lldb::eEncodingUint, lldb::eFormatHex, \
{LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \
LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \
dbg_##reg##i }, \
NULL, NULL, NULL,
#define REG_CONTEXT_SIZE \
- (sizeof(RegisterInfoPOSIX_arm64::GPR) + \
- sizeof(RegisterInfoPOSIX_arm64::FPU) + \
- sizeof(RegisterInfoPOSIX_arm64::EXC))
+ (sizeof(RegisterInfoCommon_arm64::GPR) + \
+ sizeof(RegisterInfoCommon_arm64::FPU) + \
+ sizeof(RegisterInfoCommon_arm64::EXC))
// Include RegisterInfos_arm64 to declare our g_register_infos_arm64 structure.
#define DECLARE_REGISTER_INFOS_ARM64_STRUCT
@@ -236,7 +236,7 @@ static const lldb_private::RegisterSet g_reg_set_gcs_arm64 = {
static const lldb_private::RegisterSet g_reg_set_poe_arm64 = {
"Permission Overlay Registers", "poe", k_num_poe_register, nullptr};
-RegisterInfoPOSIX_arm64::RegisterInfoPOSIX_arm64(
+RegisterInfoCommon_arm64::RegisterInfoCommon_arm64(
const lldb_private::ArchSpec &target_arch, lldb_private::Flags opt_regsets)
: lldb_private::RegisterInfoAndSetInterface(target_arch),
m_opt_regsets(opt_regsets) {
@@ -306,28 +306,28 @@ RegisterInfoPOSIX_arm64::RegisterInfoPOSIX_arm64(
}
}
-uint32_t RegisterInfoPOSIX_arm64::GetRegisterCount() const {
+uint32_t RegisterInfoCommon_arm64::GetRegisterCount() const {
return m_register_info_count;
}
-size_t RegisterInfoPOSIX_arm64::GetGPRSizeStatic() {
- return sizeof(struct RegisterInfoPOSIX_arm64::GPR);
+size_t RegisterInfoCommon_arm64::GetGPRSizeStatic() {
+ return sizeof(struct RegisterInfoCommon_arm64::GPR);
}
-size_t RegisterInfoPOSIX_arm64::GetFPRSize() const {
- return sizeof(struct RegisterInfoPOSIX_arm64::FPU);
+size_t RegisterInfoCommon_arm64::GetFPRSize() const {
+ return sizeof(struct RegisterInfoCommon_arm64::FPU);
}
const lldb_private::RegisterInfo *
-RegisterInfoPOSIX_arm64::GetRegisterInfo() const {
+RegisterInfoCommon_arm64::GetRegisterInfo() const {
return m_register_info_p;
}
-size_t RegisterInfoPOSIX_arm64::GetRegisterSetCount() const {
+size_t RegisterInfoCommon_arm64::GetRegisterSetCount() const {
return m_register_set_count;
}
-size_t RegisterInfoPOSIX_arm64::GetRegisterSetFromRegisterIndex(
+size_t RegisterInfoCommon_arm64::GetRegisterSetFromRegisterIndex(
uint32_t reg_index) const {
for (const auto ®set_range : m_per_regset_regnum_range) {
if (reg_index >= regset_range.second.first &&
@@ -338,13 +338,13 @@ size_t RegisterInfoPOSIX_arm64::GetRegisterSetFromRegisterIndex(
}
const lldb_private::RegisterSet *
-RegisterInfoPOSIX_arm64::GetRegisterSet(size_t set_index) const {
+RegisterInfoCommon_arm64::GetRegisterSet(size_t set_index) const {
if (set_index < GetRegisterSetCount())
return &m_register_set_p[set_index];
return nullptr;
}
-void RegisterInfoPOSIX_arm64::AddRegSetPAuth() {
+void RegisterInfoCommon_arm64::AddRegSetPAuth() {
uint32_t pa_regnum = m_dynamic_reg_infos.size();
for (uint32_t i = 0; i < k_num_pauth_register; i++) {
pauth_regnum_collection.push_back(pa_regnum + i);
@@ -362,7 +362,7 @@ void RegisterInfoPOSIX_arm64::AddRegSetPAuth() {
m_dynamic_reg_sets.back().registers = pauth_regnum_collection.data();
}
-void RegisterInfoPOSIX_arm64::AddRegSetMTE() {
+void RegisterInfoCommon_arm64::AddRegSetMTE() {
uint32_t mte_regnum = m_dynamic_reg_infos.size();
m_mte_regnum_collection.push_back(mte_regnum);
m_dynamic_reg_infos.push_back(g_register_infos_mte[0]);
@@ -377,7 +377,7 @@ void RegisterInfoPOSIX_arm64::AddRegSetMTE() {
m_dynamic_reg_sets.back().registers = m_mte_regnum_collection.data();
}
-void RegisterInfoPOSIX_arm64::AddRegSetTLS(bool has_tpidr2) {
+void RegisterInfoCommon_arm64::AddRegSetTLS(bool has_tpidr2) {
uint32_t tls_regnum = m_dynamic_reg_infos.size();
uint32_t num_regs = has_tpidr2 ? 2 : 1;
for (uint32_t i = 0; i < num_regs; i++) {
@@ -397,7 +397,7 @@ void RegisterInfoPOSIX_arm64::AddRegSetTLS(bool has_tpidr2) {
m_dynamic_reg_sets.back().registers = m_tls_regnum_collection.data();
}
-void RegisterInfoPOSIX_arm64::AddRegSetSME(bool has_zt) {
+void RegisterInfoCommon_arm64::AddRegSetSME(bool has_zt) {
const uint32_t first_sme_regnum = m_dynamic_reg_infos.size();
uint32_t sme_regnum = first_sme_regnum;
@@ -439,7 +439,7 @@ void RegisterInfoPOSIX_arm64::AddRegSetSME(bool has_zt) {
m_dynamic_reg_infos[GetRegNumSVEVG()].invalidate_regs = vg_invalidates;
}
-void RegisterInfoPOSIX_arm64::AddRegSetFPMR() {
+void RegisterInfoCommon_arm64::AddRegSetFPMR() {
uint32_t fpmr_regnum = m_dynamic_reg_infos.size();
m_fpmr_regnum_collection.push_back(fpmr_regnum);
m_dynamic_reg_infos.push_back(g_register_infos_fpmr[0]);
@@ -454,7 +454,7 @@ void RegisterInfoPOSIX_arm64::AddRegSetFPMR() {
m_dynamic_reg_sets.back().registers = m_fpmr_regnum_collection.data();
}
-void RegisterInfoPOSIX_arm64::AddRegSetGCS() {
+void RegisterInfoCommon_arm64::AddRegSetGCS() {
uint32_t gcs_regnum = m_dynamic_reg_infos.size();
for (uint32_t i = 0; i < k_num_gcs_register; i++) {
m_gcs_regnum_collection.push_back(gcs_regnum + i);
@@ -472,7 +472,7 @@ void RegisterInfoPOSIX_arm64::AddRegSetGCS() {
m_dynamic_reg_sets.back().registers = m_gcs_regnum_collection.data();
}
-void RegisterInfoPOSIX_arm64::AddRegSetPOE() {
+void RegisterInfoCommon_arm64::AddRegSetPOE() {
uint32_t poe_regnum = m_dynamic_reg_infos.size();
m_poe_regnum_collection.push_back(poe_regnum);
m_dynamic_reg_infos.push_back(g_register_infos_poe[0]);
@@ -487,7 +487,7 @@ void RegisterInfoPOSIX_arm64::AddRegSetPOE() {
m_dynamic_reg_sets.back().registers = m_poe_regnum_collection.data();
}
-uint32_t RegisterInfoPOSIX_arm64::ConfigureVectorLengthSVE(uint32_t sve_vq) {
+uint32_t RegisterInfoCommon_arm64::ConfigureVectorLengthSVE(uint32_t sve_vq) {
// sve_vq contains SVE Quad vector length in context of AArch64 SVE.
// SVE register infos if enabled cannot be disabled by selecting sve_vq = 0.
// Also if an invalid or previously set vector length is passed to this
@@ -551,7 +551,7 @@ uint32_t RegisterInfoPOSIX_arm64::ConfigureVectorLengthSVE(uint32_t sve_vq) {
return m_vector_reg_vq;
}
-void RegisterInfoPOSIX_arm64::ConfigureVectorLengthZA(uint32_t za_vq) {
+void RegisterInfoCommon_arm64::ConfigureVectorLengthZA(uint32_t za_vq) {
if (!VectorSizeIsValid(za_vq) || m_za_reg_vq == za_vq)
return;
@@ -565,117 +565,117 @@ void RegisterInfoPOSIX_arm64::ConfigureVectorLengthZA(uint32_t za_vq) {
(za_vq * 16) * (za_vq * 16);
}
-bool RegisterInfoPOSIX_arm64::IsSVEReg(unsigned reg) const {
+bool RegisterInfoCommon_arm64::IsSVEReg(unsigned reg) const {
if (m_vector_reg_vq > eVectorQuadwordAArch64)
return (sve_vg <= reg && reg <= sve_ffr);
else
return false;
}
-bool RegisterInfoPOSIX_arm64::IsSVEZReg(unsigned reg) const {
+bool RegisterInfoCommon_arm64::IsSVEZReg(unsigned reg) const {
return (sve_z0 <= reg && reg <= sve_z31);
}
-bool RegisterInfoPOSIX_arm64::IsSVEPReg(unsigned reg) const {
+bool RegisterInfoCommon_arm64::IsSVEPReg(unsigned reg) const {
return (sve_p0 <= reg && reg <= sve_p15);
}
-bool RegisterInfoPOSIX_arm64::IsSVERegVG(unsigned reg) const {
+bool RegisterInfoCommon_arm64::IsSVERegVG(unsigned reg) const {
return sve_vg == reg;
}
-bool RegisterInfoPOSIX_arm64::IsSVERegFFR(unsigned reg) const {
+bool RegisterInfoCommon_arm64::IsSVERegFFR(unsigned reg) const {
return sve_ffr == reg;
}
-bool RegisterInfoPOSIX_arm64::IsSMERegZA(unsigned reg) const {
+bool RegisterInfoCommon_arm64::IsSMERegZA(unsigned reg) const {
return reg == m_sme_regnum_collection[2];
}
-bool RegisterInfoPOSIX_arm64::IsSMERegZT(unsigned reg) const {
+bool RegisterInfoCommon_arm64::IsSMERegZT(unsigned reg) const {
// ZT0 is part of the SME register set only if SME2 is present.
return m_sme_regnum_collection.size() >= 4 &&
reg == m_sme_regnum_collection[3];
}
-bool RegisterInfoPOSIX_arm64::IsGPR(unsigned reg) const {
+bool RegisterInfoCommon_arm64::IsGPR(unsigned reg) const {
return GetRegisterSetFromRegisterIndex(reg) ==
- RegisterInfoPOSIX_arm64::GPRegSet;
+ RegisterInfoCommon_arm64::GPRegSet;
}
-bool RegisterInfoPOSIX_arm64::IsFPR(unsigned reg) const {
+bool RegisterInfoCommon_arm64::IsFPR(unsigned reg) const {
return GetRegisterSetFromRegisterIndex(reg) ==
- RegisterInfoPOSIX_arm64::FPRegSet;
+ RegisterInfoCommon_arm64::FPRegSet;
}
-bool RegisterInfoPOSIX_arm64::IsPAuthReg(unsigned reg) const {
+bool RegisterInfoCommon_arm64::IsPAuthReg(unsigned reg) const {
return llvm::is_contained(pauth_regnum_collection, reg);
}
-bool RegisterInfoPOSIX_arm64::IsMTEReg(unsigned reg) const {
+bool RegisterInfoCommon_arm64::IsMTEReg(unsigned reg) const {
return llvm::is_contained(m_mte_regnum_collection, reg);
}
-bool RegisterInfoPOSIX_arm64::IsTLSReg(unsigned reg) const {
+bool RegisterInfoCommon_arm64::IsTLSReg(unsigned reg) const {
return llvm::is_contained(m_tls_regnum_collection, reg);
}
-bool RegisterInfoPOSIX_arm64::IsSMEReg(unsigned reg) const {
+bool RegisterInfoCommon_arm64::IsSMEReg(unsigned reg) const {
return llvm::is_contained(m_sme_regnum_collection, reg);
}
-bool RegisterInfoPOSIX_arm64::IsFPMRReg(unsigned reg) const {
+bool RegisterInfoCommon_arm64::IsFPMRReg(unsigned reg) const {
return llvm::is_contained(m_fpmr_regnum_collection, reg);
}
-bool RegisterInfoPOSIX_arm64::IsGCSReg(unsigned reg) const {
+bool RegisterInfoCommon_arm64::IsGCSReg(unsigned reg) const {
return llvm::is_contained(m_gcs_regnum_collection, reg);
}
-bool RegisterInfoPOSIX_arm64::IsPOEReg(unsigned reg) const {
+bool RegisterInfoCommon_arm64::IsPOEReg(unsigned reg) const {
return llvm::is_contained(m_poe_regnum_collection, reg);
}
-uint32_t RegisterInfoPOSIX_arm64::GetRegNumSVEZ0() const { return sve_z0; }
+uint32_t RegisterInfoCommon_arm64::GetRegNumSVEZ0() const { return sve_z0; }
-uint32_t RegisterInfoPOSIX_arm64::GetRegNumSVEFFR() const { return sve_ffr; }
+uint32_t RegisterInfoCommon_arm64::GetRegNumSVEFFR() const { return sve_ffr; }
-uint32_t RegisterInfoPOSIX_arm64::GetRegNumFPCR() const { return fpu_fpcr; }
+uint32_t RegisterInfoCommon_arm64::GetRegNumFPCR() const { return fpu_fpcr; }
-uint32_t RegisterInfoPOSIX_arm64::GetRegNumFPSR() const { return fpu_fpsr; }
+uint32_t RegisterInfoCommon_arm64::GetRegNumFPSR() const { return fpu_fpsr; }
-uint32_t RegisterInfoPOSIX_arm64::GetRegNumFPV0() const { return fpu_v0; }
+uint32_t RegisterInfoCommon_arm64::GetRegNumFPV0() const { return fpu_v0; }
-uint32_t RegisterInfoPOSIX_arm64::GetRegNumSVEVG() const { return sve_vg; }
+uint32_t RegisterInfoCommon_arm64::GetRegNumSVEVG() const { return sve_vg; }
-uint32_t RegisterInfoPOSIX_arm64::GetRegNumSMESVG() const {
+uint32_t RegisterInfoCommon_arm64::GetRegNumSMESVG() const {
return m_sme_regnum_collection[1];
}
-uint32_t RegisterInfoPOSIX_arm64::GetPAuthOffset() const {
+uint32_t RegisterInfoCommon_arm64::GetPAuthOffset() const {
return m_register_info_p[pauth_regnum_collection[0]].byte_offset;
}
-uint32_t RegisterInfoPOSIX_arm64::GetMTEOffset() const {
+uint32_t RegisterInfoCommon_arm64::GetMTEOffset() const {
return m_register_info_p[m_mte_regnum_collection[0]].byte_offset;
}
-uint32_t RegisterInfoPOSIX_arm64::GetTLSOffset() const {
+uint32_t RegisterInfoCommon_arm64::GetTLSOffset() const {
return m_register_info_p[m_tls_regnum_collection[0]].byte_offset;
}
-uint32_t RegisterInfoPOSIX_arm64::GetSMEOffset() const {
+uint32_t RegisterInfoCommon_arm64::GetSMEOffset() const {
return m_register_info_p[m_sme_regnum_collection[0]].byte_offset;
}
-uint32_t RegisterInfoPOSIX_arm64::GetFPMROffset() const {
+uint32_t RegisterInfoCommon_arm64::GetFPMROffset() const {
return m_register_info_p[m_fpmr_regnum_collection[0]].byte_offset;
}
-uint32_t RegisterInfoPOSIX_arm64::GetGCSOffset() const {
+uint32_t RegisterInfoCommon_arm64::GetGCSOffset() const {
return m_register_info_p[m_gcs_regnum_collection[0]].byte_offset;
}
-uint32_t RegisterInfoPOSIX_arm64::GetPOEOffset() const {
+uint32_t RegisterInfoCommon_arm64::GetPOEOffset() const {
return m_register_info_p[m_poe_regnum_collection[0]].byte_offset;
}
diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h b/lldb/source/Plugins/Process/Utility/RegisterInfoCommon_arm64.h
similarity index 95%
rename from lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h
rename to lldb/source/Plugins/Process/Utility/RegisterInfoCommon_arm64.h
index 378ea3f524f6c6..837cfb187cddc7 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h
+++ b/lldb/source/Plugins/Process/Utility/RegisterInfoCommon_arm64.h
@@ -1,4 +1,4 @@
-//===-- RegisterInfoPOSIX_arm64.h -------------------------------*- C++ -*-===//
+//===----------------------------------------------------------------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
@@ -6,8 +6,8 @@
//
//===----------------------------------------------------------------------===//
-#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOPOSIX_ARM64_H
-#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOPOSIX_ARM64_H
+#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOCOMMON_ARM64_H
+#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOCOMMON_ARM64_H
#include "RegisterInfoAndSetInterface.h"
#include "lldb/Target/RegisterContext.h"
@@ -30,7 +30,7 @@ enum class SVEState : uint8_t {
StreamingFPSIMD
};
-class RegisterInfoPOSIX_arm64
+class RegisterInfoCommon_arm64
: public lldb_private::RegisterInfoAndSetInterface {
public:
enum { GPRegSet = 0, FPRegSet };
@@ -101,7 +101,7 @@ class RegisterInfoPOSIX_arm64
uint64_t mdscr_el1;
};
- RegisterInfoPOSIX_arm64(const lldb_private::ArchSpec &target_arch,
+ RegisterInfoCommon_arm64(const lldb_private::ArchSpec &target_arch,
lldb_private::Flags opt_regsets);
static size_t GetGPRSizeStatic();
diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_loongarch64.cpp b/lldb/source/Plugins/Process/Utility/RegisterInfoCommon_loongarch64.cpp
similarity index 82%
rename from lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_loongarch64.cpp
rename to lldb/source/Plugins/Process/Utility/RegisterInfoCommon_loongarch64.cpp
index 61cd40ddcfc841..8d496bfbd64a5f 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_loongarch64.cpp
+++ b/lldb/source/Plugins/Process/Utility/RegisterInfoCommon_loongarch64.cpp
@@ -1,10 +1,10 @@
-//===-- RegisterInfoPOSIX_loongarch64.cpp --------------------------------===//
+//===----------------------------------------------------------------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
#include <cassert>
#include <lldb/Utility/Flags.h>
@@ -13,32 +13,32 @@
#include "lldb/lldb-defines.h"
#include "llvm/Support/Compiler.h"
-#include "RegisterInfoPOSIX_loongarch64.h"
+#include "RegisterInfoCommon_loongarch64.h"
#define GPR_OFFSET(idx) ((idx)*8 + 0)
-#define FPR_OFFSET(idx) ((idx)*8 + sizeof(RegisterInfoPOSIX_loongarch64::GPR))
-#define FCC_OFFSET(idx) ((idx)*1 + 32 * 8 + sizeof(RegisterInfoPOSIX_loongarch64::GPR))
-#define FCSR_OFFSET (8 * 1 + 32 * 8 + sizeof(RegisterInfoPOSIX_loongarch64::GPR))
+#define FPR_OFFSET(idx) ((idx)*8 + sizeof(RegisterInfoCommon_loongarch64::GPR))
+#define FCC_OFFSET(idx) ((idx)*1 + 32 * 8 + sizeof(RegisterInfoCommon_loongarch64::GPR))
+#define FCSR_OFFSET (8 * 1 + 32 * 8 + sizeof(RegisterInfoCommon_loongarch64::GPR))
#define LSX_OFFSET(idx) \
- ((idx) * 16 + sizeof(RegisterInfoPOSIX_loongarch64::GPR) + \
- sizeof(RegisterInfoPOSIX_loongarch64::FPR))
+ ((idx) * 16 + sizeof(RegisterInfoCommon_loongarch64::GPR) + \
+ sizeof(RegisterInfoCommon_loongarch64::FPR))
#define LASX_OFFSET(idx) \
- ((idx) * 32 + sizeof(RegisterInfoPOSIX_loongarch64::GPR) + \
- sizeof(RegisterInfoPOSIX_loongarch64::FPR) + \
- sizeof(RegisterInfoPOSIX_loongarch64::LSX))
+ ((idx) * 32 + sizeof(RegisterInfoCommon_loongarch64::GPR) + \
+ sizeof(RegisterInfoCommon_loongarch64::FPR) + \
+ sizeof(RegisterInfoCommon_loongarch64::LSX))
#define REG_CONTEXT_SIZE \
- (sizeof(RegisterInfoPOSIX_loongarch64::GPR) + \
- sizeof(RegisterInfoPOSIX_loongarch64::FPR) + \
- sizeof(RegisterInfoPOSIX_loongarch64::LSX) + \
- sizeof(RegisterInfoPOSIX_loongarch64::LASX))
+ (sizeof(RegisterInfoCommon_loongarch64::GPR) + \
+ sizeof(RegisterInfoCommon_loongarch64::FPR) + \
+ sizeof(RegisterInfoCommon_loongarch64::LSX) + \
+ sizeof(RegisterInfoCommon_loongarch64::LASX))
#define DECLARE_REGISTER_INFOS_LOONGARCH64_STRUCT
#include "RegisterInfos_loongarch64.h"
#undef DECLARE_REGISTER_INFOS_LOONGARCH64_STRUCT
const lldb_private::RegisterInfo *
-RegisterInfoPOSIX_loongarch64::GetRegisterInfoPtr(
+RegisterInfoCommon_loongarch64::GetRegisterInfoPtr(
const lldb_private::ArchSpec &target_arch) {
switch (target_arch.GetMachine()) {
case llvm::Triple::loongarch64:
@@ -49,7 +49,7 @@ RegisterInfoPOSIX_loongarch64::GetRegisterInfoPtr(
}
}
-uint32_t RegisterInfoPOSIX_loongarch64::GetRegisterInfoCount(
+uint32_t RegisterInfoCommon_loongarch64::GetRegisterInfoCount(
const lldb_private::ArchSpec &target_arch) {
switch (target_arch.GetMachine()) {
case llvm::Triple::loongarch64:
@@ -166,34 +166,34 @@ static const lldb_private::RegisterSet
{"LASX Vector Registers", "lasx", k_num_lasx_registers,
g_lasx_regnums_loongarch64}};
-RegisterInfoPOSIX_loongarch64::RegisterInfoPOSIX_loongarch64(
+RegisterInfoCommon_loongarch64::RegisterInfoCommon_loongarch64(
const lldb_private::ArchSpec &target_arch, lldb_private::Flags flags)
: lldb_private::RegisterInfoAndSetInterface(target_arch),
m_register_info_p(GetRegisterInfoPtr(target_arch)),
m_register_info_count(GetRegisterInfoCount(target_arch)) {}
-uint32_t RegisterInfoPOSIX_loongarch64::GetRegisterCount() const {
+uint32_t RegisterInfoCommon_loongarch64::GetRegisterCount() const {
return m_register_info_count;
}
-size_t RegisterInfoPOSIX_loongarch64::GetGPRSize() const {
- return sizeof(struct RegisterInfoPOSIX_loongarch64::GPR);
+size_t RegisterInfoCommon_loongarch64::GetGPRSize() const {
+ return sizeof(struct RegisterInfoCommon_loongarch64::GPR);
}
-size_t RegisterInfoPOSIX_loongarch64::GetFPRSize() const {
- return sizeof(struct RegisterInfoPOSIX_loongarch64::FPR);
+size_t RegisterInfoCommon_loongarch64::GetFPRSize() const {
+ return sizeof(struct RegisterInfoCommon_loongarch64::FPR);
}
const lldb_private::RegisterInfo *
-RegisterInfoPOSIX_loongarch64::GetRegisterInfo() const {
+RegisterInfoCommon_loongarch64::GetRegisterInfo() const {
return m_register_info_p;
}
-size_t RegisterInfoPOSIX_loongarch64::GetRegisterSetCount() const {
+size_t RegisterInfoCommon_loongarch64::GetRegisterSetCount() const {
return k_num_register_sets;
}
-size_t RegisterInfoPOSIX_loongarch64::GetRegisterSetFromRegisterIndex(
+size_t RegisterInfoCommon_loongarch64::GetRegisterSetFromRegisterIndex(
uint32_t reg_index) const {
// coverity[unsigned_compare]
if (reg_index >= gpr_first_loongarch && reg_index <= gpr_last_loongarch)
@@ -208,7 +208,7 @@ size_t RegisterInfoPOSIX_loongarch64::GetRegisterSetFromRegisterIndex(
}
const lldb_private::RegisterSet *
-RegisterInfoPOSIX_loongarch64::GetRegisterSet(size_t set_index) const {
+RegisterInfoCommon_loongarch64::GetRegisterSet(size_t set_index) const {
if (set_index < GetRegisterSetCount())
return &g_reg_sets_loongarch64[set_index];
return nullptr;
diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_loongarch64.h b/lldb/source/Plugins/Process/Utility/RegisterInfoCommon_loongarch64.h
similarity index 83%
rename from lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_loongarch64.h
rename to lldb/source/Plugins/Process/Utility/RegisterInfoCommon_loongarch64.h
index 0ff08bb8c0e92a..07a6c6c627cb84 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_loongarch64.h
+++ b/lldb/source/Plugins/Process/Utility/RegisterInfoCommon_loongarch64.h
@@ -1,4 +1,4 @@
-//===-- RegisterInfoPOSIX_loongarch64.h -------------------------*- C++ -*-===//
+//===----------------------------------------------------------------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
@@ -6,15 +6,15 @@
//
//===----------------------------------------------------------------------===//
-#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOPOSIX_LOONGARCH64_H
-#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOPOSIX_LOONGARCH64_H
+#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOCOMMON_LOONGARCH64_H
+#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOCOMMON_LOONGARCH64_H
#include "RegisterInfoAndSetInterface.h"
#include "lldb/Target/RegisterContext.h"
#include "lldb/lldb-private.h"
#include <map>
-class RegisterInfoPOSIX_loongarch64
+class RegisterInfoCommon_loongarch64
: public lldb_private::RegisterInfoAndSetInterface {
public:
static const lldb_private::RegisterInfo *
@@ -55,7 +55,7 @@ class RegisterInfoPOSIX_loongarch64
uint64_t xr[32 * 4];
};
- RegisterInfoPOSIX_loongarch64(const lldb_private::ArchSpec &target_arch,
+ RegisterInfoCommon_loongarch64(const lldb_private::ArchSpec &target_arch,
lldb_private::Flags flags);
size_t GetGPRSize() const override;
diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_ppc64.cpp b/lldb/source/Plugins/Process/Utility/RegisterInfoCommon_ppc64.cpp
similarity index 83%
rename from lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_ppc64.cpp
rename to lldb/source/Plugins/Process/Utility/RegisterInfoCommon_ppc64.cpp
index e4969d4b306b70..d27abcb8c4541f 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_ppc64.cpp
+++ b/lldb/source/Plugins/Process/Utility/RegisterInfoCommon_ppc64.cpp
@@ -1,4 +1,4 @@
-//===-- RegisterInfoPOSIX_ppc64.cpp ---------------------------------------===//
+//===----------------------------------------------------------------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
@@ -13,9 +13,9 @@
#include "lldb/lldb-defines.h"
#include "llvm/Support/Compiler.h"
-#include "RegisterInfoPOSIX_ppc64.h"
+#include "RegisterInfoCommon_ppc64.h"
-// Include RegisterInfoPOSIX_ppc64 to declare our g_register_infos_ppc64
+// Include RegisterInfoCommon_ppc64 to declare our g_register_infos_ppc64
#define DECLARE_REGISTER_INFOS_PPC64_STRUCT
#include "RegisterInfos_ppc64.h"
#undef DECLARE_REGISTER_INFOS_PPC64_STRUCT
@@ -48,7 +48,7 @@ GetRegisterInfoCount(const lldb_private::ArchSpec &target_arch) {
}
}
-RegisterInfoPOSIX_ppc64::RegisterInfoPOSIX_ppc64(
+RegisterInfoCommon_ppc64::RegisterInfoCommon_ppc64(
const lldb_private::ArchSpec &target_arch)
: lldb_private::RegisterInfoInterface(target_arch),
m_register_info_p(GetRegisterInfoPtr(target_arch)),
@@ -66,13 +66,13 @@ RegisterInfoPOSIX_ppc64::RegisterInfoPOSIX_ppc64(
}
}
-size_t RegisterInfoPOSIX_ppc64::GetGPRSize() const { return m_gpr_size; }
+size_t RegisterInfoCommon_ppc64::GetGPRSize() const { return m_gpr_size; }
const lldb_private::RegisterInfo *
-RegisterInfoPOSIX_ppc64::GetRegisterInfo() const {
+RegisterInfoCommon_ppc64::GetRegisterInfo() const {
return m_register_info_p;
}
-uint32_t RegisterInfoPOSIX_ppc64::GetRegisterCount() const {
+uint32_t RegisterInfoCommon_ppc64::GetRegisterCount() const {
return m_register_info_count;
}
diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_ppc64.h b/lldb/source/Plugins/Process/Utility/RegisterInfoCommon_ppc64.h
similarity index 60%
rename from lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_ppc64.h
rename to lldb/source/Plugins/Process/Utility/RegisterInfoCommon_ppc64.h
index e33d32ae98ad38..e6feaa2431a26b 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_ppc64.h
+++ b/lldb/source/Plugins/Process/Utility/RegisterInfoCommon_ppc64.h
@@ -1,4 +1,4 @@
-//===-- RegisterInfoPOSIX_ppc64.h -------------------------------*- C++ -*-===//
+//===----------------------------------------------------------------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
@@ -6,16 +6,16 @@
//
//===----------------------------------------------------------------------===//
-#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOPOSIX_PPC64_H
-#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOPOSIX_PPC64_H
+#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOCOMMON_PPC64_H
+#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOCOMMON_PPC64_H
#include "RegisterInfoInterface.h"
#include "lldb/Target/RegisterContext.h"
#include "lldb/lldb-private.h"
-class RegisterInfoPOSIX_ppc64 : public lldb_private::RegisterInfoInterface {
+class RegisterInfoCommon_ppc64 : public lldb_private::RegisterInfoInterface {
public:
- RegisterInfoPOSIX_ppc64(const lldb_private::ArchSpec &target_arch);
+ RegisterInfoCommon_ppc64(const lldb_private::ArchSpec &target_arch);
size_t GetGPRSize() const override;
@@ -29,4 +29,4 @@ class RegisterInfoPOSIX_ppc64 : public lldb_private::RegisterInfoInterface {
size_t m_gpr_size;
};
-#endif // LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOPOSIX_PPC64_H
+#endif // LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOCOMMON_PPC64_H
diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_ppc64le.cpp b/lldb/source/Plugins/Process/Utility/RegisterInfoCommon_ppc64le.cpp
similarity index 78%
rename from lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_ppc64le.cpp
rename to lldb/source/Plugins/Process/Utility/RegisterInfoCommon_ppc64le.cpp
index 159fd2856443cc..4a81297419ba3f 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_ppc64le.cpp
+++ b/lldb/source/Plugins/Process/Utility/RegisterInfoCommon_ppc64le.cpp
@@ -1,10 +1,10 @@
-//===-- RegisterInfoPOSIX_ppc64le.cpp -------------------------------------===//
+//===----------------------------------------------------------------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
#include <cassert>
#include <cstddef>
@@ -13,9 +13,9 @@
#include "lldb/lldb-defines.h"
#include "llvm/Support/Compiler.h"
-#include "RegisterInfoPOSIX_ppc64le.h"
+#include "RegisterInfoCommon_ppc64le.h"
-// Include RegisterInfoPOSIX_ppc64le to declare our g_register_infos_ppc64le
+// Include RegisterInfoCommon_ppc64le to declare our g_register_infos_ppc64le
#define DECLARE_REGISTER_INFOS_PPC64LE_STRUCT
#include "RegisterInfos_ppc64le.h"
#undef DECLARE_REGISTER_INFOS_PPC64LE_STRUCT
@@ -43,21 +43,21 @@ GetRegisterInfoCount(const lldb_private::ArchSpec &target_arch) {
}
}
-RegisterInfoPOSIX_ppc64le::RegisterInfoPOSIX_ppc64le(
+RegisterInfoCommon_ppc64le::RegisterInfoCommon_ppc64le(
const lldb_private::ArchSpec &target_arch)
: lldb_private::RegisterInfoInterface(target_arch),
m_register_info_p(GetRegisterInfoPtr(target_arch)),
m_register_info_count(GetRegisterInfoCount(target_arch)) {}
-size_t RegisterInfoPOSIX_ppc64le::GetGPRSize() const {
+size_t RegisterInfoCommon_ppc64le::GetGPRSize() const {
return sizeof(GPR);
}
const lldb_private::RegisterInfo *
-RegisterInfoPOSIX_ppc64le::GetRegisterInfo() const {
+RegisterInfoCommon_ppc64le::GetRegisterInfo() const {
return m_register_info_p;
}
-uint32_t RegisterInfoPOSIX_ppc64le::GetRegisterCount() const {
+uint32_t RegisterInfoCommon_ppc64le::GetRegisterCount() const {
return m_register_info_count;
}
diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_ppc64le.h b/lldb/source/Plugins/Process/Utility/RegisterInfoCommon_ppc64le.h
similarity index 63%
rename from lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_ppc64le.h
rename to lldb/source/Plugins/Process/Utility/RegisterInfoCommon_ppc64le.h
index 98549ac0dda404..c853f62f8b6ad9 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_ppc64le.h
+++ b/lldb/source/Plugins/Process/Utility/RegisterInfoCommon_ppc64le.h
@@ -1,4 +1,4 @@
-//===-- RegisterInfoPOSIX_ppc64le.h -----------------------------*- C++ -*-===//
+//===----------------------------------------------------------------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
@@ -6,16 +6,16 @@
//
//===----------------------------------------------------------------------===//
-#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOPOSIX_PPC64LE_H
-#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOPOSIX_PPC64LE_H
+#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOCOMMON_PPC64LE_H
+#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOCOMMON_PPC64LE_H
#include "RegisterInfoInterface.h"
#include "lldb/Target/RegisterContext.h"
#include "lldb/lldb-private.h"
-class RegisterInfoPOSIX_ppc64le : public lldb_private::RegisterInfoInterface {
+class RegisterInfoCommon_ppc64le : public lldb_private::RegisterInfoInterface {
public:
- RegisterInfoPOSIX_ppc64le(const lldb_private::ArchSpec &target_arch);
+ RegisterInfoCommon_ppc64le(const lldb_private::ArchSpec &target_arch);
size_t GetGPRSize() const override;
diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_riscv32.cpp b/lldb/source/Plugins/Process/Utility/RegisterInfoCommon_riscv32.cpp
similarity index 80%
rename from lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_riscv32.cpp
rename to lldb/source/Plugins/Process/Utility/RegisterInfoCommon_riscv32.cpp
index e213b4a4a18200..67e5f20e6e45f5 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_riscv32.cpp
+++ b/lldb/source/Plugins/Process/Utility/RegisterInfoCommon_riscv32.cpp
@@ -1,12 +1,12 @@
-//===-- RegisterInfoPOSIX_riscv32.cpp -------------------------------------===//
+//===----------------------------------------------------------------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
-#include "RegisterInfoPOSIX_riscv32.h"
+#include "RegisterInfoCommon_riscv32.h"
#include "lldb/Utility/Flags.h"
#include "lldb/lldb-defines.h"
#include "llvm/Support/Compiler.h"
@@ -15,17 +15,17 @@
#include <stddef.h>
#define GPR_OFFSET(idx) ((idx) * 4 + 0)
-#define FPR_OFFSET(idx) ((idx) * 4 + sizeof(RegisterInfoPOSIX_riscv32::GPR))
+#define FPR_OFFSET(idx) ((idx) * 4 + sizeof(RegisterInfoCommon_riscv32::GPR))
#define REG_CONTEXT_SIZE \
- (sizeof(RegisterInfoPOSIX_riscv32::GPR) + \
- sizeof(RegisterInfoPOSIX_riscv32::FPR))
+ (sizeof(RegisterInfoCommon_riscv32::GPR) + \
+ sizeof(RegisterInfoCommon_riscv32::FPR))
#define DECLARE_REGISTER_INFOS_RISCV32_STRUCT
#include "RegisterInfos_riscv32.h"
#undef DECLARE_REGISTER_INFOS_RISCV32_STRUCT
-const lldb_private::RegisterInfo *RegisterInfoPOSIX_riscv32::GetRegisterInfoPtr(
+const lldb_private::RegisterInfo *RegisterInfoCommon_riscv32::GetRegisterInfoPtr(
const lldb_private::ArchSpec &target_arch) {
switch (target_arch.GetMachine()) {
case llvm::Triple::riscv32:
@@ -36,7 +36,7 @@ const lldb_private::RegisterInfo *RegisterInfoPOSIX_riscv32::GetRegisterInfoPtr(
}
}
-uint32_t RegisterInfoPOSIX_riscv32::GetRegisterInfoCount(
+uint32_t RegisterInfoCommon_riscv32::GetRegisterInfoCount(
const lldb_private::ArchSpec &target_arch) {
switch (target_arch.GetMachine()) {
case llvm::Triple::riscv32:
@@ -96,35 +96,35 @@ static const lldb_private::RegisterSet g_reg_sets_riscv32[k_num_register_sets] =
{"Floating Point Registers", "fpr", k_num_fpr_registers,
g_fpr_regnums_riscv32}};
-RegisterInfoPOSIX_riscv32::RegisterInfoPOSIX_riscv32(
+RegisterInfoCommon_riscv32::RegisterInfoCommon_riscv32(
const lldb_private::ArchSpec &target_arch, lldb_private::Flags opt_regsets)
: lldb_private::RegisterInfoAndSetInterface(target_arch),
m_register_info_p(GetRegisterInfoPtr(target_arch)),
m_register_info_count(GetRegisterInfoCount(target_arch)),
m_opt_regsets(opt_regsets) {}
-uint32_t RegisterInfoPOSIX_riscv32::GetRegisterCount() const {
+uint32_t RegisterInfoCommon_riscv32::GetRegisterCount() const {
return m_register_info_count;
}
-size_t RegisterInfoPOSIX_riscv32::GetGPRSize() const {
- return sizeof(struct RegisterInfoPOSIX_riscv32::GPR);
+size_t RegisterInfoCommon_riscv32::GetGPRSize() const {
+ return sizeof(struct RegisterInfoCommon_riscv32::GPR);
}
-size_t RegisterInfoPOSIX_riscv32::GetFPRSize() const {
- return sizeof(struct RegisterInfoPOSIX_riscv32::FPR);
+size_t RegisterInfoCommon_riscv32::GetFPRSize() const {
+ return sizeof(struct RegisterInfoCommon_riscv32::FPR);
}
const lldb_private::RegisterInfo *
-RegisterInfoPOSIX_riscv32::GetRegisterInfo() const {
+RegisterInfoCommon_riscv32::GetRegisterInfo() const {
return m_register_info_p;
}
-size_t RegisterInfoPOSIX_riscv32::GetRegisterSetCount() const {
+size_t RegisterInfoCommon_riscv32::GetRegisterSetCount() const {
return k_num_register_sets;
}
-size_t RegisterInfoPOSIX_riscv32::GetRegisterSetFromRegisterIndex(
+size_t RegisterInfoCommon_riscv32::GetRegisterSetFromRegisterIndex(
uint32_t reg_index) const {
// coverity[unsigned_compare]
if (reg_index >= gpr_first_riscv && reg_index <= gpr_last_riscv)
@@ -135,7 +135,7 @@ size_t RegisterInfoPOSIX_riscv32::GetRegisterSetFromRegisterIndex(
}
const lldb_private::RegisterSet *
-RegisterInfoPOSIX_riscv32::GetRegisterSet(size_t set_index) const {
+RegisterInfoCommon_riscv32::GetRegisterSet(size_t set_index) const {
if (set_index < GetRegisterSetCount())
return &g_reg_sets_riscv32[set_index];
return nullptr;
diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_riscv32.h b/lldb/source/Plugins/Process/Utility/RegisterInfoCommon_riscv32.h
similarity index 83%
rename from lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_riscv32.h
rename to lldb/source/Plugins/Process/Utility/RegisterInfoCommon_riscv32.h
index a2648d6f2faec2..4b51afdfbfb844 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_riscv32.h
+++ b/lldb/source/Plugins/Process/Utility/RegisterInfoCommon_riscv32.h
@@ -1,4 +1,4 @@
-//===-- RegisterInfoPOSIX_riscv32.h -----------------------------*- C++ -*-===//
+//===----------------------------------------------------------------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
@@ -6,8 +6,8 @@
//
//===----------------------------------------------------------------------===//
-#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOPOSIX_RISCV32_H
-#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOPOSIX_RISCV32_H
+#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOCOMMON_RISCV32_H
+#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOCOMMON_RISCV32_H
#include "RegisterInfoAndSetInterface.h"
#include "lldb/Target/RegisterContext.h"
@@ -16,7 +16,7 @@
#include <map>
-class RegisterInfoPOSIX_riscv32
+class RegisterInfoCommon_riscv32
: public lldb_private::RegisterInfoAndSetInterface {
public:
static const lldb_private::RegisterInfo *
@@ -42,7 +42,7 @@ class RegisterInfoPOSIX_riscv32
uint32_t fcsr;
};
- RegisterInfoPOSIX_riscv32(const lldb_private::ArchSpec &target_arch,
+ RegisterInfoCommon_riscv32(const lldb_private::ArchSpec &target_arch,
lldb_private::Flags flags);
size_t GetGPRSize() const override;
diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.cpp b/lldb/source/Plugins/Process/Utility/RegisterInfoCommon_riscv64.cpp
similarity index 82%
rename from lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.cpp
rename to lldb/source/Plugins/Process/Utility/RegisterInfoCommon_riscv64.cpp
index a0be54fc76cd53..34f554de637cf1 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.cpp
+++ b/lldb/source/Plugins/Process/Utility/RegisterInfoCommon_riscv64.cpp
@@ -1,12 +1,12 @@
-//===-- RegisterInfoPOSIX_riscv64.cpp -------------------------------------===//
+//===----------------------------------------------------------------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
-//===---------------------------------------------------------------------===//
+//===----------------------------------------------------------------------===//
-#include "RegisterInfoPOSIX_riscv64.h"
+#include "RegisterInfoCommon_riscv64.h"
#include "lldb/Utility/Flags.h"
#include "lldb/lldb-defines.h"
#include "llvm/Support/Compiler.h"
@@ -15,7 +15,7 @@
#include <stddef.h>
#define GPR_OFFSET(idx) ((idx)*8 + 0)
-#define FPR_OFFSET(idx) ((idx)*8 + sizeof(RegisterInfoPOSIX_riscv64::GPR))
+#define FPR_OFFSET(idx) ((idx)*8 + sizeof(RegisterInfoCommon_riscv64::GPR))
#define DECLARE_REGISTER_INFOS_RISCV64_STRUCT
#include "RegisterInfos_riscv64.h"
@@ -52,7 +52,7 @@ static const lldb_private::RegisterSet g_reg_set_gpr_riscv64 = {
static const lldb_private::RegisterSet g_reg_set_fpr_riscv64 = {
"Floating Point Registers", "fpr", k_num_fpr_registers, nullptr};
-RegisterInfoPOSIX_riscv64::RegisterInfoPOSIX_riscv64(
+RegisterInfoCommon_riscv64::RegisterInfoCommon_riscv64(
const lldb_private::ArchSpec &target_arch, lldb_private::Flags opt_regsets)
: lldb_private::RegisterInfoAndSetInterface(target_arch),
m_opt_regsets(opt_regsets) {
@@ -72,7 +72,7 @@ RegisterInfoPOSIX_riscv64::RegisterInfoPOSIX_riscv64(
}
}
-void RegisterInfoPOSIX_riscv64::AddRegSetGP() {
+void RegisterInfoCommon_riscv64::AddRegSetGP() {
m_register_infos.resize(k_num_gpr_registers);
memcpy(&m_register_infos[0], g_register_infos_riscv64_gpr,
sizeof(g_register_infos_riscv64_gpr));
@@ -82,7 +82,7 @@ void RegisterInfoPOSIX_riscv64::AddRegSetGP() {
std::make_pair(gpr_first_riscv, m_register_infos.size());
}
-void RegisterInfoPOSIX_riscv64::AddRegSetFP() {
+void RegisterInfoCommon_riscv64::AddRegSetFP() {
const uint32_t register_info_count = m_register_infos.size();
const uint32_t register_set_count = m_register_sets.size();
@@ -106,28 +106,28 @@ void RegisterInfoPOSIX_riscv64::AddRegSetFP() {
std::make_pair(register_info_count, m_register_infos.size());
}
-uint32_t RegisterInfoPOSIX_riscv64::GetRegisterCount() const {
+uint32_t RegisterInfoCommon_riscv64::GetRegisterCount() const {
return m_register_infos.size();
}
-size_t RegisterInfoPOSIX_riscv64::GetGPRSize() const {
- return sizeof(struct RegisterInfoPOSIX_riscv64::GPR);
+size_t RegisterInfoCommon_riscv64::GetGPRSize() const {
+ return sizeof(struct RegisterInfoCommon_riscv64::GPR);
}
-size_t RegisterInfoPOSIX_riscv64::GetFPRSize() const {
- return sizeof(struct RegisterInfoPOSIX_riscv64::FPR);
+size_t RegisterInfoCommon_riscv64::GetFPRSize() const {
+ return sizeof(struct RegisterInfoCommon_riscv64::FPR);
}
const lldb_private::RegisterInfo *
-RegisterInfoPOSIX_riscv64::GetRegisterInfo() const {
+RegisterInfoCommon_riscv64::GetRegisterInfo() const {
return m_register_infos.data();
}
-size_t RegisterInfoPOSIX_riscv64::GetRegisterSetCount() const {
+size_t RegisterInfoCommon_riscv64::GetRegisterSetCount() const {
return m_register_sets.size();
}
-size_t RegisterInfoPOSIX_riscv64::GetRegisterSetFromRegisterIndex(
+size_t RegisterInfoCommon_riscv64::GetRegisterSetFromRegisterIndex(
uint32_t reg_index) const {
for (const auto ®set_range : m_per_regset_regnum_range) {
if (reg_index >= regset_range.second.first &&
@@ -137,12 +137,12 @@ size_t RegisterInfoPOSIX_riscv64::GetRegisterSetFromRegisterIndex(
return LLDB_INVALID_REGNUM;
}
-bool RegisterInfoPOSIX_riscv64::IsFPReg(unsigned reg) const {
+bool RegisterInfoCommon_riscv64::IsFPReg(unsigned reg) const {
return llvm::is_contained(m_fp_regnum_collection, reg);
}
const lldb_private::RegisterSet *
-RegisterInfoPOSIX_riscv64::GetRegisterSet(size_t set_index) const {
+RegisterInfoCommon_riscv64::GetRegisterSet(size_t set_index) const {
if (set_index < GetRegisterSetCount())
return &m_register_sets[set_index];
return nullptr;
diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h b/lldb/source/Plugins/Process/Utility/RegisterInfoCommon_riscv64.h
similarity index 85%
rename from lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h
rename to lldb/source/Plugins/Process/Utility/RegisterInfoCommon_riscv64.h
index f8e22c7df3c88f..b041e369256723 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h
+++ b/lldb/source/Plugins/Process/Utility/RegisterInfoCommon_riscv64.h
@@ -1,4 +1,4 @@
-//===-- RegisterInfoPOSIX_riscv64.h -----------------------------*- C++ -*-===//
+//===----------------------------------------------------------------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
@@ -6,8 +6,8 @@
//
//===----------------------------------------------------------------------===//
-#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOPOSIX_RISCV64_H
-#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOPOSIX_RISCV64_H
+#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOCOMMON_RISCV64_H
+#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOCOMMON_RISCV64_H
#include "RegisterInfoAndSetInterface.h"
#include "lldb/Target/RegisterContext.h"
@@ -15,7 +15,7 @@
#include "lldb/lldb-private.h"
#include <map>
-class RegisterInfoPOSIX_riscv64
+class RegisterInfoCommon_riscv64
: public lldb_private::RegisterInfoAndSetInterface {
public:
enum { GPRegSet = 0 };
@@ -42,7 +42,7 @@ class RegisterInfoPOSIX_riscv64
void *vpr;
};
- RegisterInfoPOSIX_riscv64(const lldb_private::ArchSpec &target_arch,
+ RegisterInfoCommon_riscv64(const lldb_private::ArchSpec &target_arch,
lldb_private::Flags opt_regsets);
void AddRegSetGP();
diff --git a/lldb/source/Plugins/Process/Windows/Common/NativeRegisterContextWindows_arm.cpp b/lldb/source/Plugins/Process/Windows/Common/NativeRegisterContextWindows_arm.cpp
index fd8a0c05c1b25c..f4f52f7193bf12 100644
--- a/lldb/source/Plugins/Process/Windows/Common/NativeRegisterContextWindows_arm.cpp
+++ b/lldb/source/Plugins/Process/Windows/Common/NativeRegisterContextWindows_arm.cpp
@@ -10,7 +10,7 @@
#include "NativeRegisterContextWindows_arm.h"
#include "NativeThreadWindows.h"
-#include "Plugins/Process/Utility/RegisterInfoPOSIX_arm.h"
+#include "Plugins/Process/Utility/RegisterInfoCommon_arm.h"
#include "ProcessWindowsLog.h"
#include "lldb/Host/HostInfo.h"
#include "lldb/Host/HostThread.h"
@@ -82,7 +82,7 @@ static RegisterInfoInterface *
CreateRegisterInfoInterface(const ArchSpec &target_arch) {
assert((HostInfo::GetArchitecture().GetAddressByteSize() == 4) &&
"Register setting path assumes this is a 32-bit host");
- return new RegisterInfoPOSIX_arm(target_arch);
+ return new RegisterInfoCommon_arm(target_arch);
}
static Status GetThreadContextHelper(lldb::thread_t thread_handle,
diff --git a/lldb/source/Plugins/Process/Windows/Common/NativeRegisterContextWindows_arm64.cpp b/lldb/source/Plugins/Process/Windows/Common/NativeRegisterContextWindows_arm64.cpp
index 2a09c42531074b..af6307757dc4a1 100644
--- a/lldb/source/Plugins/Process/Windows/Common/NativeRegisterContextWindows_arm64.cpp
+++ b/lldb/source/Plugins/Process/Windows/Common/NativeRegisterContextWindows_arm64.cpp
@@ -97,8 +97,8 @@ static RegisterInfoInterface *
CreateRegisterInfoInterface(const ArchSpec &target_arch) {
assert((HostInfo::GetArchitecture().GetAddressByteSize() == 8) &&
"Register setting path assumes this is a 64-bit host");
- return new RegisterInfoPOSIX_arm64(
- target_arch, RegisterInfoPOSIX_arm64::eRegsetMaskDefault);
+ return new RegisterInfoCommon_arm64(
+ target_arch, RegisterInfoCommon_arm64::eRegsetMaskDefault);
}
static Status GetThreadContextLength(DWORD context_flags,
diff --git a/lldb/source/Plugins/Process/Windows/Common/NativeRegisterContextWindows_arm64.h b/lldb/source/Plugins/Process/Windows/Common/NativeRegisterContextWindows_arm64.h
index 4cfb3bf13c91bb..ec9e3e74ad3cf1 100644
--- a/lldb/source/Plugins/Process/Windows/Common/NativeRegisterContextWindows_arm64.h
+++ b/lldb/source/Plugins/Process/Windows/Common/NativeRegisterContextWindows_arm64.h
@@ -13,7 +13,7 @@
#include "NativeRegisterContextWindows.h"
#include "Plugins/Process/Utility/NativeRegisterContextDBReg_arm64.h"
-#include "Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h"
+#include "Plugins/Process/Utility/RegisterInfoCommon_arm64.h"
#include "Plugins/Process/Utility/lldb-arm64-register-enums.h"
#include "lldb/Host/windows/windows.h"
diff --git a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm.cpp b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm.cpp
index c9e90ebf8a4ddf..d64fa9a567c852 100644
--- a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm.cpp
+++ b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm.cpp
@@ -16,7 +16,7 @@
using namespace lldb_private;
RegisterContextCorePOSIX_arm::RegisterContextCorePOSIX_arm(
- Thread &thread, std::unique_ptr<RegisterInfoPOSIX_arm> register_info,
+ Thread &thread, std::unique_ptr<RegisterInfoCommon_arm> register_info,
const DataExtractor &gpregset, llvm::ArrayRef<CoreNote> notes)
: RegisterContextPOSIX_arm(thread, std::move(register_info)) {
m_gpr_buffer = std::make_shared<DataBufferHeap>(gpregset.GetDataStart(),
diff --git a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm.h b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm.h
index e466ee242181bc..3b41cbc24d5547 100644
--- a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm.h
+++ b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm.h
@@ -18,7 +18,7 @@ class RegisterContextCorePOSIX_arm : public RegisterContextPOSIX_arm {
public:
RegisterContextCorePOSIX_arm(
lldb_private::Thread &thread,
- std::unique_ptr<RegisterInfoPOSIX_arm> register_info,
+ std::unique_ptr<RegisterInfoCommon_arm> register_info,
const lldb_private::DataExtractor &gpregset,
llvm::ArrayRef<lldb_private::CoreNote> notes);
diff --git a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.cpp b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.cpp
index 837cb30798fe19..f910f62fb92a03 100644
--- a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.cpp
+++ b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.cpp
@@ -7,7 +7,7 @@
//===----------------------------------------------------------------------===//
#include "RegisterContextPOSIXCore_arm64.h"
-#include "Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h"
+#include "Plugins/Process/Utility/RegisterInfoCommon_arm64.h"
#include "Plugins/Process/Utility/AuxVector.h"
#include "Plugins/Process/Utility/RegisterTypeDetector_arm64.h"
@@ -24,50 +24,50 @@ std::unique_ptr<RegisterContextCorePOSIX_arm64>
RegisterContextCorePOSIX_arm64::Create(Thread &thread, const ArchSpec &arch,
const DataExtractor &gpregset,
llvm::ArrayRef<CoreNote> notes) {
- Flags opt_regsets = RegisterInfoPOSIX_arm64::eRegsetMaskDefault;
+ Flags opt_regsets = RegisterInfoCommon_arm64::eRegsetMaskDefault;
DataExtractor ssve_data =
getRegset(notes, arch.GetTriple(), AARCH64_SSVE_Desc);
if (ssve_data.GetByteSize() >= sizeof(sve::user_sve_header))
- opt_regsets.Set(RegisterInfoPOSIX_arm64::eRegsetMaskSSVE);
+ opt_regsets.Set(RegisterInfoCommon_arm64::eRegsetMaskSSVE);
DataExtractor sve_data = getRegset(notes, arch.GetTriple(), AARCH64_SVE_Desc);
if (sve_data.GetByteSize() >= sizeof(sve::user_sve_header))
- opt_regsets.Set(RegisterInfoPOSIX_arm64::eRegsetMaskSVE);
+ opt_regsets.Set(RegisterInfoCommon_arm64::eRegsetMaskSVE);
// Pointer Authentication register set data is based on struct
// user_pac_mask declared in ptrace.h. See reference implementation
// in Linux kernel source at arch/arm64/include/uapi/asm/ptrace.h.
DataExtractor pac_data = getRegset(notes, arch.GetTriple(), AARCH64_PAC_Desc);
if (pac_data.GetByteSize() >= sizeof(uint64_t) * 2)
- opt_regsets.Set(RegisterInfoPOSIX_arm64::eRegsetMaskPAuth);
+ opt_regsets.Set(RegisterInfoCommon_arm64::eRegsetMaskPAuth);
DataExtractor tls_data = getRegset(notes, arch.GetTriple(), AARCH64_TLS_Desc);
// A valid note will always contain at least one register, "tpidr". It may
// expand in future.
if (tls_data.GetByteSize() >= sizeof(uint64_t))
- opt_regsets.Set(RegisterInfoPOSIX_arm64::eRegsetMaskTLS);
+ opt_regsets.Set(RegisterInfoCommon_arm64::eRegsetMaskTLS);
DataExtractor za_data = getRegset(notes, arch.GetTriple(), AARCH64_ZA_Desc);
// Nothing if ZA is not present, just the header if it is disabled.
if (za_data.GetByteSize() >= sizeof(sve::user_za_header))
- opt_regsets.Set(RegisterInfoPOSIX_arm64::eRegsetMaskZA);
+ opt_regsets.Set(RegisterInfoCommon_arm64::eRegsetMaskZA);
DataExtractor mte_data = getRegset(notes, arch.GetTriple(), AARCH64_MTE_Desc);
if (mte_data.GetByteSize() >= sizeof(uint64_t))
- opt_regsets.Set(RegisterInfoPOSIX_arm64::eRegsetMaskMTE);
+ opt_regsets.Set(RegisterInfoCommon_arm64::eRegsetMaskMTE);
DataExtractor zt_data = getRegset(notes, arch.GetTriple(), AARCH64_ZT_Desc);
// Although ZT0 can be in a disabled state like ZA can, the kernel reports
// its content as 0s in that state. Therefore even a disabled ZT0 will have
// a note containing those 0s. ZT0 is a 512 bit / 64 byte register.
if (zt_data.GetByteSize() >= 64)
- opt_regsets.Set(RegisterInfoPOSIX_arm64::eRegsetMaskZT);
+ opt_regsets.Set(RegisterInfoCommon_arm64::eRegsetMaskZT);
DataExtractor fpmr_data =
getRegset(notes, arch.GetTriple(), AARCH64_FPMR_Desc);
if (fpmr_data.GetByteSize() >= sizeof(uint64_t))
- opt_regsets.Set(RegisterInfoPOSIX_arm64::eRegsetMaskFPMR);
+ opt_regsets.Set(RegisterInfoCommon_arm64::eRegsetMaskFPMR);
DataExtractor gcs_data = getRegset(notes, arch.GetTriple(), AARCH64_GCS_Desc);
struct __attribute__((packed)) gcs_regs {
@@ -76,24 +76,24 @@ RegisterContextCorePOSIX_arm64::Create(Thread &thread, const ArchSpec &arch,
uint64_t gcspr_e0;
};
if (gcs_data.GetByteSize() >= sizeof(gcs_regs))
- opt_regsets.Set(RegisterInfoPOSIX_arm64::eRegsetMaskGCS);
+ opt_regsets.Set(RegisterInfoCommon_arm64::eRegsetMaskGCS);
DataExtractor poe_data = getRegset(notes, arch.GetTriple(), AARCH64_POE_Desc);
struct poe_regs {
uint64_t por_el0_reg;
};
if (poe_data.GetByteSize() >= sizeof(poe_regs))
- opt_regsets.Set(RegisterInfoPOSIX_arm64::eRegsetMaskPOE);
+ opt_regsets.Set(RegisterInfoCommon_arm64::eRegsetMaskPOE);
auto register_info_up =
- std::make_unique<RegisterInfoPOSIX_arm64>(arch, opt_regsets);
+ std::make_unique<RegisterInfoCommon_arm64>(arch, opt_regsets);
return std::unique_ptr<RegisterContextCorePOSIX_arm64>(
new RegisterContextCorePOSIX_arm64(thread, std::move(register_info_up),
gpregset, notes));
}
RegisterContextCorePOSIX_arm64::RegisterContextCorePOSIX_arm64(
- Thread &thread, std::unique_ptr<RegisterInfoPOSIX_arm64> register_info,
+ Thread &thread, std::unique_ptr<RegisterInfoCommon_arm64> register_info,
const DataExtractor &gpregset, llvm::ArrayRef<CoreNote> notes)
: RegisterContextPOSIX_arm64(thread, std::move(register_info)) {
::memset(&m_sme_pseudo_regs, 0, sizeof(m_sme_pseudo_regs));
diff --git a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.h b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.h
index 9d9a2da2bc1b99..2499556e203d4d 100644
--- a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.h
+++ b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.h
@@ -41,7 +41,7 @@ class RegisterContextCorePOSIX_arm64 : public RegisterContextPOSIX_arm64 {
protected:
RegisterContextCorePOSIX_arm64(
lldb_private::Thread &thread,
- std::unique_ptr<RegisterInfoPOSIX_arm64> register_info,
+ std::unique_ptr<RegisterInfoCommon_arm64> register_info,
const lldb_private::DataExtractor &gpregset,
llvm::ArrayRef<lldb_private::CoreNote> notes);
diff --git a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_loongarch64.cpp b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_loongarch64.cpp
index f0500948a6ab22..9b0dc0984f5f60 100644
--- a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_loongarch64.cpp
+++ b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_loongarch64.cpp
@@ -20,13 +20,13 @@ RegisterContextCorePOSIX_loongarch64::Create(Thread &thread,
return std::unique_ptr<RegisterContextCorePOSIX_loongarch64>(
new RegisterContextCorePOSIX_loongarch64(
thread,
- std::make_unique<RegisterInfoPOSIX_loongarch64>(arch, Flags()),
+ std::make_unique<RegisterInfoCommon_loongarch64>(arch, Flags()),
gpregset, notes));
}
RegisterContextCorePOSIX_loongarch64::RegisterContextCorePOSIX_loongarch64(
Thread &thread,
- std::unique_ptr<RegisterInfoPOSIX_loongarch64> register_info,
+ std::unique_ptr<RegisterInfoCommon_loongarch64> register_info,
const DataExtractor &gpregset, llvm::ArrayRef<CoreNote> notes)
: RegisterContextPOSIX_loongarch64(thread, std::move(register_info)) {
diff --git a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_loongarch64.h b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_loongarch64.h
index 7bb53bd642030a..63b97551bbbeed 100644
--- a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_loongarch64.h
+++ b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_loongarch64.h
@@ -10,7 +10,7 @@
#define LLDB_SOURCE_PLUGINS_PROCESS_ELF_CORE_REGISTERCONTEXTPOSIXCORE_LOONGARCH64_H
#include "Plugins/Process/Utility/RegisterContextPOSIX_loongarch64.h"
-#include "Plugins/Process/Utility/RegisterInfoPOSIX_loongarch64.h"
+#include "Plugins/Process/Utility/RegisterInfoCommon_loongarch64.h"
#include "Plugins/Process/elf-core/RegisterUtilities.h"
#include "lldb/Target/Thread.h"
@@ -38,7 +38,7 @@ class RegisterContextCorePOSIX_loongarch64
protected:
RegisterContextCorePOSIX_loongarch64(
lldb_private::Thread &thread,
- std::unique_ptr<RegisterInfoPOSIX_loongarch64> register_info,
+ std::unique_ptr<RegisterInfoCommon_loongarch64> register_info,
const lldb_private::DataExtractor &gpregset,
llvm::ArrayRef<lldb_private::CoreNote> notes);
diff --git a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv32.cpp b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv32.cpp
index 9718e1b0fe1a99..a52d99c2791ab6 100644
--- a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv32.cpp
+++ b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv32.cpp
@@ -42,13 +42,13 @@ RegisterContextCorePOSIX_riscv32::Create(Thread &thread, const ArchSpec &arch,
llvm::ArrayRef<CoreNote> notes) {
return std::unique_ptr<RegisterContextCorePOSIX_riscv32>(
new RegisterContextCorePOSIX_riscv32(
- thread, std::make_unique<RegisterInfoPOSIXDynamic_riscv32>(arch),
+ thread, std::make_unique<RegisterInfoCommonDynamic_riscv32>(arch),
gpregset, notes));
}
RegisterContextCorePOSIX_riscv32::RegisterContextCorePOSIX_riscv32(
Thread &thread,
- std::unique_ptr<RegisterInfoPOSIXDynamic_riscv32> register_info,
+ std::unique_ptr<RegisterInfoCommonDynamic_riscv32> register_info,
const DataExtractor &gpregset, llvm::ArrayRef<CoreNote> notes)
: RegisterContext(thread, 0), m_reg_infos_up(std::move(register_info)) {
// Compute the maximum register counts for GPR, FPR, and CSR.
diff --git a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv32.h b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv32.h
index 40407982145b9c..6f154bcfbceb99 100644
--- a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv32.h
+++ b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv32.h
@@ -9,7 +9,7 @@
#ifndef LLDB_SOURCE_PLUGINS_PROCESS_ELF_CORE_REGISTERCONTEXTPOSIXCORE_RISCV32_H
#define LLDB_SOURCE_PLUGINS_PROCESS_ELF_CORE_REGISTERCONTEXTPOSIXCORE_RISCV32_H
-#include "Plugins/Process/Utility/RegisterInfoPOSIXDynamic_riscv32.h"
+#include "Plugins/Process/Utility/RegisterInfoCommonDynamic_riscv32.h"
#include "Plugins/Process/elf-core/RegisterUtilities.h"
#include "lldb/Target/Thread.h"
#include "lldb/Utility/DataExtractor.h"
@@ -51,7 +51,7 @@ class RegisterContextCorePOSIX_riscv32 : public lldb_private::RegisterContext {
protected:
RegisterContextCorePOSIX_riscv32(
lldb_private::Thread &thread,
- std::unique_ptr<RegisterInfoPOSIXDynamic_riscv32> register_info,
+ std::unique_ptr<RegisterInfoCommonDynamic_riscv32> register_info,
const lldb_private::DataExtractor &gpregset,
llvm::ArrayRef<lldb_private::CoreNote> notes);
@@ -71,7 +71,7 @@ class RegisterContextCorePOSIX_riscv32 : public lldb_private::RegisterContext {
void GetFeatures(llvm::SmallVectorImpl<std::string> &features) const;
private:
- std::unique_ptr<RegisterInfoPOSIXDynamic_riscv32> m_reg_infos_up;
+ std::unique_ptr<RegisterInfoCommonDynamic_riscv32> m_reg_infos_up;
lldb_private::DataExtractor m_gpregset;
lldb_private::DataExtractor m_fpregset;
lldb_private::DataExtractor m_csregset;
diff --git a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv64.cpp b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv64.cpp
index 3dca4b16099056..6e4e6451297488 100644
--- a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv64.cpp
+++ b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv64.cpp
@@ -16,22 +16,22 @@ std::unique_ptr<RegisterContextCorePOSIX_riscv64>
RegisterContextCorePOSIX_riscv64::Create(Thread &thread, const ArchSpec &arch,
const DataExtractor &gpregset,
llvm::ArrayRef<CoreNote> notes) {
- Flags opt_regsets = RegisterInfoPOSIX_riscv64::eRegsetMaskDefault;
+ Flags opt_regsets = RegisterInfoCommon_riscv64::eRegsetMaskDefault;
DataExtractor fpregset = getRegset(notes, arch.GetTriple(), FPR_Desc);
if (fpregset.GetByteSize() >= sizeof(uint64_t)) {
- opt_regsets.Set(RegisterInfoPOSIX_riscv64::eRegsetMaskFP);
+ opt_regsets.Set(RegisterInfoCommon_riscv64::eRegsetMaskFP);
}
return std::unique_ptr<RegisterContextCorePOSIX_riscv64>(
new RegisterContextCorePOSIX_riscv64(
thread,
- std::make_unique<RegisterInfoPOSIX_riscv64>(arch, opt_regsets),
+ std::make_unique<RegisterInfoCommon_riscv64>(arch, opt_regsets),
gpregset, notes));
}
RegisterContextCorePOSIX_riscv64::RegisterContextCorePOSIX_riscv64(
- Thread &thread, std::unique_ptr<RegisterInfoPOSIX_riscv64> register_info,
+ Thread &thread, std::unique_ptr<RegisterInfoCommon_riscv64> register_info,
const DataExtractor &gpregset, llvm::ArrayRef<CoreNote> notes)
: RegisterContextPOSIX_riscv64(thread, std::move(register_info)) {
diff --git a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv64.h b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv64.h
index a9a59844635749..9a0153d78d867f 100644
--- a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv64.h
+++ b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv64.h
@@ -10,7 +10,7 @@
#define LLDB_SOURCE_PLUGINS_PROCESS_ELF_CORE_REGISTERCONTEXTPOSIXCORE_RISCV64_H
#include "Plugins/Process/Utility/RegisterContextPOSIX_riscv64.h"
-#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h"
+#include "Plugins/Process/Utility/RegisterInfoCommon_riscv64.h"
#include "Plugins/Process/elf-core/RegisterUtilities.h"
#include "lldb/Target/Thread.h"
@@ -37,7 +37,7 @@ class RegisterContextCorePOSIX_riscv64 : public RegisterContextPOSIX_riscv64 {
protected:
RegisterContextCorePOSIX_riscv64(
lldb_private::Thread &thread,
- std::unique_ptr<RegisterInfoPOSIX_riscv64> register_info,
+ std::unique_ptr<RegisterInfoCommon_riscv64> register_info,
const lldb_private::DataExtractor &gpregset,
llvm::ArrayRef<lldb_private::CoreNote> notes);
diff --git a/lldb/source/Plugins/Process/elf-core/ThreadElfCore.cpp b/lldb/source/Plugins/Process/elf-core/ThreadElfCore.cpp
index 25f9a6a164d26f..f024211abc2b6d 100644
--- a/lldb/source/Plugins/Process/elf-core/ThreadElfCore.cpp
+++ b/lldb/source/Plugins/Process/elf-core/ThreadElfCore.cpp
@@ -26,9 +26,9 @@
#include "Plugins/Process/Utility/RegisterInfoNetBSD_x86_64.h"
#include "Plugins/Process/Utility/RegisterInfoOpenBSD_i386.h"
#include "Plugins/Process/Utility/RegisterInfoOpenBSD_x86_64.h"
-#include "Plugins/Process/Utility/RegisterInfoPOSIX_arm.h"
-#include "Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h"
-#include "Plugins/Process/Utility/RegisterInfoPOSIX_ppc64le.h"
+#include "Plugins/Process/Utility/RegisterInfoCommon_arm.h"
+#include "Plugins/Process/Utility/RegisterInfoCommon_arm64.h"
+#include "Plugins/Process/Utility/RegisterInfoCommon_ppc64le.h"
#include "ProcessElfCore.h"
#include "RegisterContextLinuxCore_x86.h"
#include "RegisterContextPOSIXCore_arm.h"
@@ -131,7 +131,7 @@ ThreadElfCore::CreateRegisterContextForFrame(StackFrame *frame) {
case llvm::Triple::aarch64:
break;
case llvm::Triple::ppc64le:
- reg_interface = new RegisterInfoPOSIX_ppc64le(arch);
+ reg_interface = new RegisterInfoCommon_ppc64le(arch);
break;
case llvm::Triple::systemz:
reg_interface = new RegisterInfoLinux_s390x(arch);
@@ -185,7 +185,7 @@ ThreadElfCore::CreateRegisterContextForFrame(StackFrame *frame) {
break;
case llvm::Triple::arm:
m_thread_reg_ctx_sp = std::make_shared<RegisterContextCorePOSIX_arm>(
- *this, std::make_unique<RegisterInfoPOSIX_arm>(arch), m_gpregset_data,
+ *this, std::make_unique<RegisterInfoCommon_arm>(arch), m_gpregset_data,
m_notes);
break;
case llvm::Triple::loongarch64:
diff --git a/lldb/unittests/Instruction/ARM64/TestAArch64Emulator.cpp b/lldb/unittests/Instruction/ARM64/TestAArch64Emulator.cpp
index c6bfe0fa687599..1ad9ec8f88f929 100644
--- a/lldb/unittests/Instruction/ARM64/TestAArch64Emulator.cpp
+++ b/lldb/unittests/Instruction/ARM64/TestAArch64Emulator.cpp
@@ -16,14 +16,14 @@
#include "lldb/Utility/RegisterValue.h"
#include "Plugins/Instruction/ARM64/EmulateInstructionARM64.h"
-#include "Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h"
+#include "Plugins/Process/Utility/RegisterInfoCommon_arm64.h"
#include "Plugins/Process/Utility/lldb-arm64-register-enums.h"
using namespace lldb;
using namespace lldb_private;
struct Arch64EmulatorTester : public EmulateInstructionARM64 {
- RegisterInfoPOSIX_arm64::GPR gpr;
+ RegisterInfoCommon_arm64::GPR gpr;
uint8_t memory[64] = {0};
uint64_t memory_offset = 0;
diff --git a/lldb/unittests/Instruction/LoongArch/TestLoongArchEmulator.cpp b/lldb/unittests/Instruction/LoongArch/TestLoongArchEmulator.cpp
index f3b0d65c2cbfe0..c53b0bde52a090 100644
--- a/lldb/unittests/Instruction/LoongArch/TestLoongArchEmulator.cpp
+++ b/lldb/unittests/Instruction/LoongArch/TestLoongArchEmulator.cpp
@@ -15,7 +15,7 @@
#include "gtest/gtest.h"
#include "Plugins/Instruction/LoongArch/EmulateInstructionLoongArch.h"
-#include "Plugins/Process/Utility/RegisterInfoPOSIX_loongarch64.h"
+#include "Plugins/Process/Utility/RegisterInfoCommon_loongarch64.h"
#include "Plugins/Process/Utility/lldb-loongarch-register-enums.h"
using namespace llvm;
@@ -48,8 +48,8 @@ using namespace lldb_private;
struct LoongArch64EmulatorTester : public EmulateInstructionLoongArch,
testing::Test {
- RegisterInfoPOSIX_loongarch64::GPR gpr;
- RegisterInfoPOSIX_loongarch64::FPR fpr;
+ RegisterInfoCommon_loongarch64::GPR gpr;
+ RegisterInfoCommon_loongarch64::FPR fpr;
LoongArch64EmulatorTester(
std::string triple = "loongarch64-unknown-linux-gnu")
diff --git a/lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp b/lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp
index f713755c77a7c7..ebc80a3dd45d52 100644
--- a/lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp
+++ b/lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp
@@ -16,8 +16,8 @@
#include "lldb/Utility/RegisterValue.h"
#include "Plugins/Instruction/RISCV/EmulateInstructionRISCV.h"
-#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv32.h"
-#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h"
+#include "Plugins/Process/Utility/RegisterInfoCommon_riscv32.h"
+#include "Plugins/Process/Utility/RegisterInfoCommon_riscv64.h"
#include "Plugins/Process/Utility/lldb-riscv-register-enums.h"
using namespace llvm;
@@ -25,8 +25,8 @@ using namespace lldb;
using namespace lldb_private;
struct RISCVEmulatorTester : public EmulateInstructionRISCV, testing::Test {
- RegisterInfoPOSIX_riscv64::GPR gpr;
- RegisterInfoPOSIX_riscv64::FPR fpr;
+ RegisterInfoCommon_riscv64::GPR gpr;
+ RegisterInfoCommon_riscv64::FPR fpr;
uint8_t memory[1024] = {0};
RISCVEmulatorTester(std::string triple = "riscv64-unknown-linux-gnu")
diff --git a/lldb/unittests/Process/Utility/RegisterInfoFreeBSDTest.cpp b/lldb/unittests/Process/Utility/RegisterInfoFreeBSDTest.cpp
index e14307dad4a480..f8be5f7262aa45 100644
--- a/lldb/unittests/Process/Utility/RegisterInfoFreeBSDTest.cpp
+++ b/lldb/unittests/Process/Utility/RegisterInfoFreeBSDTest.cpp
@@ -21,8 +21,8 @@
#include "Plugins/Process/Utility/RegisterInfoFreeBSD_powerpc.h"
#include "Plugins/Process/Utility/RegisterInfoFreeBSD_x86_64.h"
#include "Plugins/Process/Utility/RegisterContextPOSIX_powerpc.h"
-#include "Plugins/Process/Utility/RegisterInfoPOSIX_arm.h"
-#include "Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h"
+#include "Plugins/Process/Utility/RegisterInfoCommon_arm.h"
+#include "Plugins/Process/Utility/RegisterInfoCommon_arm64.h"
#include "Plugins/Process/Utility/lldb-arm-register-enums.h"
#include "Plugins/Process/Utility/lldb-arm64-register-enums.h"
#include "Plugins/Process/Utility/lldb-x86-register-enums.h"
@@ -253,7 +253,7 @@ TEST(RegisterInfoFreeBSDTest, i386) {
TEST(RegisterInfoFreeBSDTest, arm) {
ArchSpec arch{"arm-unknown-freebsd"};
- RegisterInfoPOSIX_arm reg_ctx{arch};
+ RegisterInfoCommon_arm reg_ctx{arch};
EXPECT_GPR_ARM(r0, r[0]);
EXPECT_GPR_ARM(r1, r[1]);
@@ -323,9 +323,9 @@ TEST(RegisterInfoFreeBSDTest, arm) {
sizeof(fpreg::fbsd_reg)))
TEST(RegisterInfoFreeBSDTest, arm64) {
- Flags opt_regsets = RegisterInfoPOSIX_arm64::eRegsetMaskDefault;
+ Flags opt_regsets = RegisterInfoCommon_arm64::eRegsetMaskDefault;
ArchSpec arch{"aarch64-unknown-freebsd"};
- RegisterInfoPOSIX_arm64 reg_ctx{arch, opt_regsets};
+ RegisterInfoCommon_arm64 reg_ctx{arch, opt_regsets};
EXPECT_GPR_ARM64(x0, x[0]);
EXPECT_GPR_ARM64(x1, x[1]);
diff --git a/llvm/utils/gn/secondary/lldb/source/Plugins/Process/Utility/BUILD.gn b/llvm/utils/gn/secondary/lldb/source/Plugins/Process/Utility/BUILD.gn
index ee138642d78f15..88841256310bf6 100644
--- a/llvm/utils/gn/secondary/lldb/source/Plugins/Process/Utility/BUILD.gn
+++ b/llvm/utils/gn/secondary/lldb/source/Plugins/Process/Utility/BUILD.gn
@@ -23,14 +23,14 @@ static_library("Register") {
"RegisterInfoWindows_i386.cpp",
"RegisterInfoWindows_x86_64.cpp",
"RegisterContext_x86.cpp",
- "RegisterInfoPOSIXDynamic_riscv32.cpp",
- "RegisterInfoPOSIX_arm.cpp",
- "RegisterInfoPOSIX_arm64.cpp",
- "RegisterInfoPOSIX_loongarch64.cpp",
- "RegisterInfoPOSIX_ppc64.cpp",
- "RegisterInfoPOSIX_ppc64le.cpp",
- "RegisterInfoPOSIX_riscv32.cpp",
- "RegisterInfoPOSIX_riscv64.cpp",
+ "RegisterInfoCommonDynamic_riscv32.cpp",
+ "RegisterInfoCommon_arm.cpp",
+ "RegisterInfoCommon_arm64.cpp",
+ "RegisterInfoCommon_loongarch64.cpp",
+ "RegisterInfoCommon_ppc64.cpp",
+ "RegisterInfoCommon_ppc64le.cpp",
+ "RegisterInfoCommon_riscv32.cpp",
+ "RegisterInfoCommon_riscv64.cpp",
"RegisterInfos_x86_64_with_base_shared.cpp",
"RegisterTypeDetector_arm64.cpp",
]
>From b7df6ed959e4569ef699559830d91114f2ca5a7d Mon Sep 17 00:00:00 2001
From: Minsoo Choo <minsoo at minsoo.io>
Date: Thu, 10 Sep 2026 10:39:03 -0400
Subject: [PATCH 2/5] [lldb] Move register support out of ProcessUtility
---
lldb/source/CMakeLists.txt | 1 +
.../Plugins/ABI/PowerPC/ABISysV_ppc64.cpp | 4 +-
.../ARM64/EmulateInstructionARM64.cpp | 4 +-
.../LoongArch/EmulateInstructionLoongArch.cpp | 4 +-
.../MIPS/EmulateInstructionMIPS.cpp | 2 +-
.../MIPS64/EmulateInstructionMIPS64.cpp | 2 +-
.../PPC64/EmulateInstructionPPC64.cpp | 4 +-
.../RISCV/EmulateInstructionRISCV.cpp | 8 +-
.../Instruction/RISCV/RISCVCInstructions.h | 2 +-
.../ObjectFile/PECOFF/PECallFrameInfo.cpp | 2 +-
.../Plugins/Platform/Linux/PlatformLinux.cpp | 2 +-
.../Plugins/Process/AIX/NativeProcessAIX.cpp | 2 +-
.../AIX/NativeRegisterContextAIX_ppc64.cpp | 2 +-
.../AIX/NativeRegisterContextAIX_ppc64.h | 4 +-
.../RegisterContextFreeBSDKernelCore_arm.cpp | 2 +-
...RegisterContextFreeBSDKernelCore_arm64.cpp | 2 +-
.../ThreadFreeBSDKernelCore.cpp | 12 +-
.../NativeRegisterContextFreeBSD_arm.cpp | 2 +-
.../NativeRegisterContextFreeBSD_arm.h | 2 +-
.../NativeRegisterContextFreeBSD_arm64.cpp | 4 +-
.../NativeRegisterContextFreeBSD_arm64.h | 2 +-
.../NativeRegisterContextFreeBSD_powerpc.h | 2 +-
.../NativeRegisterContextFreeBSD_x86.cpp | 4 +-
.../NativeRegisterContextFreeBSD_x86.h | 4 +-
.../Linux/NativeRegisterContextLinux_arm.cpp | 2 +-
.../Linux/NativeRegisterContextLinux_arm.h | 4 +-
.../NativeRegisterContextLinux_arm64.cpp | 4 +-
.../Linux/NativeRegisterContextLinux_arm64.h | 2 +-
...NativeRegisterContextLinux_loongarch64.cpp | 4 +-
.../NativeRegisterContextLinux_loongarch64.h | 2 +-
.../NativeRegisterContextLinux_ppc64le.cpp | 2 +-
.../NativeRegisterContextLinux_ppc64le.h | 4 +-
.../NativeRegisterContextLinux_riscv64.cpp | 4 +-
.../NativeRegisterContextLinux_riscv64.h | 2 +-
.../NativeRegisterContextLinux_s390x.cpp | 2 +-
.../Linux/NativeRegisterContextLinux_s390x.h | 4 +-
.../Linux/NativeRegisterContextLinux_x86.cpp | 4 +-
.../Linux/NativeRegisterContextLinux_x86.h | 6 +-
.../NativeRegisterContextNetBSD_x86.cpp | 4 +-
.../NetBSD/NativeRegisterContextNetBSD_x86.h | 4 +-
.../Plugins/Process/Utility/CMakeLists.txt | 36 -
.../NativeRegisterContextDBReg_x86.cpp | 2 +-
.../Utility/RegisterContextPOSIX_ppc64le.h | 2 +-
.../RegisterInfos_x86_64_with_base_shared.h | 16 +-
.../NativeRegisterContextWindows_WoW64.cpp | 2 +-
.../NativeRegisterContextWindows_WoW64.h | 4 +-
.../NativeRegisterContextWindows_arm.cpp | 2 +-
.../Common/NativeRegisterContextWindows_arm.h | 2 +-
.../NativeRegisterContextWindows_arm64.h | 4 +-
.../NativeRegisterContextWindows_i386.cpp | 2 +-
.../NativeRegisterContextWindows_i386.h | 4 +-
.../NativeRegisterContextWindows_x86_64.cpp | 4 +-
.../NativeRegisterContextWindows_x86_64.h | 4 +-
.../Common/arm/RegisterContextWindows_arm.cpp | 2 +-
.../arm64/RegisterContextWindows_arm64.cpp | 2 +-
.../Common/x64/RegisterContextWindows_x64.cpp | 4 +-
.../Common/x86/RegisterContextWindows_x86.cpp | 4 +-
.../RegisterContextPOSIXCore_arm64.cpp | 4 +-
.../elf-core/RegisterContextPOSIXCore_arm64.h | 2 +-
.../RegisterContextPOSIXCore_loongarch64.h | 2 +-
.../RegisterContextPOSIXCore_ppc64le.cpp | 2 +-
.../RegisterContextPOSIXCore_riscv32.cpp | 2 +-
.../RegisterContextPOSIXCore_riscv32.h | 2 +-
.../RegisterContextPOSIXCore_riscv64.h | 2 +-
.../Process/elf-core/ThreadElfCore.cpp | 26 +-
.../minidump/RegisterContextMinidump_ARM.h | 2 +-
.../minidump/RegisterContextMinidump_ARM64.h | 2 +-
.../minidump/RegisterContextMinidump_x86_32.h | 4 +-
.../minidump/RegisterContextMinidump_x86_64.h | 4 +-
.../Process/minidump/ThreadMinidump.cpp | 4 +-
.../NativePDB/CodeViewRegisterMapping.cpp | 4 +-
.../Arch}/RegisterContext_mips.h | 6 +-
.../Arch}/RegisterContext_powerpc.h | 6 +-
.../Arch}/RegisterContext_s390x.h | 4 +-
.../Arch}/RegisterContext_x86.cpp | 4 +-
.../Arch}/RegisterContext_x86.h | 4 +-
.../Arch}/RegisterInfos_arm.h | 0
.../Arch}/RegisterInfos_arm64.h | 0
.../Arch}/RegisterInfos_arm64_sve.h | 0
.../Arch}/RegisterInfos_i386.h | 0
.../Arch}/RegisterInfos_loongarch64.h | 2 +-
.../Arch}/RegisterInfos_mips.h | 0
.../Arch}/RegisterInfos_mips64.h | 0
.../Arch}/RegisterInfos_powerpc.h | 0
.../Arch}/RegisterInfos_ppc64.h | 2 +-
.../Arch}/RegisterInfos_ppc64le.h | 2 +-
.../Register/Arch/RegisterInfos_riscv32.h | 764 +++
.../Arch}/RegisterInfos_riscv64.h | 2 +-
.../Arch}/RegisterInfos_s390x.h | 0
.../Arch}/RegisterInfos_x86_64.h | 0
.../Arch}/RegisterInfos_x86_64_with_base.h | 2 +-
.../RegisterInfos_x86_64_with_base_shared.cpp | 2 +-
.../RegisterInfos_x86_64_with_base_shared.h | 142 +
.../Arch}/lldb-arm-register-enums.h | 6 +-
.../Arch}/lldb-arm64-register-enums.h | 6 +-
.../Arch}/lldb-loongarch-register-enums.h | 6 +-
.../Arch}/lldb-ppc64-register-enums.h | 6 +-
.../Arch}/lldb-ppc64le-register-enums.h | 6 +-
.../Register/Arch/lldb-riscv-register-enums.h | 4733 +++++++++++++++++
.../Arch}/lldb-s390x-register-enums.h | 6 +-
.../Arch}/lldb-x86-register-enums.h | 6 +-
lldb/source/Register/CMakeLists.txt | 33 +
.../RegisterInfoCommonDynamic_riscv32.cpp | 6 +-
.../RegisterInfoCommonDynamic_riscv32.h | 8 +-
.../Common/RegisterInfoCommon_arm.cpp | 211 +
.../Register/Common/RegisterInfoCommon_arm.h | 80 +
.../Common/RegisterInfoCommon_arm64.cpp | 681 +++
.../Common/RegisterInfoCommon_arm64.h | 226 +
.../Common/RegisterInfoCommon_loongarch64.cpp | 215 +
.../Common/RegisterInfoCommon_loongarch64.h | 81 +
.../Common/RegisterInfoCommon_ppc64.cpp | 78 +
.../Common/RegisterInfoCommon_ppc64.h | 32 +
.../Common/RegisterInfoCommon_ppc64le.cpp | 63 +
.../Common/RegisterInfoCommon_ppc64le.h | 31 +
.../Common/RegisterInfoCommon_riscv32.cpp | 142 +
.../Common/RegisterInfoCommon_riscv32.h | 71 +
.../Common/RegisterInfoCommon_riscv64.cpp | 149 +
.../Common/RegisterInfoCommon_riscv64.h | 86 +
.../Common}/RegisterTypeDetector_arm64.cpp | 2 +-
.../Common}/RegisterTypeDetector_arm64.h | 6 +-
.../FreeBSD/RegisterInfoFreeBSD_i386.cpp | 85 +
.../FreeBSD/RegisterInfoFreeBSD_i386.h | 25 +
.../FreeBSD/RegisterInfoFreeBSD_powerpc.cpp | 233 +
.../FreeBSD/RegisterInfoFreeBSD_powerpc.h | 52 +
.../FreeBSD/RegisterInfoFreeBSD_x86_64.cpp | 143 +
.../FreeBSD/RegisterInfoFreeBSD_x86_64.h | 30 +
.../Register/Linux/RegisterInfoLinux_i386.cpp | 127 +
.../Register/Linux/RegisterInfoLinux_i386.h | 29 +
.../Linux/RegisterInfoLinux_s390x.cpp | 69 +
.../Register/Linux/RegisterInfoLinux_s390x.h | 32 +
.../Register/Linux/RegisterInfoLinux_x86.h | 30 +
.../Linux/RegisterInfoLinux_x86_64.cpp | 186 +
.../Register/Linux/RegisterInfoLinux_x86_64.h | 34 +
.../NetBSD/RegisterInfoNetBSD_i386.cpp | 98 +
.../Register/NetBSD/RegisterInfoNetBSD_i386.h | 25 +
.../NetBSD/RegisterInfoNetBSD_x86_64.cpp | 180 +
.../NetBSD/RegisterInfoNetBSD_x86_64.h | 33 +
.../OpenBSD/RegisterInfoOpenBSD_i386.cpp | 79 +
.../OpenBSD/RegisterInfoOpenBSD_i386.h | 25 +
.../OpenBSD/RegisterInfoOpenBSD_x86_64.cpp | 106 +
.../OpenBSD/RegisterInfoOpenBSD_x86_64.h | 30 +
.../RegisterInfoAndSetInterface.h | 6 +-
.../RegisterInfoInterface.h | 4 +-
.../Windows/RegisterInfoWindows_i386.cpp | 90 +
.../Windows/RegisterInfoWindows_i386.h | 27 +
.../Windows/RegisterInfoWindows_x86_64.cpp | 153 +
.../Windows/RegisterInfoWindows_x86_64.h | 28 +
.../Instruction/ARM64/TestAArch64Emulator.cpp | 4 +-
.../LoongArch/TestLoongArchEmulator.cpp | 4 +-
.../Instruction/RISCV/TestRISCVEmulator.cpp | 6 +-
.../RISCV/TestRiscvInstEmulation.cpp | 2 +-
.../ObjectFile/PECOFF/TestPECallFrameInfo.cpp | 2 +-
.../ObjectFile/PECOFF/TestSectionSize.cpp | 3 +-
.../Utility/RegisterInfoFreeBSDTest.cpp | 16 +-
.../Utility/RegisterInfoNetBSDTest_i386.cpp | 4 +-
.../Utility/RegisterInfoNetBSDTest_x86_64.cpp | 6 +-
.../Process/Utility/RegisterInfo_x86Test.cpp | 2 +-
.../minidump/RegisterContextMinidumpTest.cpp | 4 +-
.../Symbol/TestDWARFCallFrameInfo.cpp | 2 +-
.../ARM64/TestArm64InstEmulation.cpp | 1 +
.../PPC64/TestPPC64InstEmulation.cpp | 2 +-
.../source/Plugins/Process/Utility/BUILD.gn | 40 +-
.../secondary/lldb/source/Register/BUILD.gn | 37 +
163 files changed, 10017 insertions(+), 286 deletions(-)
rename lldb/source/{Plugins/Process/Utility => Register/Arch}/RegisterContext_mips.h (97%)
rename lldb/source/{Plugins/Process/Utility => Register/Arch}/RegisterContext_powerpc.h (92%)
rename lldb/source/{Plugins/Process/Utility => Register/Arch}/RegisterContext_s390x.h (93%)
rename lldb/source/{Plugins/Process/Utility => Register/Arch}/RegisterContext_x86.cpp (99%)
rename lldb/source/{Plugins/Process/Utility => Register/Arch}/RegisterContext_x86.h (99%)
rename lldb/source/{Plugins/Process/Utility => Register/Arch}/RegisterInfos_arm.h (100%)
rename lldb/source/{Plugins/Process/Utility => Register/Arch}/RegisterInfos_arm64.h (100%)
rename lldb/source/{Plugins/Process/Utility => Register/Arch}/RegisterInfos_arm64_sve.h (100%)
rename lldb/source/{Plugins/Process/Utility => Register/Arch}/RegisterInfos_i386.h (100%)
rename lldb/source/{Plugins/Process/Utility => Register/Arch}/RegisterInfos_loongarch64.h (99%)
rename lldb/source/{Plugins/Process/Utility => Register/Arch}/RegisterInfos_mips.h (100%)
rename lldb/source/{Plugins/Process/Utility => Register/Arch}/RegisterInfos_mips64.h (100%)
rename lldb/source/{Plugins/Process/Utility => Register/Arch}/RegisterInfos_powerpc.h (100%)
rename lldb/source/{Plugins/Process/Utility => Register/Arch}/RegisterInfos_ppc64.h (99%)
rename lldb/source/{Plugins/Process/Utility => Register/Arch}/RegisterInfos_ppc64le.h (99%)
create mode 100644 lldb/source/Register/Arch/RegisterInfos_riscv32.h
rename lldb/source/{Plugins/Process/Utility => Register/Arch}/RegisterInfos_riscv64.h (99%)
rename lldb/source/{Plugins/Process/Utility => Register/Arch}/RegisterInfos_s390x.h (100%)
rename lldb/source/{Plugins/Process/Utility => Register/Arch}/RegisterInfos_x86_64.h (100%)
rename lldb/source/{Plugins/Process/Utility => Register/Arch}/RegisterInfos_x86_64_with_base.h (99%)
rename lldb/source/{Plugins/Process/Utility => Register/Arch}/RegisterInfos_x86_64_with_base_shared.cpp (99%)
create mode 100644 lldb/source/Register/Arch/RegisterInfos_x86_64_with_base_shared.h
rename lldb/source/{Plugins/Process/Utility => Register/Arch}/lldb-arm-register-enums.h (94%)
rename lldb/source/{Plugins/Process/Utility => Register/Arch}/lldb-arm64-register-enums.h (95%)
rename lldb/source/{Plugins/Process/Utility => Register/Arch}/lldb-loongarch-register-enums.h (96%)
rename lldb/source/{Plugins/Process/Utility => Register/Arch}/lldb-ppc64-register-enums.h (94%)
rename lldb/source/{Plugins/Process/Utility => Register/Arch}/lldb-ppc64le-register-enums.h (95%)
create mode 100644 lldb/source/Register/Arch/lldb-riscv-register-enums.h
rename lldb/source/{Plugins/Process/Utility => Register/Arch}/lldb-s390x-register-enums.h (90%)
rename lldb/source/{Plugins/Process/Utility => Register/Arch}/lldb-x86-register-enums.h (98%)
create mode 100644 lldb/source/Register/CMakeLists.txt
rename lldb/source/{Plugins/Process/Utility => Register/Common}/RegisterInfoCommonDynamic_riscv32.cpp (97%)
rename lldb/source/{Plugins/Process/Utility => Register/Common}/RegisterInfoCommonDynamic_riscv32.h (89%)
create mode 100644 lldb/source/Register/Common/RegisterInfoCommon_arm.cpp
create mode 100644 lldb/source/Register/Common/RegisterInfoCommon_arm.h
create mode 100644 lldb/source/Register/Common/RegisterInfoCommon_arm64.cpp
create mode 100644 lldb/source/Register/Common/RegisterInfoCommon_arm64.h
create mode 100644 lldb/source/Register/Common/RegisterInfoCommon_loongarch64.cpp
create mode 100644 lldb/source/Register/Common/RegisterInfoCommon_loongarch64.h
create mode 100644 lldb/source/Register/Common/RegisterInfoCommon_ppc64.cpp
create mode 100644 lldb/source/Register/Common/RegisterInfoCommon_ppc64.h
create mode 100644 lldb/source/Register/Common/RegisterInfoCommon_ppc64le.cpp
create mode 100644 lldb/source/Register/Common/RegisterInfoCommon_ppc64le.h
create mode 100644 lldb/source/Register/Common/RegisterInfoCommon_riscv32.cpp
create mode 100644 lldb/source/Register/Common/RegisterInfoCommon_riscv32.h
create mode 100644 lldb/source/Register/Common/RegisterInfoCommon_riscv64.cpp
create mode 100644 lldb/source/Register/Common/RegisterInfoCommon_riscv64.h
rename lldb/source/{Plugins/Process/Utility => Register/Common}/RegisterTypeDetector_arm64.cpp (99%)
rename lldb/source/{Plugins/Process/Utility => Register/Common}/RegisterTypeDetector_arm64.h (96%)
create mode 100644 lldb/source/Register/FreeBSD/RegisterInfoFreeBSD_i386.cpp
create mode 100644 lldb/source/Register/FreeBSD/RegisterInfoFreeBSD_i386.h
create mode 100644 lldb/source/Register/FreeBSD/RegisterInfoFreeBSD_powerpc.cpp
create mode 100644 lldb/source/Register/FreeBSD/RegisterInfoFreeBSD_powerpc.h
create mode 100644 lldb/source/Register/FreeBSD/RegisterInfoFreeBSD_x86_64.cpp
create mode 100644 lldb/source/Register/FreeBSD/RegisterInfoFreeBSD_x86_64.h
create mode 100644 lldb/source/Register/Linux/RegisterInfoLinux_i386.cpp
create mode 100644 lldb/source/Register/Linux/RegisterInfoLinux_i386.h
create mode 100644 lldb/source/Register/Linux/RegisterInfoLinux_s390x.cpp
create mode 100644 lldb/source/Register/Linux/RegisterInfoLinux_s390x.h
create mode 100644 lldb/source/Register/Linux/RegisterInfoLinux_x86.h
create mode 100644 lldb/source/Register/Linux/RegisterInfoLinux_x86_64.cpp
create mode 100644 lldb/source/Register/Linux/RegisterInfoLinux_x86_64.h
create mode 100644 lldb/source/Register/NetBSD/RegisterInfoNetBSD_i386.cpp
create mode 100644 lldb/source/Register/NetBSD/RegisterInfoNetBSD_i386.h
create mode 100644 lldb/source/Register/NetBSD/RegisterInfoNetBSD_x86_64.cpp
create mode 100644 lldb/source/Register/NetBSD/RegisterInfoNetBSD_x86_64.h
create mode 100644 lldb/source/Register/OpenBSD/RegisterInfoOpenBSD_i386.cpp
create mode 100644 lldb/source/Register/OpenBSD/RegisterInfoOpenBSD_i386.h
create mode 100644 lldb/source/Register/OpenBSD/RegisterInfoOpenBSD_x86_64.cpp
create mode 100644 lldb/source/Register/OpenBSD/RegisterInfoOpenBSD_x86_64.h
rename lldb/source/{Plugins/Process/Utility => Register}/RegisterInfoAndSetInterface.h (84%)
rename lldb/source/{Plugins/Process/Utility => Register}/RegisterInfoInterface.h (91%)
create mode 100644 lldb/source/Register/Windows/RegisterInfoWindows_i386.cpp
create mode 100644 lldb/source/Register/Windows/RegisterInfoWindows_i386.h
create mode 100644 lldb/source/Register/Windows/RegisterInfoWindows_x86_64.cpp
create mode 100644 lldb/source/Register/Windows/RegisterInfoWindows_x86_64.h
create mode 100644 llvm/utils/gn/secondary/lldb/source/Register/BUILD.gn
diff --git a/lldb/source/CMakeLists.txt b/lldb/source/CMakeLists.txt
index ae02227ca35788..4125f32197b261 100644
--- a/lldb/source/CMakeLists.txt
+++ b/lldb/source/CMakeLists.txt
@@ -9,6 +9,7 @@ add_subdirectory(Expression)
add_subdirectory(Host)
add_subdirectory(Initialization)
add_subdirectory(Interpreter)
+add_subdirectory(Register)
add_subdirectory(Plugins)
add_subdirectory(Protocol)
add_subdirectory(Symbol)
diff --git a/lldb/source/Plugins/ABI/PowerPC/ABISysV_ppc64.cpp b/lldb/source/Plugins/ABI/PowerPC/ABISysV_ppc64.cpp
index 0895cd3d75df66..3c2b391cfb8699 100644
--- a/lldb/source/Plugins/ABI/PowerPC/ABISysV_ppc64.cpp
+++ b/lldb/source/Plugins/ABI/PowerPC/ABISysV_ppc64.cpp
@@ -38,11 +38,11 @@
#include "clang/AST/Decl.h"
#define DECLARE_REGISTER_INFOS_PPC64_STRUCT
-#include "Plugins/Process/Utility/RegisterInfos_ppc64.h"
+#include "Register/Arch/RegisterInfos_ppc64.h"
#undef DECLARE_REGISTER_INFOS_PPC64_STRUCT
#define DECLARE_REGISTER_INFOS_PPC64LE_STRUCT
-#include "Plugins/Process/Utility/RegisterInfos_ppc64le.h"
+#include "Register/Arch/RegisterInfos_ppc64le.h"
#undef DECLARE_REGISTER_INFOS_PPC64LE_STRUCT
#include <optional>
diff --git a/lldb/source/Plugins/Instruction/ARM64/EmulateInstructionARM64.cpp b/lldb/source/Plugins/Instruction/ARM64/EmulateInstructionARM64.cpp
index 4ef62bbfa2bc7a..78c51531260a8d 100644
--- a/lldb/source/Plugins/Instruction/ARM64/EmulateInstructionARM64.cpp
+++ b/lldb/source/Plugins/Instruction/ARM64/EmulateInstructionARM64.cpp
@@ -19,7 +19,7 @@
#include "Plugins/Process/Utility/ARMDefines.h"
#include "Plugins/Process/Utility/ARMUtils.h"
-#include "Plugins/Process/Utility/lldb-arm64-register-enums.h"
+#include "Register/Arch/lldb-arm64-register-enums.h"
#include <algorithm>
#include <cstdlib>
@@ -40,7 +40,7 @@
#define DECLARE_REGISTER_INFOS_ARM64_STRUCT
-#include "Plugins/Process/Utility/RegisterInfos_arm64.h"
+#include "Register/Arch/RegisterInfos_arm64.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/Support/MathExtras.h"
diff --git a/lldb/source/Plugins/Instruction/LoongArch/EmulateInstructionLoongArch.cpp b/lldb/source/Plugins/Instruction/LoongArch/EmulateInstructionLoongArch.cpp
index 5090ddf0b6d1e9..73041bbcad9c88 100644
--- a/lldb/source/Plugins/Instruction/LoongArch/EmulateInstructionLoongArch.cpp
+++ b/lldb/source/Plugins/Instruction/LoongArch/EmulateInstructionLoongArch.cpp
@@ -11,8 +11,8 @@
#include "EmulateInstructionLoongArch.h"
#include "Plugins/Process/Utility/InstructionUtils.h"
-#include "Plugins/Process/Utility/RegisterInfoCommon_loongarch64.h"
-#include "Plugins/Process/Utility/lldb-loongarch-register-enums.h"
+#include "Register/Common/RegisterInfoCommon_loongarch64.h"
+#include "Register/Arch/lldb-loongarch-register-enums.h"
#include "lldb/Core/Address.h"
#include "lldb/Core/PluginManager.h"
#include "lldb/Interpreter/OptionValueArray.h"
diff --git a/lldb/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp b/lldb/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp
index deaa2fdadd22ea..de158426064b9c 100644
--- a/lldb/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp
+++ b/lldb/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp
@@ -36,7 +36,7 @@
#include "llvm/ADT/STLExtras.h"
#include "Plugins/Process/Utility/InstructionUtils.h"
-#include "Plugins/Process/Utility/RegisterContext_mips.h"
+#include "Register/Arch/RegisterContext_mips.h"
using namespace lldb;
using namespace lldb_private;
diff --git a/lldb/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp b/lldb/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
index 57f04fb8d19b77..7d2ebd15632d0d 100644
--- a/lldb/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
+++ b/lldb/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
@@ -36,7 +36,7 @@
#include "llvm/ADT/STLExtras.h"
#include "Plugins/Process/Utility/InstructionUtils.h"
-#include "Plugins/Process/Utility/RegisterContext_mips.h"
+#include "Register/Arch/RegisterContext_mips.h"
using namespace lldb;
using namespace lldb_private;
diff --git a/lldb/source/Plugins/Instruction/PPC64/EmulateInstructionPPC64.cpp b/lldb/source/Plugins/Instruction/PPC64/EmulateInstructionPPC64.cpp
index 29516c57d2a204..299b61f774132b 100644
--- a/lldb/source/Plugins/Instruction/PPC64/EmulateInstructionPPC64.cpp
+++ b/lldb/source/Plugins/Instruction/PPC64/EmulateInstructionPPC64.cpp
@@ -11,7 +11,7 @@
#include <cstdlib>
#include <optional>
-#include "Plugins/Process/Utility/lldb-ppc64le-register-enums.h"
+#include "Register/Arch/lldb-ppc64le-register-enums.h"
#include "lldb/Core/PluginManager.h"
#include "lldb/Symbol/UnwindPlan.h"
#include "lldb/Utility/ArchSpec.h"
@@ -19,7 +19,7 @@
#include "lldb/Utility/LLDBLog.h"
#define DECLARE_REGISTER_INFOS_PPC64LE_STRUCT
-#include "Plugins/Process/Utility/RegisterInfos_ppc64le.h"
+#include "Register/Arch/RegisterInfos_ppc64le.h"
#include "Plugins/Process/Utility/InstructionUtils.h"
diff --git a/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp b/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
index ba6990ba235a7f..aff404caeac115 100644
--- a/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
+++ b/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
@@ -7,10 +7,10 @@
//===----------------------------------------------------------------------===//
#include "EmulateInstructionRISCV.h"
-#include "Plugins/Process/Utility/RegisterInfoInterface.h"
-#include "Plugins/Process/Utility/RegisterInfoCommon_riscv32.h"
-#include "Plugins/Process/Utility/RegisterInfoCommon_riscv64.h"
-#include "Plugins/Process/Utility/lldb-riscv-register-enums.h"
+#include "Register/RegisterInfoInterface.h"
+#include "Register/Common/RegisterInfoCommon_riscv32.h"
+#include "Register/Common/RegisterInfoCommon_riscv64.h"
+#include "Register/Arch/lldb-riscv-register-enums.h"
#include "RISCVCInstructions.h"
#include "RISCVInstructions.h"
diff --git a/lldb/source/Plugins/Instruction/RISCV/RISCVCInstructions.h b/lldb/source/Plugins/Instruction/RISCV/RISCVCInstructions.h
index 54140703d7049c..fee0da0b0c282e 100644
--- a/lldb/source/Plugins/Instruction/RISCV/RISCVCInstructions.h
+++ b/lldb/source/Plugins/Instruction/RISCV/RISCVCInstructions.h
@@ -12,7 +12,7 @@
#include <cstdint>
#include <variant>
-#include "Plugins/Process/Utility/lldb-riscv-register-enums.h"
+#include "Register/Arch/lldb-riscv-register-enums.h"
#include "RISCVInstructions.h"
namespace lldb_private {
diff --git a/lldb/source/Plugins/ObjectFile/PECOFF/PECallFrameInfo.cpp b/lldb/source/Plugins/ObjectFile/PECOFF/PECallFrameInfo.cpp
index 4b516b2e954bd6..6a312b39057e53 100644
--- a/lldb/source/Plugins/ObjectFile/PECOFF/PECallFrameInfo.cpp
+++ b/lldb/source/Plugins/ObjectFile/PECOFF/PECallFrameInfo.cpp
@@ -2,7 +2,7 @@
#include "ObjectFilePECOFF.h"
-#include "Plugins/Process/Utility/lldb-x86-register-enums.h"
+#include "Register/Arch/lldb-x86-register-enums.h"
#include "lldb/Symbol/UnwindPlan.h"
#include "llvm/Support/Win64EH.h"
diff --git a/lldb/source/Plugins/Platform/Linux/PlatformLinux.cpp b/lldb/source/Plugins/Platform/Linux/PlatformLinux.cpp
index eda300b21b981a..dab63b6becf7cb 100644
--- a/lldb/source/Plugins/Platform/Linux/PlatformLinux.cpp
+++ b/lldb/source/Plugins/Platform/Linux/PlatformLinux.cpp
@@ -15,7 +15,7 @@
#endif
#include "Plugins/Process/Utility/LinuxSignals.h"
-#include "Plugins/Process/Utility/lldb-riscv-register-enums.h"
+#include "Register/Arch/lldb-riscv-register-enums.h"
#include "Utility/ARM64_DWARF_Registers.h"
#include "lldb/Core/Debugger.h"
#include "lldb/Core/PluginManager.h"
diff --git a/lldb/source/Plugins/Process/AIX/NativeProcessAIX.cpp b/lldb/source/Plugins/Process/AIX/NativeProcessAIX.cpp
index 6d99c228575490..cfc78219dcd87d 100644
--- a/lldb/source/Plugins/Process/AIX/NativeProcessAIX.cpp
+++ b/lldb/source/Plugins/Process/AIX/NativeProcessAIX.cpp
@@ -27,7 +27,7 @@
#include <sys/ptrace.h>
#include <unistd.h>
#define DECLARE_REGISTER_INFOS_PPC64_STRUCT
-#include "Plugins/Process/Utility/RegisterInfos_ppc64.h"
+#include "Register/Arch/RegisterInfos_ppc64.h"
#undef DECLARE_REGISTER_INFOS_PPC64_STRUCT
using namespace lldb;
diff --git a/lldb/source/Plugins/Process/AIX/NativeRegisterContextAIX_ppc64.cpp b/lldb/source/Plugins/Process/AIX/NativeRegisterContextAIX_ppc64.cpp
index 0726e3ac779789..cc87f411e91c81 100644
--- a/lldb/source/Plugins/Process/AIX/NativeRegisterContextAIX_ppc64.cpp
+++ b/lldb/source/Plugins/Process/AIX/NativeRegisterContextAIX_ppc64.cpp
@@ -10,7 +10,7 @@
#include "NativeRegisterContextAIX_ppc64.h"
#include "NativeThreadAIX.h"
-#include "Plugins/Process/Utility/RegisterInfoCommon_ppc64.h"
+#include "Register/Common/RegisterInfoCommon_ppc64.h"
#include "lldb/Utility/RegisterValue.h"
using namespace lldb;
diff --git a/lldb/source/Plugins/Process/AIX/NativeRegisterContextAIX_ppc64.h b/lldb/source/Plugins/Process/AIX/NativeRegisterContextAIX_ppc64.h
index aa0a6b8549900c..c61d3133abdb87 100644
--- a/lldb/source/Plugins/Process/AIX/NativeRegisterContextAIX_ppc64.h
+++ b/lldb/source/Plugins/Process/AIX/NativeRegisterContextAIX_ppc64.h
@@ -12,10 +12,10 @@
#define LLDB_SOURCE_PLUGINS_PROCESS_AIX_NATIVEREGISTERCONTEXTAIX_PPC64_H
#include "Plugins/Process/AIX/NativeRegisterContextAIX.h"
-#include "Plugins/Process/Utility/lldb-ppc64-register-enums.h"
+#include "Register/Arch/lldb-ppc64-register-enums.h"
#define DECLARE_REGISTER_INFOS_PPC64_STRUCT
-#include "Plugins/Process/Utility/RegisterInfos_ppc64.h"
+#include "Register/Arch/RegisterInfos_ppc64.h"
#undef DECLARE_REGISTER_INFOS_PPC64_STRUCT
namespace lldb_private {
diff --git a/lldb/source/Plugins/Process/FreeBSD-Kernel-Core/RegisterContextFreeBSDKernelCore_arm.cpp b/lldb/source/Plugins/Process/FreeBSD-Kernel-Core/RegisterContextFreeBSDKernelCore_arm.cpp
index 621a7a314ab46c..e527ca6ab589cb 100644
--- a/lldb/source/Plugins/Process/FreeBSD-Kernel-Core/RegisterContextFreeBSDKernelCore_arm.cpp
+++ b/lldb/source/Plugins/Process/FreeBSD-Kernel-Core/RegisterContextFreeBSDKernelCore_arm.cpp
@@ -7,7 +7,7 @@
//===----------------------------------------------------------------------===//
#include "RegisterContextFreeBSDKernelCore_arm.h"
-#include "Plugins/Process/Utility/lldb-arm-register-enums.h"
+#include "Register/Arch/lldb-arm-register-enums.h"
#include "lldb/Target/Process.h"
#include "lldb/Target/Thread.h"
diff --git a/lldb/source/Plugins/Process/FreeBSD-Kernel-Core/RegisterContextFreeBSDKernelCore_arm64.cpp b/lldb/source/Plugins/Process/FreeBSD-Kernel-Core/RegisterContextFreeBSDKernelCore_arm64.cpp
index 3af209e406ae9a..42f81ef5542401 100644
--- a/lldb/source/Plugins/Process/FreeBSD-Kernel-Core/RegisterContextFreeBSDKernelCore_arm64.cpp
+++ b/lldb/source/Plugins/Process/FreeBSD-Kernel-Core/RegisterContextFreeBSDKernelCore_arm64.cpp
@@ -7,7 +7,7 @@
//===----------------------------------------------------------------------===//
#include "RegisterContextFreeBSDKernelCore_arm64.h"
-#include "Plugins/Process/Utility/lldb-arm64-register-enums.h"
+#include "Register/Arch/lldb-arm64-register-enums.h"
#include "lldb/Symbol/Symbol.h"
#include "lldb/Target/Process.h"
diff --git a/lldb/source/Plugins/Process/FreeBSD-Kernel-Core/ThreadFreeBSDKernelCore.cpp b/lldb/source/Plugins/Process/FreeBSD-Kernel-Core/ThreadFreeBSDKernelCore.cpp
index 4f0e7021d692db..0e415b6d03da95 100644
--- a/lldb/source/Plugins/Process/FreeBSD-Kernel-Core/ThreadFreeBSDKernelCore.cpp
+++ b/lldb/source/Plugins/Process/FreeBSD-Kernel-Core/ThreadFreeBSDKernelCore.cpp
@@ -12,12 +12,12 @@
#include "lldb/Target/Unwind.h"
#include "lldb/Utility/Log.h"
-#include "Plugins/Process/Utility/RegisterInfoFreeBSD_i386.h"
-#include "Plugins/Process/Utility/RegisterInfoFreeBSD_x86_64.h"
-#include "Plugins/Process/Utility/RegisterInfoCommon_arm.h"
-#include "Plugins/Process/Utility/RegisterInfoCommon_arm64.h"
-#include "Plugins/Process/Utility/RegisterInfoCommon_ppc64le.h"
-#include "Plugins/Process/Utility/RegisterInfoCommon_riscv64.h"
+#include "Register/FreeBSD/RegisterInfoFreeBSD_i386.h"
+#include "Register/FreeBSD/RegisterInfoFreeBSD_x86_64.h"
+#include "Register/Common/RegisterInfoCommon_arm.h"
+#include "Register/Common/RegisterInfoCommon_arm64.h"
+#include "Register/Common/RegisterInfoCommon_ppc64le.h"
+#include "Register/Common/RegisterInfoCommon_riscv64.h"
#include "ProcessFreeBSDKernelCore.h"
#include "RegisterContextFreeBSDKernelCore_arm.h"
#include "RegisterContextFreeBSDKernelCore_arm64.h"
diff --git a/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_arm.cpp b/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_arm.cpp
index fe4a6d3f104de0..1b0cb0b1cf930a 100644
--- a/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_arm.cpp
+++ b/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_arm.cpp
@@ -15,7 +15,7 @@
#include "lldb/Utility/Status.h"
#include "Plugins/Process/FreeBSD/NativeProcessFreeBSD.h"
-#include "Plugins/Process/Utility/RegisterInfoCommon_arm.h"
+#include "Register/Common/RegisterInfoCommon_arm.h"
// clang-format off
#include <sys/param.h>
diff --git a/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_arm.h b/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_arm.h
index eecc6b89502efc..5b9913fa6cbb4d 100644
--- a/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_arm.h
+++ b/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_arm.h
@@ -18,7 +18,7 @@
// clang-format on
#include "Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD.h"
-#include "Plugins/Process/Utility/RegisterInfoCommon_arm.h"
+#include "Register/Common/RegisterInfoCommon_arm.h"
#include <array>
diff --git a/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_arm64.cpp b/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_arm64.cpp
index f30dd262ebf1ff..8ecf690a48b2bc 100644
--- a/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_arm64.cpp
+++ b/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_arm64.cpp
@@ -16,8 +16,8 @@
#include "Plugins/Process/FreeBSD/NativeProcessFreeBSD.h"
#include "Plugins/Process/POSIX/ProcessPOSIXLog.h"
-#include "Plugins/Process/Utility/RegisterInfoCommon_arm64.h"
-#include "Plugins/Process/Utility/RegisterTypeDetector_arm64.h"
+#include "Register/Common/RegisterInfoCommon_arm64.h"
+#include "Register/Common/RegisterTypeDetector_arm64.h"
// clang-format off
#include <sys/param.h>
diff --git a/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_arm64.h b/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_arm64.h
index 613cfb761e52f7..b40507add17f3f 100644
--- a/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_arm64.h
+++ b/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_arm64.h
@@ -19,7 +19,7 @@
#include "Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD.h"
#include "Plugins/Process/Utility/NativeRegisterContextDBReg_arm64.h"
-#include "Plugins/Process/Utility/RegisterInfoCommon_arm64.h"
+#include "Register/Common/RegisterInfoCommon_arm64.h"
#include <array>
diff --git a/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_powerpc.h b/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_powerpc.h
index b0dcec4575de9d..632393704c8299 100644
--- a/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_powerpc.h
+++ b/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_powerpc.h
@@ -17,7 +17,7 @@
// clang-format on
#include "Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD.h"
-#include "Plugins/Process/Utility/RegisterInfoFreeBSD_powerpc.h"
+#include "Register/FreeBSD/RegisterInfoFreeBSD_powerpc.h"
#include <array>
#include <optional>
diff --git a/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_x86.cpp b/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_x86.cpp
index 50cea232972ceb..3359c59f88d8e2 100644
--- a/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_x86.cpp
+++ b/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_x86.cpp
@@ -23,8 +23,8 @@
#include "lldb/Utility/Status.h"
#include "NativeProcessFreeBSD.h"
-#include "Plugins/Process/Utility/RegisterInfoFreeBSD_i386.h"
-#include "Plugins/Process/Utility/RegisterInfoFreeBSD_x86_64.h"
+#include "Register/FreeBSD/RegisterInfoFreeBSD_i386.h"
+#include "Register/FreeBSD/RegisterInfoFreeBSD_x86_64.h"
#include <optional>
using namespace lldb_private;
diff --git a/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_x86.h b/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_x86.h
index cd519691eb5ad3..9d86935d13c32a 100644
--- a/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_x86.h
+++ b/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_x86.h
@@ -23,8 +23,8 @@
#include "Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD.h"
#include "Plugins/Process/Utility/NativeRegisterContextDBReg_x86.h"
-#include "Plugins/Process/Utility/RegisterContext_x86.h"
-#include "Plugins/Process/Utility/lldb-x86-register-enums.h"
+#include "Register/Arch/RegisterContext_x86.h"
+#include "Register/Arch/lldb-x86-register-enums.h"
#define LLDB_INVALID_XSAVE_OFFSET UINT32_MAX
diff --git a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm.cpp b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm.cpp
index 515b9ed9f1dcdc..5ea3f73f5228b2 100644
--- a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm.cpp
+++ b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm.cpp
@@ -13,7 +13,7 @@
#include "Plugins/Process/Linux/NativeProcessLinux.h"
#include "Plugins/Process/Linux/Procfs.h"
#include "Plugins/Process/POSIX/ProcessPOSIXLog.h"
-#include "Plugins/Process/Utility/RegisterInfoCommon_arm.h"
+#include "Register/Common/RegisterInfoCommon_arm.h"
#include "lldb/Host/HostInfo.h"
#include "lldb/Utility/DataBufferHeap.h"
#include "lldb/Utility/Log.h"
diff --git a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm.h b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm.h
index 1fea0aa4baf38f..949a27fc5c139e 100644
--- a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm.h
+++ b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm.h
@@ -13,8 +13,8 @@
#include "Plugins/Process/Linux/NativeRegisterContextLinux.h"
#include "Plugins/Process/Utility/NativeRegisterContextDBReg_arm.h"
-#include "Plugins/Process/Utility/RegisterInfoCommon_arm.h"
-#include "Plugins/Process/Utility/lldb-arm-register-enums.h"
+#include "Register/Common/RegisterInfoCommon_arm.h"
+#include "Register/Arch/lldb-arm-register-enums.h"
namespace lldb_private {
namespace process_linux {
diff --git a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
index 6a7a5d615a3a86..0c28881e5433e0 100644
--- a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
+++ b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.cpp
@@ -16,8 +16,8 @@
#include "Plugins/Process/Linux/Procfs.h"
#include "Plugins/Process/POSIX/ProcessPOSIXLog.h"
#include "Plugins/Process/Utility/MemoryTagManagerAArch64MTE.h"
-#include "Plugins/Process/Utility/RegisterInfoCommon_arm64.h"
-#include "Plugins/Process/Utility/RegisterTypeDetector_arm64.h"
+#include "Register/Common/RegisterInfoCommon_arm64.h"
+#include "Register/Common/RegisterTypeDetector_arm64.h"
#include "lldb/Host/HostInfo.h"
#include "lldb/Host/common/NativeProcessProtocol.h"
#include "lldb/Utility/DataBufferHeap.h"
diff --git a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
index 8dfc1f54c5dbdf..44d3b191d509a5 100644
--- a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
+++ b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
@@ -14,7 +14,7 @@
#include "Plugins/Process/Linux/NativeRegisterContextLinux.h"
#include "Plugins/Process/Utility/LinuxPTraceDefines_arm64sve.h"
#include "Plugins/Process/Utility/NativeRegisterContextDBReg_arm64.h"
-#include "Plugins/Process/Utility/RegisterInfoCommon_arm64.h"
+#include "Register/Common/RegisterInfoCommon_arm64.h"
#include "llvm/ADT/BitmaskEnum.h"
diff --git a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_loongarch64.cpp b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_loongarch64.cpp
index ed5da5c4b61965..52e3dad6bdfe4b 100644
--- a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_loongarch64.cpp
+++ b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_loongarch64.cpp
@@ -12,8 +12,8 @@
#include "Plugins/Process/Linux/NativeProcessLinux.h"
#include "Plugins/Process/Linux/Procfs.h"
-#include "Plugins/Process/Utility/RegisterInfoCommon_loongarch64.h"
-#include "Plugins/Process/Utility/lldb-loongarch-register-enums.h"
+#include "Register/Common/RegisterInfoCommon_loongarch64.h"
+#include "Register/Arch/lldb-loongarch-register-enums.h"
#include "lldb/Host/HostInfo.h"
#include "lldb/Utility/DataBufferHeap.h"
#include "lldb/Utility/Log.h"
diff --git a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_loongarch64.h b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_loongarch64.h
index fc6bb05211c7da..1ee8ffa8681f23 100644
--- a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_loongarch64.h
+++ b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_loongarch64.h
@@ -13,7 +13,7 @@
#include "Plugins/Process/Linux/NativeRegisterContextLinux.h"
#include "Plugins/Process/Utility/NativeRegisterContextDBReg_loongarch.h"
-#include "Plugins/Process/Utility/RegisterInfoCommon_loongarch64.h"
+#include "Register/Common/RegisterInfoCommon_loongarch64.h"
#include <asm/ptrace.h>
diff --git a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_ppc64le.cpp b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_ppc64le.cpp
index b58954510a40ba..d1df65952ccaec 100644
--- a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_ppc64le.cpp
+++ b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_ppc64le.cpp
@@ -16,7 +16,7 @@
#include "Plugins/Process/Linux/NativeProcessLinux.h"
#include "Plugins/Process/Linux/Procfs.h"
#include "Plugins/Process/POSIX/ProcessPOSIXLog.h"
-#include "Plugins/Process/Utility/RegisterInfoCommon_ppc64le.h"
+#include "Register/Common/RegisterInfoCommon_ppc64le.h"
#include "lldb/Host/HostInfo.h"
#include "lldb/Host/common/NativeProcessProtocol.h"
#include "lldb/Utility/DataBufferHeap.h"
diff --git a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_ppc64le.h b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_ppc64le.h
index 4ca9d43a249267..d8ad09e8dc5116 100644
--- a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_ppc64le.h
+++ b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_ppc64le.h
@@ -15,10 +15,10 @@
#define lldb_NativeRegisterContextLinux_ppc64le_h
#include "Plugins/Process/Linux/NativeRegisterContextLinux.h"
-#include "Plugins/Process/Utility/lldb-ppc64le-register-enums.h"
+#include "Register/Arch/lldb-ppc64le-register-enums.h"
#define DECLARE_REGISTER_INFOS_PPC64LE_STRUCT
-#include "Plugins/Process/Utility/RegisterInfos_ppc64le.h"
+#include "Register/Arch/RegisterInfos_ppc64le.h"
#undef DECLARE_REGISTER_INFOS_PPC64LE_STRUCT
namespace lldb_private {
diff --git a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_riscv64.cpp b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_riscv64.cpp
index 43cc522eff0367..294fff439589ac 100644
--- a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_riscv64.cpp
+++ b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_riscv64.cpp
@@ -12,8 +12,8 @@
#include "Plugins/Process/Linux/NativeProcessLinux.h"
#include "Plugins/Process/Linux/Procfs.h"
-#include "Plugins/Process/Utility/RegisterInfoCommon_riscv64.h"
-#include "Plugins/Process/Utility/lldb-riscv-register-enums.h"
+#include "Register/Common/RegisterInfoCommon_riscv64.h"
+#include "Register/Arch/lldb-riscv-register-enums.h"
#include "lldb/Host/HostInfo.h"
#include "lldb/Utility/DataBufferHeap.h"
#include "lldb/Utility/Log.h"
diff --git a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_riscv64.h b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_riscv64.h
index d5df762c9bee63..bd0048bb315579 100644
--- a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_riscv64.h
+++ b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_riscv64.h
@@ -12,7 +12,7 @@
#define lldb_NativeRegisterContextLinux_riscv64_h
#include "Plugins/Process/Linux/NativeRegisterContextLinux.h"
-#include "Plugins/Process/Utility/RegisterInfoCommon_riscv64.h"
+#include "Register/Common/RegisterInfoCommon_riscv64.h"
#include <asm/ptrace.h>
diff --git a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_s390x.cpp b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_s390x.cpp
index 1851eb21c6351e..d56fe891d37920 100644
--- a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_s390x.cpp
+++ b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_s390x.cpp
@@ -10,7 +10,7 @@
#include "NativeRegisterContextLinux_s390x.h"
#include "Plugins/Process/Linux/NativeProcessLinux.h"
-#include "Plugins/Process/Utility/RegisterInfoLinux_s390x.h"
+#include "Register/Linux/RegisterInfoLinux_s390x.h"
#include "lldb/Host/HostInfo.h"
#include "lldb/Utility/DataBufferHeap.h"
#include "lldb/Utility/Log.h"
diff --git a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_s390x.h b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_s390x.h
index 4b97fc89c3482b..23ea6db981241d 100644
--- a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_s390x.h
+++ b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_s390x.h
@@ -12,8 +12,8 @@
#define lldb_NativeRegisterContextLinux_s390x_h
#include "Plugins/Process/Linux/NativeRegisterContextLinux.h"
-#include "Plugins/Process/Utility/RegisterContext_s390x.h"
-#include "Plugins/Process/Utility/lldb-s390x-register-enums.h"
+#include "Register/Arch/RegisterContext_s390x.h"
+#include "Register/Arch/lldb-s390x-register-enums.h"
#include <asm/ptrace.h>
namespace lldb_private {
diff --git a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86.cpp b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86.cpp
index 1ab29f277b70a5..0d6356c75bd500 100644
--- a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86.cpp
+++ b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86.cpp
@@ -12,8 +12,8 @@
#include "Plugins/Process/Linux/NativeProcessLinux.h"
#include "Plugins/Process/Linux/NativeThreadLinux.h"
-#include "Plugins/Process/Utility/RegisterInfoLinux_i386.h"
-#include "Plugins/Process/Utility/RegisterInfoLinux_x86_64.h"
+#include "Register/Linux/RegisterInfoLinux_i386.h"
+#include "Register/Linux/RegisterInfoLinux_x86_64.h"
#include "lldb/Host/HostInfo.h"
#include "lldb/Utility/DataBufferHeap.h"
#include "lldb/Utility/Log.h"
diff --git a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86.h b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86.h
index 92793118939105..b58ae5bebe95fa 100644
--- a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86.h
+++ b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86.h
@@ -13,9 +13,9 @@
#include "Plugins/Process/Linux/NativeRegisterContextLinux.h"
#include "Plugins/Process/Utility/NativeRegisterContextDBReg_x86.h"
-#include "Plugins/Process/Utility/RegisterInfoLinux_x86.h"
-#include "Plugins/Process/Utility/RegisterContext_x86.h"
-#include "Plugins/Process/Utility/lldb-x86-register-enums.h"
+#include "Register/Linux/RegisterInfoLinux_x86.h"
+#include "Register/Arch/RegisterContext_x86.h"
+#include "Register/Arch/lldb-x86-register-enums.h"
#include <optional>
#include <sys/uio.h>
diff --git a/lldb/source/Plugins/Process/NetBSD/NativeRegisterContextNetBSD_x86.cpp b/lldb/source/Plugins/Process/NetBSD/NativeRegisterContextNetBSD_x86.cpp
index 55f13bda25ce20..b8f7bffbbf69f7 100644
--- a/lldb/source/Plugins/Process/NetBSD/NativeRegisterContextNetBSD_x86.cpp
+++ b/lldb/source/Plugins/Process/NetBSD/NativeRegisterContextNetBSD_x86.cpp
@@ -16,8 +16,8 @@
#include "lldb/Utility/RegisterValue.h"
#include "lldb/Utility/Status.h"
-#include "Plugins/Process/Utility/RegisterInfoNetBSD_i386.h"
-#include "Plugins/Process/Utility/RegisterInfoNetBSD_x86_64.h"
+#include "Register/NetBSD/RegisterInfoNetBSD_i386.h"
+#include "Register/NetBSD/RegisterInfoNetBSD_x86_64.h"
// clang-format off
#include <sys/types.h>
diff --git a/lldb/source/Plugins/Process/NetBSD/NativeRegisterContextNetBSD_x86.h b/lldb/source/Plugins/Process/NetBSD/NativeRegisterContextNetBSD_x86.h
index 10f11bd92db820..dba5ac78f67d39 100644
--- a/lldb/source/Plugins/Process/NetBSD/NativeRegisterContextNetBSD_x86.h
+++ b/lldb/source/Plugins/Process/NetBSD/NativeRegisterContextNetBSD_x86.h
@@ -22,9 +22,9 @@
#include <optional>
#include "Plugins/Process/NetBSD/NativeRegisterContextNetBSD.h"
-#include "Plugins/Process/Utility/RegisterContext_x86.h"
+#include "Register/Arch/RegisterContext_x86.h"
#include "Plugins/Process/Utility/NativeRegisterContextDBReg_x86.h"
-#include "Plugins/Process/Utility/lldb-x86-register-enums.h"
+#include "Register/Arch/lldb-x86-register-enums.h"
namespace lldb_private {
namespace process_netbsd {
diff --git a/lldb/source/Plugins/Process/Utility/CMakeLists.txt b/lldb/source/Plugins/Process/Utility/CMakeLists.txt
index 43bd2848c34b59..19a65bfa4fde1f 100644
--- a/lldb/source/Plugins/Process/Utility/CMakeLists.txt
+++ b/lldb/source/Plugins/Process/Utility/CMakeLists.txt
@@ -1,43 +1,7 @@
# TODO: Clean up this directory and its dependencies
set_property(DIRECTORY PROPERTY LLDB_PLUGIN_KIND ProcessUtility)
-add_lldb_library(lldbRegister NO_PLUGIN_DEPENDENCIES
- PARTIAL_SOURCES_INTENDED
- RegisterContext_x86.cpp
- RegisterInfoFreeBSD_i386.cpp
- RegisterInfoFreeBSD_powerpc.cpp
- RegisterInfoFreeBSD_x86_64.cpp
- RegisterInfoLinux_i386.cpp
- RegisterInfoLinux_x86_64.cpp
- RegisterInfoLinux_s390x.cpp
- RegisterInfoNetBSD_i386.cpp
- RegisterInfoNetBSD_x86_64.cpp
- RegisterInfoOpenBSD_i386.cpp
- RegisterInfoOpenBSD_x86_64.cpp
- RegisterInfoWindows_i386.cpp
- RegisterInfoWindows_x86_64.cpp
- RegisterTypeDetector_arm64.cpp
- RegisterInfos_x86_64_with_base_shared.cpp
- RegisterInfoCommon_arm.cpp
- RegisterInfoCommon_arm64.cpp
- RegisterInfoCommon_loongarch64.cpp
- RegisterInfoCommon_ppc64le.cpp
- RegisterInfoCommon_ppc64.cpp
- RegisterInfoCommon_riscv32.cpp
- RegisterInfoCommon_riscv64.cpp
- RegisterInfoCommonDynamic_riscv32.cpp
-
- LINK_COMPONENTS
- Support
- TargetParser
- LINK_LIBS
- lldbUtility
- ALLOWED_INTERNAL_DEPENDENCIES
- lldbUtility
- )
-
add_lldb_library(lldbPluginProcessUtility
- PARTIAL_SOURCES_INTENDED
AuxVector.cpp
FreeBSDSignals.cpp
GDBRemoteSignals.cpp
diff --git a/lldb/source/Plugins/Process/Utility/NativeRegisterContextDBReg_x86.cpp b/lldb/source/Plugins/Process/Utility/NativeRegisterContextDBReg_x86.cpp
index 3038cbcb723718..ed927691629e8e 100644
--- a/lldb/source/Plugins/Process/Utility/NativeRegisterContextDBReg_x86.cpp
+++ b/lldb/source/Plugins/Process/Utility/NativeRegisterContextDBReg_x86.cpp
@@ -10,7 +10,7 @@
#include "lldb/Utility/LLDBLog.h"
#include "lldb/Utility/RegisterValue.h"
-#include "Plugins/Process/Utility/lldb-x86-register-enums.h"
+#include "Register/Arch/lldb-x86-register-enums.h"
using namespace lldb_private;
diff --git a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_ppc64le.h b/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_ppc64le.h
index 66794ec9e9cabe..65209179596295 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_ppc64le.h
+++ b/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_ppc64le.h
@@ -9,7 +9,7 @@
#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTPOSIX_PPC64LE_H
#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTPOSIX_PPC64LE_H
-#include "Plugins/Process/Utility/lldb-ppc64le-register-enums.h"
+#include "Register/Arch/lldb-ppc64le-register-enums.h"
#include "RegisterInfoInterface.h"
#include "Utility/PPC64LE_DWARF_Registers.h"
#include "lldb/Target/RegisterContext.h"
diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfos_x86_64_with_base_shared.h b/lldb/source/Plugins/Process/Utility/RegisterInfos_x86_64_with_base_shared.h
index efd6ab542016d4..a0562c8d94ceb9 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterInfos_x86_64_with_base_shared.h
+++ b/lldb/source/Plugins/Process/Utility/RegisterInfos_x86_64_with_base_shared.h
@@ -1,11 +1,11 @@
-//===-- RegisterInfos_x86_64_with_base_shared.h -----------------*- C++ -*-===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-
+ //===-- RegisterInfos_x86_64_with_base_shared.h -----------------*- C++ -*-===//
+ //
+ // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+ // See https://llvm.org/LICENSE.txt for license information.
+ // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+ //
+ //===----------------------------------------------------------------------===//
+
#ifndef lldb_RegisterInfos_x86_64_with_base_shared_h
#define lldb_RegisterInfos_x86_64_with_base_shared_h
diff --git a/lldb/source/Plugins/Process/Windows/Common/NativeRegisterContextWindows_WoW64.cpp b/lldb/source/Plugins/Process/Windows/Common/NativeRegisterContextWindows_WoW64.cpp
index b188bf979a01b4..f6a155f9ba8f97 100644
--- a/lldb/source/Plugins/Process/Windows/Common/NativeRegisterContextWindows_WoW64.cpp
+++ b/lldb/source/Plugins/Process/Windows/Common/NativeRegisterContextWindows_WoW64.cpp
@@ -11,7 +11,7 @@
#include "NativeRegisterContextWindows_WoW64.h"
#include "NativeThreadWindows.h"
-#include "Plugins/Process/Utility/RegisterInfoWindows_i386.h"
+#include "Register/Windows/RegisterInfoWindows_i386.h"
#include "ProcessWindowsLog.h"
#include "lldb/Host/HostInfo.h"
#include "lldb/Host/HostThread.h"
diff --git a/lldb/source/Plugins/Process/Windows/Common/NativeRegisterContextWindows_WoW64.h b/lldb/source/Plugins/Process/Windows/Common/NativeRegisterContextWindows_WoW64.h
index 213826ac7feda9..fa22c59f7c3ac1 100644
--- a/lldb/source/Plugins/Process/Windows/Common/NativeRegisterContextWindows_WoW64.h
+++ b/lldb/source/Plugins/Process/Windows/Common/NativeRegisterContextWindows_WoW64.h
@@ -10,8 +10,8 @@
#ifndef liblldb_NativeRegisterContextWindows_WoW64_h_
#define liblldb_NativeRegisterContextWindows_WoW64_h_
-#include "Plugins/Process/Utility/RegisterContext_x86.h"
-#include "Plugins/Process/Utility/lldb-x86-register-enums.h"
+#include "Register/Arch/RegisterContext_x86.h"
+#include "Register/Arch/lldb-x86-register-enums.h"
#include "NativeRegisterContextWindows.h"
diff --git a/lldb/source/Plugins/Process/Windows/Common/NativeRegisterContextWindows_arm.cpp b/lldb/source/Plugins/Process/Windows/Common/NativeRegisterContextWindows_arm.cpp
index f4f52f7193bf12..28181ca089303b 100644
--- a/lldb/source/Plugins/Process/Windows/Common/NativeRegisterContextWindows_arm.cpp
+++ b/lldb/source/Plugins/Process/Windows/Common/NativeRegisterContextWindows_arm.cpp
@@ -10,7 +10,7 @@
#include "NativeRegisterContextWindows_arm.h"
#include "NativeThreadWindows.h"
-#include "Plugins/Process/Utility/RegisterInfoCommon_arm.h"
+#include "Register/Common/RegisterInfoCommon_arm.h"
#include "ProcessWindowsLog.h"
#include "lldb/Host/HostInfo.h"
#include "lldb/Host/HostThread.h"
diff --git a/lldb/source/Plugins/Process/Windows/Common/NativeRegisterContextWindows_arm.h b/lldb/source/Plugins/Process/Windows/Common/NativeRegisterContextWindows_arm.h
index d8e8e81dde13d0..62464c60e253e2 100644
--- a/lldb/source/Plugins/Process/Windows/Common/NativeRegisterContextWindows_arm.h
+++ b/lldb/source/Plugins/Process/Windows/Common/NativeRegisterContextWindows_arm.h
@@ -10,7 +10,7 @@
#ifndef liblldb_NativeRegisterContextWindows_arm_h_
#define liblldb_NativeRegisterContextWindows_arm_h_
-#include "Plugins/Process/Utility/lldb-arm-register-enums.h"
+#include "Register/Arch/lldb-arm-register-enums.h"
#include "NativeRegisterContextWindows.h"
diff --git a/lldb/source/Plugins/Process/Windows/Common/NativeRegisterContextWindows_arm64.h b/lldb/source/Plugins/Process/Windows/Common/NativeRegisterContextWindows_arm64.h
index ec9e3e74ad3cf1..970d4ce26c61f4 100644
--- a/lldb/source/Plugins/Process/Windows/Common/NativeRegisterContextWindows_arm64.h
+++ b/lldb/source/Plugins/Process/Windows/Common/NativeRegisterContextWindows_arm64.h
@@ -13,8 +13,8 @@
#include "NativeRegisterContextWindows.h"
#include "Plugins/Process/Utility/NativeRegisterContextDBReg_arm64.h"
-#include "Plugins/Process/Utility/RegisterInfoCommon_arm64.h"
-#include "Plugins/Process/Utility/lldb-arm64-register-enums.h"
+#include "Register/Common/RegisterInfoCommon_arm64.h"
+#include "Register/Arch/lldb-arm64-register-enums.h"
#include "lldb/Host/windows/windows.h"
diff --git a/lldb/source/Plugins/Process/Windows/Common/NativeRegisterContextWindows_i386.cpp b/lldb/source/Plugins/Process/Windows/Common/NativeRegisterContextWindows_i386.cpp
index 940ae503a97c8c..563d54385f0807 100644
--- a/lldb/source/Plugins/Process/Windows/Common/NativeRegisterContextWindows_i386.cpp
+++ b/lldb/source/Plugins/Process/Windows/Common/NativeRegisterContextWindows_i386.cpp
@@ -11,7 +11,7 @@
#include "NativeRegisterContextWindows_i386.h"
#include "NativeThreadWindows.h"
-#include "Plugins/Process/Utility/RegisterInfoWindows_i386.h"
+#include "Register/Windows/RegisterInfoWindows_i386.h"
#include "ProcessWindowsLog.h"
#include "lldb/Host/HostInfo.h"
#include "lldb/Host/HostThread.h"
diff --git a/lldb/source/Plugins/Process/Windows/Common/NativeRegisterContextWindows_i386.h b/lldb/source/Plugins/Process/Windows/Common/NativeRegisterContextWindows_i386.h
index 325fbc35d3482d..be589fc6992cdb 100644
--- a/lldb/source/Plugins/Process/Windows/Common/NativeRegisterContextWindows_i386.h
+++ b/lldb/source/Plugins/Process/Windows/Common/NativeRegisterContextWindows_i386.h
@@ -10,8 +10,8 @@
#ifndef liblldb_NativeRegisterContextWindows_i386_h_
#define liblldb_NativeRegisterContextWindows_i386_h_
-#include "Plugins/Process/Utility/RegisterContext_x86.h"
-#include "Plugins/Process/Utility/lldb-x86-register-enums.h"
+#include "Register/Arch/RegisterContext_x86.h"
+#include "Register/Arch/lldb-x86-register-enums.h"
#include "NativeRegisterContextWindows.h"
diff --git a/lldb/source/Plugins/Process/Windows/Common/NativeRegisterContextWindows_x86_64.cpp b/lldb/source/Plugins/Process/Windows/Common/NativeRegisterContextWindows_x86_64.cpp
index 0695a42fc1848a..bb244e4ac1a638 100644
--- a/lldb/source/Plugins/Process/Windows/Common/NativeRegisterContextWindows_x86_64.cpp
+++ b/lldb/source/Plugins/Process/Windows/Common/NativeRegisterContextWindows_x86_64.cpp
@@ -11,8 +11,8 @@
#include "NativeRegisterContextWindows_x86_64.h"
#include "NativeRegisterContextWindows_WoW64.h"
#include "NativeThreadWindows.h"
-#include "Plugins/Process/Utility/RegisterInfoWindows_i386.h"
-#include "Plugins/Process/Utility/RegisterInfoWindows_x86_64.h"
+#include "Register/Windows/RegisterInfoWindows_i386.h"
+#include "Register/Windows/RegisterInfoWindows_x86_64.h"
#include "ProcessWindowsLog.h"
#include "lldb/Host/HostInfo.h"
#include "lldb/Host/HostThread.h"
diff --git a/lldb/source/Plugins/Process/Windows/Common/NativeRegisterContextWindows_x86_64.h b/lldb/source/Plugins/Process/Windows/Common/NativeRegisterContextWindows_x86_64.h
index 1eea8fbaa2e1cb..52bc7085210573 100644
--- a/lldb/source/Plugins/Process/Windows/Common/NativeRegisterContextWindows_x86_64.h
+++ b/lldb/source/Plugins/Process/Windows/Common/NativeRegisterContextWindows_x86_64.h
@@ -10,8 +10,8 @@
#ifndef liblldb_NativeRegisterContextWindows_x86_64_h_
#define liblldb_NativeRegisterContextWindows_x86_64_h_
-#include "Plugins/Process/Utility/RegisterContext_x86.h"
-#include "Plugins/Process/Utility/lldb-x86-register-enums.h"
+#include "Register/Arch/RegisterContext_x86.h"
+#include "Register/Arch/lldb-x86-register-enums.h"
#include "NativeRegisterContextWindows.h"
diff --git a/lldb/source/Plugins/Process/Windows/Common/arm/RegisterContextWindows_arm.cpp b/lldb/source/Plugins/Process/Windows/Common/arm/RegisterContextWindows_arm.cpp
index a31a299c337899..1c2a7b77f16cd6 100644
--- a/lldb/source/Plugins/Process/Windows/Common/arm/RegisterContextWindows_arm.cpp
+++ b/lldb/source/Plugins/Process/Windows/Common/arm/RegisterContextWindows_arm.cpp
@@ -38,7 +38,7 @@ using namespace lldb_private;
// Include RegisterInfos_arm to declare our g_register_infos_arm structure.
#define DECLARE_REGISTER_INFOS_ARM_STRUCT
-#include "Plugins/Process/Utility/RegisterInfos_arm.h"
+#include "Register/Arch/RegisterInfos_arm.h"
#undef DECLARE_REGISTER_INFOS_ARM_STRUCT
static size_t k_num_register_infos = std::size(g_register_infos_arm);
diff --git a/lldb/source/Plugins/Process/Windows/Common/arm64/RegisterContextWindows_arm64.cpp b/lldb/source/Plugins/Process/Windows/Common/arm64/RegisterContextWindows_arm64.cpp
index 33bb0712d4b5e4..38ebf8fb80466f 100644
--- a/lldb/source/Plugins/Process/Windows/Common/arm64/RegisterContextWindows_arm64.cpp
+++ b/lldb/source/Plugins/Process/Windows/Common/arm64/RegisterContextWindows_arm64.cpp
@@ -39,7 +39,7 @@ using namespace lldb_private;
// Include RegisterInfos_arm64 to declare our g_register_infos_arm64 structure.
#define DECLARE_REGISTER_INFOS_ARM64_STRUCT
-#include "Plugins/Process/Utility/RegisterInfos_arm64.h"
+#include "Register/Arch/RegisterInfos_arm64.h"
#undef DECLARE_REGISTER_INFOS_ARM64_STRUCT
static size_t k_num_register_infos = std::size(g_register_infos_arm64_le);
diff --git a/lldb/source/Plugins/Process/Windows/Common/x64/RegisterContextWindows_x64.cpp b/lldb/source/Plugins/Process/Windows/Common/x64/RegisterContextWindows_x64.cpp
index ae1e7a47e92bc2..25d7bdbc81b10b 100644
--- a/lldb/source/Plugins/Process/Windows/Common/x64/RegisterContextWindows_x64.cpp
+++ b/lldb/source/Plugins/Process/Windows/Common/x64/RegisterContextWindows_x64.cpp
@@ -14,8 +14,8 @@
#include "lldb/Utility/Status.h"
#include "lldb/lldb-private-types.h"
-#include "Plugins/Process/Utility/RegisterContext_x86.h"
-#include "Plugins/Process/Utility/lldb-x86-register-enums.h"
+#include "Register/Arch/RegisterContext_x86.h"
+#include "Register/Arch/lldb-x86-register-enums.h"
#include "ProcessWindowsLog.h"
#include "RegisterContextWindows_x64.h"
#include "TargetThreadWindows.h"
diff --git a/lldb/source/Plugins/Process/Windows/Common/x86/RegisterContextWindows_x86.cpp b/lldb/source/Plugins/Process/Windows/Common/x86/RegisterContextWindows_x86.cpp
index 3613120f5e3b9c..4d3ef9588b09dc 100644
--- a/lldb/source/Plugins/Process/Windows/Common/x86/RegisterContextWindows_x86.cpp
+++ b/lldb/source/Plugins/Process/Windows/Common/x86/RegisterContextWindows_x86.cpp
@@ -16,9 +16,9 @@
#include "ProcessWindowsLog.h"
#include "RegisterContextWindows_x86.h"
-#include "Plugins/Process/Utility/RegisterContext_x86.h"
+#include "Register/Arch/RegisterContext_x86.h"
#include "TargetThreadWindows.h"
-#include "Plugins/Process/Utility/lldb-x86-register-enums.h"
+#include "Register/Arch/lldb-x86-register-enums.h"
#include "llvm/ADT/STLExtras.h"
diff --git a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.cpp b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.cpp
index f910f62fb92a03..f1e90318a42279 100644
--- a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.cpp
+++ b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.cpp
@@ -7,10 +7,10 @@
//===----------------------------------------------------------------------===//
#include "RegisterContextPOSIXCore_arm64.h"
-#include "Plugins/Process/Utility/RegisterInfoCommon_arm64.h"
+#include "Register/Common/RegisterInfoCommon_arm64.h"
#include "Plugins/Process/Utility/AuxVector.h"
-#include "Plugins/Process/Utility/RegisterTypeDetector_arm64.h"
+#include "Register/Common/RegisterTypeDetector_arm64.h"
#include "Plugins/Process/elf-core/ProcessElfCore.h"
#include "Plugins/Process/elf-core/RegisterUtilities.h"
#include "lldb/Target/Thread.h"
diff --git a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.h b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.h
index 2499556e203d4d..c9314b6b7ea1d2 100644
--- a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.h
+++ b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.h
@@ -11,7 +11,7 @@
#include "Plugins/Process/Utility/LinuxPTraceDefines_arm64sve.h"
#include "Plugins/Process/Utility/RegisterContextPOSIX_arm64.h"
-#include "Plugins/Process/Utility/RegisterTypeDetector_arm64.h"
+#include "Register/Common/RegisterTypeDetector_arm64.h"
#include "Plugins/Process/elf-core/RegisterUtilities.h"
#include "lldb/Utility/DataBufferHeap.h"
diff --git a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_loongarch64.h b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_loongarch64.h
index 63b97551bbbeed..a12a23adf89dd0 100644
--- a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_loongarch64.h
+++ b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_loongarch64.h
@@ -10,7 +10,7 @@
#define LLDB_SOURCE_PLUGINS_PROCESS_ELF_CORE_REGISTERCONTEXTPOSIXCORE_LOONGARCH64_H
#include "Plugins/Process/Utility/RegisterContextPOSIX_loongarch64.h"
-#include "Plugins/Process/Utility/RegisterInfoCommon_loongarch64.h"
+#include "Register/Common/RegisterInfoCommon_loongarch64.h"
#include "Plugins/Process/elf-core/RegisterUtilities.h"
#include "lldb/Target/Thread.h"
diff --git a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_ppc64le.cpp b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_ppc64le.cpp
index d44fb399e18a74..4f0f46b2213c45 100644
--- a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_ppc64le.cpp
+++ b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_ppc64le.cpp
@@ -12,7 +12,7 @@
#include "lldb/Utility/DataBufferHeap.h"
#include "lldb/Utility/RegisterValue.h"
-#include "Plugins/Process/Utility/lldb-ppc64le-register-enums.h"
+#include "Register/Arch/lldb-ppc64le-register-enums.h"
#include "Plugins/Process/elf-core/RegisterUtilities.h"
#include <memory>
diff --git a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv32.cpp b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv32.cpp
index a52d99c2791ab6..07bedccd01f2d6 100644
--- a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv32.cpp
+++ b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv32.cpp
@@ -20,7 +20,7 @@
#define FPR_OFFSET(idx) ((idx) * sizeof(uint32_t))
#define DECLARE_REGISTER_INFOS_RISCV32_STRUCT
-#include "Plugins/Process/Utility/RegisterInfos_riscv32.h"
+#include "Register/Arch/RegisterInfos_riscv32.h"
#undef DECLARE_REGISTER_INFOS_RISCV32_STRUCT
using namespace lldb_private;
diff --git a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv32.h b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv32.h
index 6f154bcfbceb99..4cae36cf319e39 100644
--- a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv32.h
+++ b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv32.h
@@ -9,7 +9,7 @@
#ifndef LLDB_SOURCE_PLUGINS_PROCESS_ELF_CORE_REGISTERCONTEXTPOSIXCORE_RISCV32_H
#define LLDB_SOURCE_PLUGINS_PROCESS_ELF_CORE_REGISTERCONTEXTPOSIXCORE_RISCV32_H
-#include "Plugins/Process/Utility/RegisterInfoCommonDynamic_riscv32.h"
+#include "Register/Common/RegisterInfoCommonDynamic_riscv32.h"
#include "Plugins/Process/elf-core/RegisterUtilities.h"
#include "lldb/Target/Thread.h"
#include "lldb/Utility/DataExtractor.h"
diff --git a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv64.h b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv64.h
index 9a0153d78d867f..22a67654bbc790 100644
--- a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv64.h
+++ b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv64.h
@@ -10,7 +10,7 @@
#define LLDB_SOURCE_PLUGINS_PROCESS_ELF_CORE_REGISTERCONTEXTPOSIXCORE_RISCV64_H
#include "Plugins/Process/Utility/RegisterContextPOSIX_riscv64.h"
-#include "Plugins/Process/Utility/RegisterInfoCommon_riscv64.h"
+#include "Register/Common/RegisterInfoCommon_riscv64.h"
#include "Plugins/Process/elf-core/RegisterUtilities.h"
#include "lldb/Target/Thread.h"
diff --git a/lldb/source/Plugins/Process/elf-core/ThreadElfCore.cpp b/lldb/source/Plugins/Process/elf-core/ThreadElfCore.cpp
index f024211abc2b6d..6372eff29de97d 100644
--- a/lldb/source/Plugins/Process/elf-core/ThreadElfCore.cpp
+++ b/lldb/source/Plugins/Process/elf-core/ThreadElfCore.cpp
@@ -16,19 +16,19 @@
#include "lldb/Utility/Log.h"
#include "lldb/Utility/ProcessInfo.h"
-#include "Plugins/Process/Utility/RegisterInfoFreeBSD_i386.h"
-#include "Plugins/Process/Utility/RegisterInfoFreeBSD_powerpc.h"
-#include "Plugins/Process/Utility/RegisterInfoFreeBSD_x86_64.h"
-#include "Plugins/Process/Utility/RegisterInfoLinux_i386.h"
-#include "Plugins/Process/Utility/RegisterInfoLinux_s390x.h"
-#include "Plugins/Process/Utility/RegisterInfoLinux_x86_64.h"
-#include "Plugins/Process/Utility/RegisterInfoNetBSD_i386.h"
-#include "Plugins/Process/Utility/RegisterInfoNetBSD_x86_64.h"
-#include "Plugins/Process/Utility/RegisterInfoOpenBSD_i386.h"
-#include "Plugins/Process/Utility/RegisterInfoOpenBSD_x86_64.h"
-#include "Plugins/Process/Utility/RegisterInfoCommon_arm.h"
-#include "Plugins/Process/Utility/RegisterInfoCommon_arm64.h"
-#include "Plugins/Process/Utility/RegisterInfoCommon_ppc64le.h"
+#include "Register/FreeBSD/RegisterInfoFreeBSD_i386.h"
+#include "Register/FreeBSD/RegisterInfoFreeBSD_powerpc.h"
+#include "Register/FreeBSD/RegisterInfoFreeBSD_x86_64.h"
+#include "Register/Linux/RegisterInfoLinux_i386.h"
+#include "Register/Linux/RegisterInfoLinux_s390x.h"
+#include "Register/Linux/RegisterInfoLinux_x86_64.h"
+#include "Register/NetBSD/RegisterInfoNetBSD_i386.h"
+#include "Register/NetBSD/RegisterInfoNetBSD_x86_64.h"
+#include "Register/OpenBSD/RegisterInfoOpenBSD_i386.h"
+#include "Register/OpenBSD/RegisterInfoOpenBSD_x86_64.h"
+#include "Register/Common/RegisterInfoCommon_arm.h"
+#include "Register/Common/RegisterInfoCommon_arm64.h"
+#include "Register/Common/RegisterInfoCommon_ppc64le.h"
#include "ProcessElfCore.h"
#include "RegisterContextLinuxCore_x86.h"
#include "RegisterContextPOSIXCore_arm.h"
diff --git a/lldb/source/Plugins/Process/minidump/RegisterContextMinidump_ARM.h b/lldb/source/Plugins/Process/minidump/RegisterContextMinidump_ARM.h
index 857f9c0a376743..07388cbe0f65f1 100644
--- a/lldb/source/Plugins/Process/minidump/RegisterContextMinidump_ARM.h
+++ b/lldb/source/Plugins/Process/minidump/RegisterContextMinidump_ARM.h
@@ -11,7 +11,7 @@
#include "MinidumpTypes.h"
-#include "Plugins/Process/Utility/RegisterInfoInterface.h"
+#include "Register/RegisterInfoInterface.h"
#include "lldb/Target/RegisterContext.h"
diff --git a/lldb/source/Plugins/Process/minidump/RegisterContextMinidump_ARM64.h b/lldb/source/Plugins/Process/minidump/RegisterContextMinidump_ARM64.h
index 58cf8d62fb8653..e761fda93b67f0 100644
--- a/lldb/source/Plugins/Process/minidump/RegisterContextMinidump_ARM64.h
+++ b/lldb/source/Plugins/Process/minidump/RegisterContextMinidump_ARM64.h
@@ -11,7 +11,7 @@
#include "MinidumpTypes.h"
-#include "Plugins/Process/Utility/RegisterInfoInterface.h"
+#include "Register/RegisterInfoInterface.h"
#include "lldb/Target/RegisterContext.h"
#include "llvm/ADT/ArrayRef.h"
diff --git a/lldb/source/Plugins/Process/minidump/RegisterContextMinidump_x86_32.h b/lldb/source/Plugins/Process/minidump/RegisterContextMinidump_x86_32.h
index 4dffc4f9db0ebd..5599843771bcb5 100644
--- a/lldb/source/Plugins/Process/minidump/RegisterContextMinidump_x86_32.h
+++ b/lldb/source/Plugins/Process/minidump/RegisterContextMinidump_x86_32.h
@@ -11,8 +11,8 @@
#include "MinidumpTypes.h"
-#include "Plugins/Process/Utility/RegisterInfoInterface.h"
-#include "Plugins/Process/Utility/lldb-x86-register-enums.h"
+#include "Register/RegisterInfoInterface.h"
+#include "Register/Arch/lldb-x86-register-enums.h"
#include "lldb/Target/RegisterContext.h"
diff --git a/lldb/source/Plugins/Process/minidump/RegisterContextMinidump_x86_64.h b/lldb/source/Plugins/Process/minidump/RegisterContextMinidump_x86_64.h
index f8d38e4ba53786..09fbde77a06e01 100644
--- a/lldb/source/Plugins/Process/minidump/RegisterContextMinidump_x86_64.h
+++ b/lldb/source/Plugins/Process/minidump/RegisterContextMinidump_x86_64.h
@@ -11,8 +11,8 @@
#include "MinidumpTypes.h"
-#include "Plugins/Process/Utility/RegisterInfoInterface.h"
-#include "Plugins/Process/Utility/lldb-x86-register-enums.h"
+#include "Register/RegisterInfoInterface.h"
+#include "Register/Arch/lldb-x86-register-enums.h"
#include "lldb/Target/RegisterContext.h"
diff --git a/lldb/source/Plugins/Process/minidump/ThreadMinidump.cpp b/lldb/source/Plugins/Process/minidump/ThreadMinidump.cpp
index 270dded14cf3b4..905fb9348ab9b7 100644
--- a/lldb/source/Plugins/Process/minidump/ThreadMinidump.cpp
+++ b/lldb/source/Plugins/Process/minidump/ThreadMinidump.cpp
@@ -15,8 +15,8 @@
#include "RegisterContextMinidump_x86_32.h"
#include "RegisterContextMinidump_x86_64.h"
-#include "Plugins/Process/Utility/RegisterInfoLinux_i386.h"
-#include "Plugins/Process/Utility/RegisterInfoLinux_x86_64.h"
+#include "Register/Linux/RegisterInfoLinux_i386.h"
+#include "Register/Linux/RegisterInfoLinux_x86_64.h"
#include "Plugins/Process/elf-core/RegisterContextPOSIXCore_x86.h"
#include "Plugins/Process/elf-core/RegisterUtilities.h"
diff --git a/lldb/source/Plugins/SymbolFile/NativePDB/CodeViewRegisterMapping.cpp b/lldb/source/Plugins/SymbolFile/NativePDB/CodeViewRegisterMapping.cpp
index 3c10d4aa314b20..44d5ff84a9b3ef 100644
--- a/lldb/source/Plugins/SymbolFile/NativePDB/CodeViewRegisterMapping.cpp
+++ b/lldb/source/Plugins/SymbolFile/NativePDB/CodeViewRegisterMapping.cpp
@@ -10,8 +10,8 @@
#include "lldb/lldb-defines.h"
-#include "Plugins/Process/Utility/lldb-arm64-register-enums.h"
-#include "Plugins/Process/Utility/lldb-x86-register-enums.h"
+#include "Register/Arch/lldb-arm64-register-enums.h"
+#include "Register/Arch/lldb-x86-register-enums.h"
using namespace lldb_private;
diff --git a/lldb/source/Plugins/Process/Utility/RegisterContext_mips.h b/lldb/source/Register/Arch/RegisterContext_mips.h
similarity index 97%
rename from lldb/source/Plugins/Process/Utility/RegisterContext_mips.h
rename to lldb/source/Register/Arch/RegisterContext_mips.h
index 15081f974c667d..07e0add1f1c1c0 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterContext_mips.h
+++ b/lldb/source/Register/Arch/RegisterContext_mips.h
@@ -6,8 +6,8 @@
//
//===----------------------------------------------------------------------===//
-#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXT_MIPS_H
-#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXT_MIPS_H
+#ifndef LLDB_SOURCE_REGISTER_ARCH_REGISTERCONTEXT_MIPS_H
+#define LLDB_SOURCE_REGISTER_ARCH_REGISTERCONTEXT_MIPS_H
#include <cstddef>
#include <cstdint>
@@ -371,4 +371,4 @@ struct UserArea {
MSA_linux_mips msa; // MSA registers.
};
-#endif // LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXT_MIPS_H
+#endif // LLDB_SOURCE_REGISTER_ARCH_REGISTERCONTEXT_MIPS_H
diff --git a/lldb/source/Plugins/Process/Utility/RegisterContext_powerpc.h b/lldb/source/Register/Arch/RegisterContext_powerpc.h
similarity index 92%
rename from lldb/source/Plugins/Process/Utility/RegisterContext_powerpc.h
rename to lldb/source/Register/Arch/RegisterContext_powerpc.h
index 7407e2f402e08a..1ca6ac4685720f 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterContext_powerpc.h
+++ b/lldb/source/Register/Arch/RegisterContext_powerpc.h
@@ -7,8 +7,8 @@
//
//===----------------------------------------------------------------------===//
-#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXT_POWERPC_H
-#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXT_POWERPC_H
+#ifndef LLDB_SOURCE_REGISTER_ARCH_REGISTERCONTEXT_POWERPC_H
+#define LLDB_SOURCE_REGISTER_ARCH_REGISTERCONTEXT_POWERPC_H
// eh_frame and DWARF Register numbers (eRegisterKindEHFrame &
// eRegisterKindDWARF)
@@ -120,4 +120,4 @@ enum {
dwarf_v31_powerpc,
};
-#endif // LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXT_POWERPC_H
+#endif // LLDB_SOURCE_REGISTER_ARCH_REGISTERCONTEXT_POWERPC_H
diff --git a/lldb/source/Plugins/Process/Utility/RegisterContext_s390x.h b/lldb/source/Register/Arch/RegisterContext_s390x.h
similarity index 93%
rename from lldb/source/Plugins/Process/Utility/RegisterContext_s390x.h
rename to lldb/source/Register/Arch/RegisterContext_s390x.h
index 248b3bd0beacb9..2bea399dfd2985 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterContext_s390x.h
+++ b/lldb/source/Register/Arch/RegisterContext_s390x.h
@@ -6,8 +6,8 @@
//
//===----------------------------------------------------------------------===//
-#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXT_S390X_H
-#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXT_S390X_H
+#ifndef LLDB_SOURCE_REGISTER_ARCH_REGISTERCONTEXT_S390X_H
+#define LLDB_SOURCE_REGISTER_ARCH_REGISTERCONTEXT_S390X_H
// SystemZ ehframe, dwarf regnums
diff --git a/lldb/source/Plugins/Process/Utility/RegisterContext_x86.cpp b/lldb/source/Register/Arch/RegisterContext_x86.cpp
similarity index 99%
rename from lldb/source/Plugins/Process/Utility/RegisterContext_x86.cpp
rename to lldb/source/Register/Arch/RegisterContext_x86.cpp
index 059862d0481dad..e1617120c686ea 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterContext_x86.cpp
+++ b/lldb/source/Register/Arch/RegisterContext_x86.cpp
@@ -6,8 +6,8 @@
//
//===----------------------------------------------------------------------===//
-#include "RegisterContext_x86.h"
-#include "lldb-x86-register-enums.h"
+#include "Register/Arch/RegisterContext_x86.h"
+#include "Register/Arch/lldb-x86-register-enums.h"
#include "lldb/lldb-defines.h"
using namespace lldb_private;
diff --git a/lldb/source/Plugins/Process/Utility/RegisterContext_x86.h b/lldb/source/Register/Arch/RegisterContext_x86.h
similarity index 99%
rename from lldb/source/Plugins/Process/Utility/RegisterContext_x86.h
rename to lldb/source/Register/Arch/RegisterContext_x86.h
index d1d7e94f31776e..2e06f9ae281385 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterContext_x86.h
+++ b/lldb/source/Register/Arch/RegisterContext_x86.h
@@ -6,8 +6,8 @@
//
//===----------------------------------------------------------------------===//
-#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXT_X86_H
-#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXT_X86_H
+#ifndef LLDB_SOURCE_REGISTER_ARCH_REGISTERCONTEXT_X86_H
+#define LLDB_SOURCE_REGISTER_ARCH_REGISTERCONTEXT_X86_H
#include <cstddef>
#include <cstdint>
diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfos_arm.h b/lldb/source/Register/Arch/RegisterInfos_arm.h
similarity index 100%
rename from lldb/source/Plugins/Process/Utility/RegisterInfos_arm.h
rename to lldb/source/Register/Arch/RegisterInfos_arm.h
diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfos_arm64.h b/lldb/source/Register/Arch/RegisterInfos_arm64.h
similarity index 100%
rename from lldb/source/Plugins/Process/Utility/RegisterInfos_arm64.h
rename to lldb/source/Register/Arch/RegisterInfos_arm64.h
diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfos_arm64_sve.h b/lldb/source/Register/Arch/RegisterInfos_arm64_sve.h
similarity index 100%
rename from lldb/source/Plugins/Process/Utility/RegisterInfos_arm64_sve.h
rename to lldb/source/Register/Arch/RegisterInfos_arm64_sve.h
diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfos_i386.h b/lldb/source/Register/Arch/RegisterInfos_i386.h
similarity index 100%
rename from lldb/source/Plugins/Process/Utility/RegisterInfos_i386.h
rename to lldb/source/Register/Arch/RegisterInfos_i386.h
diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfos_loongarch64.h b/lldb/source/Register/Arch/RegisterInfos_loongarch64.h
similarity index 99%
rename from lldb/source/Plugins/Process/Utility/RegisterInfos_loongarch64.h
rename to lldb/source/Register/Arch/RegisterInfos_loongarch64.h
index ff8fe5990ce118..ee16c9606a90a2 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterInfos_loongarch64.h
+++ b/lldb/source/Register/Arch/RegisterInfos_loongarch64.h
@@ -15,7 +15,7 @@
#include "lldb/lldb-private.h"
#include "Utility/LoongArch_DWARF_Registers.h"
-#include "lldb-loongarch-register-enums.h"
+#include "Register/Arch/lldb-loongarch-register-enums.h"
#ifndef GPR_OFFSET
#error GPR_OFFSET must be defined before including this header file
diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfos_mips.h b/lldb/source/Register/Arch/RegisterInfos_mips.h
similarity index 100%
rename from lldb/source/Plugins/Process/Utility/RegisterInfos_mips.h
rename to lldb/source/Register/Arch/RegisterInfos_mips.h
diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfos_mips64.h b/lldb/source/Register/Arch/RegisterInfos_mips64.h
similarity index 100%
rename from lldb/source/Plugins/Process/Utility/RegisterInfos_mips64.h
rename to lldb/source/Register/Arch/RegisterInfos_mips64.h
diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfos_powerpc.h b/lldb/source/Register/Arch/RegisterInfos_powerpc.h
similarity index 100%
rename from lldb/source/Plugins/Process/Utility/RegisterInfos_powerpc.h
rename to lldb/source/Register/Arch/RegisterInfos_powerpc.h
diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfos_ppc64.h b/lldb/source/Register/Arch/RegisterInfos_ppc64.h
similarity index 99%
rename from lldb/source/Plugins/Process/Utility/RegisterInfos_ppc64.h
rename to lldb/source/Register/Arch/RegisterInfos_ppc64.h
index ba0b6d45d95ba7..61165ad0df3ecd 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterInfos_ppc64.h
+++ b/lldb/source/Register/Arch/RegisterInfos_ppc64.h
@@ -22,7 +22,7 @@
#define GPR_PPC64_SIZE(regname) (sizeof(((GPR_PPC64 *)NULL)->regname))
#include "Utility/PPC64_DWARF_Registers.h"
-#include "lldb-ppc64-register-enums.h"
+#include "Register/Arch/lldb-ppc64-register-enums.h"
// Note that the size and offset will be updated by platform-specific classes.
#define DEFINE_GPR_PPC64(reg, alt, lldb_kind) \
diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfos_ppc64le.h b/lldb/source/Register/Arch/RegisterInfos_ppc64le.h
similarity index 99%
rename from lldb/source/Plugins/Process/Utility/RegisterInfos_ppc64le.h
rename to lldb/source/Register/Arch/RegisterInfos_ppc64le.h
index 18489fb74f86ee..dbf3c425d420c1 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterInfos_ppc64le.h
+++ b/lldb/source/Register/Arch/RegisterInfos_ppc64le.h
@@ -19,7 +19,7 @@
#define GPR_SIZE(regname) (sizeof(((GPR *)NULL)->regname))
#include "Utility/PPC64LE_DWARF_Registers.h"
-#include "lldb-ppc64le-register-enums.h"
+#include "Register/Arch/lldb-ppc64le-register-enums.h"
// Note that the size and offset will be updated by platform-specific classes.
#define DEFINE_GPR(reg, alt, lldb_kind) \
diff --git a/lldb/source/Register/Arch/RegisterInfos_riscv32.h b/lldb/source/Register/Arch/RegisterInfos_riscv32.h
new file mode 100644
index 00000000000000..943058b817702c
--- /dev/null
+++ b/lldb/source/Register/Arch/RegisterInfos_riscv32.h
@@ -0,0 +1,764 @@
+//===-- RegisterInfos_riscv32.h ---------------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifdef DECLARE_REGISTER_INFOS_RISCV32_STRUCT
+
+#include "Utility/RISCV_DWARF_Registers.h"
+#include "Register/Arch/lldb-riscv-register-enums.h"
+#include "lldb/lldb-defines.h"
+#include "lldb/lldb-enumerations.h"
+#include "lldb/lldb-private.h"
+
+#include <stddef.h>
+
+#ifndef GPR_OFFSET
+#error GPR_OFFSET must be defined before including this header file
+#endif
+
+#ifndef FPR_OFFSET
+#error FPR_OFFSET must be defined before including this header file
+#endif
+
+using namespace riscv_dwarf;
+
+// Assuming register numbers seen in eh_frame and DWARF to be the same.
+#define KIND_HELPER(reg, generic_kind) \
+ {riscv_dwarf::dwarf_##reg, riscv_dwarf::dwarf_##reg, generic_kind, \
+ LLDB_INVALID_REGNUM, reg##_riscv}
+
+// Generates RegisterInfo::kinds for GPRs.
+#define GPR32_KIND(reg, generic_kind) KIND_HELPER(reg, generic_kind)
+
+// Generates RegisterInfo::kinds for FPRs.
+#define FPR32_KIND(reg, generic_kind) KIND_HELPER(reg, generic_kind)
+
+// Generates RegisterInfo::kinds for VPRs.
+#define VPR_KIND(reg, generic_kind) KIND_HELPER(reg, generic_kind)
+
+// Generates RegisterInfo::kinds for CSRs.
+#define CSR_KIND(reg, generic_kind) KIND_HELPER(reg, generic_kind)
+
+// Defines a 32-bit GPR.
+#define DEFINE_GPR32(reg, generic_kind) DEFINE_GPR32_ALT(reg, reg, generic_kind)
+
+// Defines a 32-bit GPR.
+#define DEFINE_GPR32_ALT(reg, alt, generic_kind) \
+ {#reg, \
+ #alt, \
+ 4, \
+ GPR_OFFSET(gpr_##reg##_riscv - gpr_first_riscv), \
+ lldb::eEncodingUint, \
+ lldb::eFormatHex, \
+ GPR32_KIND(gpr_##reg, generic_kind), \
+ nullptr, \
+ nullptr, \
+ nullptr}
+
+// Defines a 32-bit FPR.
+#define DEFINE_FPR32_ALT(reg, alt, generic_kind) \
+ DEFINE_FPR_ALT(reg, alt, 8, generic_kind)
+
+// Defines a 32-bit FPR.
+#define DEFINE_FPR_ALT(reg, alt, size, generic_kind) \
+ {#reg, \
+ #alt, \
+ size, \
+ FPR_OFFSET(fpr_##reg##_riscv - fpr_first_riscv), \
+ lldb::eEncodingIEEE754, \
+ lldb::eFormatHex, \
+ FPR32_KIND(fpr_##reg, generic_kind), \
+ nullptr, \
+ nullptr, \
+ nullptr}
+
+// Defines a 32-bit VPR.
+#define DEFINE_VPR(reg, generic_kind) DEFINE_VPR_ALT(reg, reg, generic_kind)
+
+// Defines a scalable vector register with default size of 128 bits.
+// The byte offset of 0 is a placeholder and should be corrected at runtime.
+// Defines a 32-bit VPR.
+#define DEFINE_VPR_ALT(reg, alt, generic_kind) \
+ {#reg, \
+ #alt, \
+ 16, \
+ 0, \
+ lldb::eEncodingVector, \
+ lldb::eFormatVectorOfUInt8, \
+ VPR_KIND(vpr_##reg, generic_kind), \
+ nullptr, \
+ nullptr, \
+ nullptr}
+
+// Defines a 32-bit CSR.
+#define DEFINE_CSR32(reg, generic_kind) DEFINE_CSR32_ALT(reg, reg, generic_kind)
+
+// Defines a 32-bit CSR.
+#define DEFINE_CSR32_ALT(reg, alt, generic_kind) \
+ DEFINE_CSR32_ALT_REGID(reg, alt, reg, generic_kind)
+
+// Defines a 32-bit CSR specified by Xqci or its sub-extension.
+#define DEFINE_QC_CSR32_ALT(name, alt, generic_kind) \
+ DEFINE_CSR32_ALT_REGID(qc.name, alt, qc_##name, generic_kind)
+
+// Defines a 32-bit CSR.
+// The byte offset of 0 is a placeholder and should be corrected at runtime.
+#define DEFINE_CSR32_ALT_REGID(name, alt, regid, generic_kind) \
+ {#name, \
+ #alt, \
+ 4, \
+ 0, \
+ lldb::eEncodingUint, \
+ lldb::eFormatHex, \
+ CSR_KIND(csr_##regid, generic_kind), \
+ nullptr, \
+ nullptr, \
+ nullptr}
+
+static lldb_private::RegisterInfo g_register_infos_riscv32_le[] = {
+ // DEFINE_GPR32(name, GENERIC KIND)
+ DEFINE_GPR32(pc, LLDB_REGNUM_GENERIC_PC),
+ DEFINE_GPR32_ALT(ra, x1, LLDB_REGNUM_GENERIC_RA),
+ DEFINE_GPR32_ALT(sp, x2, LLDB_REGNUM_GENERIC_SP),
+ DEFINE_GPR32_ALT(gp, x3, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(tp, x4, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(t0, x5, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(t1, x6, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(t2, x7, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(fp, x8, LLDB_REGNUM_GENERIC_FP),
+ DEFINE_GPR32_ALT(s1, x9, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(a0, x10, LLDB_REGNUM_GENERIC_ARG1),
+ DEFINE_GPR32_ALT(a1, x11, LLDB_REGNUM_GENERIC_ARG2),
+ DEFINE_GPR32_ALT(a2, x12, LLDB_REGNUM_GENERIC_ARG3),
+ DEFINE_GPR32_ALT(a3, x13, LLDB_REGNUM_GENERIC_ARG4),
+ DEFINE_GPR32_ALT(a4, x14, LLDB_REGNUM_GENERIC_ARG5),
+ DEFINE_GPR32_ALT(a5, x15, LLDB_REGNUM_GENERIC_ARG6),
+ DEFINE_GPR32_ALT(a6, x16, LLDB_REGNUM_GENERIC_ARG7),
+ DEFINE_GPR32_ALT(a7, x17, LLDB_REGNUM_GENERIC_ARG8),
+ DEFINE_GPR32_ALT(s2, x18, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(s3, x19, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(s4, x20, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(s5, x21, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(s6, x22, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(s7, x23, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(s8, x24, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(s9, x25, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(s10, x26, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(s11, x27, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(t3, x28, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(t4, x29, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(t5, x30, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(t6, x31, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(zero, x0, LLDB_INVALID_REGNUM),
+
+ DEFINE_FPR32_ALT(ft0, f0, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(ft1, f1, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(ft2, f2, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(ft3, f3, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(ft4, f4, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(ft5, f5, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(ft6, f6, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(ft7, f7, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fs0, f8, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fs1, f9, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fa0, f10, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fa1, f11, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fa2, f12, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fa3, f13, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fa4, f14, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fa5, f15, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fa6, f16, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fa7, f17, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fs2, f18, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fs3, f19, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fs4, f20, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fs5, f21, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fs6, f22, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fs7, f23, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fs8, f24, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fs9, f25, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fs10, f26, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fs11, f27, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(ft8, f28, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(ft9, f29, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(ft10, f30, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(ft11, f31, LLDB_INVALID_REGNUM),
+ DEFINE_FPR_ALT(fcsr, nullptr, 4, LLDB_INVALID_REGNUM),
+
+ DEFINE_VPR(v0, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v1, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v2, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v3, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v4, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v5, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v6, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v7, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v8, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v9, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v10, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v11, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v12, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v13, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v14, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v15, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v16, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v17, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v18, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v19, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v20, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v21, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v22, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v23, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v24, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v25, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v26, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v27, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v28, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v29, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v30, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v31, LLDB_INVALID_REGNUM),
+};
+
+static lldb_private::RegisterInfo g_register_infos_riscv32_gpr[] = {
+ DEFINE_GPR32(pc, LLDB_REGNUM_GENERIC_PC),
+ DEFINE_GPR32_ALT(ra, x1, LLDB_REGNUM_GENERIC_RA),
+ DEFINE_GPR32_ALT(sp, x2, LLDB_REGNUM_GENERIC_SP),
+ DEFINE_GPR32_ALT(gp, x3, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(tp, x4, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(t0, x5, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(t1, x6, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(t2, x7, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(fp, x8, LLDB_REGNUM_GENERIC_FP),
+ DEFINE_GPR32_ALT(s1, x9, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(a0, x10, LLDB_REGNUM_GENERIC_ARG1),
+ DEFINE_GPR32_ALT(a1, x11, LLDB_REGNUM_GENERIC_ARG2),
+ DEFINE_GPR32_ALT(a2, x12, LLDB_REGNUM_GENERIC_ARG3),
+ DEFINE_GPR32_ALT(a3, x13, LLDB_REGNUM_GENERIC_ARG4),
+ DEFINE_GPR32_ALT(a4, x14, LLDB_REGNUM_GENERIC_ARG5),
+ DEFINE_GPR32_ALT(a5, x15, LLDB_REGNUM_GENERIC_ARG6),
+ DEFINE_GPR32_ALT(a6, x16, LLDB_REGNUM_GENERIC_ARG7),
+ DEFINE_GPR32_ALT(a7, x17, LLDB_REGNUM_GENERIC_ARG8),
+ DEFINE_GPR32_ALT(s2, x18, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(s3, x19, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(s4, x20, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(s5, x21, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(s6, x22, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(s7, x23, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(s8, x24, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(s9, x25, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(s10, x26, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(s11, x27, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(t3, x28, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(t4, x29, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(t5, x30, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(t6, x31, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(zero, x0, LLDB_INVALID_REGNUM),
+};
+
+static lldb_private::RegisterInfo g_register_infos_riscv32_fpr[] = {
+ DEFINE_FPR32_ALT(ft0, f0, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(ft1, f1, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(ft2, f2, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(ft3, f3, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(ft4, f4, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(ft5, f5, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(ft6, f6, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(ft7, f7, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fs0, f8, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fs1, f9, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fa0, f10, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fa1, f11, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fa2, f12, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fa3, f13, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fa4, f14, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fa5, f15, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fa6, f16, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fa7, f17, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fs2, f18, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fs3, f19, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fs4, f20, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fs5, f21, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fs6, f22, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fs7, f23, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fs8, f24, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fs9, f25, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fs10, f26, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fs11, f27, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(ft8, f28, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(ft9, f29, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(ft10, f30, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(ft11, f31, LLDB_INVALID_REGNUM),
+};
+
+static lldb_private::RegisterInfo g_register_infos_riscv32_vpr[] = {
+ DEFINE_VPR(v0, LLDB_INVALID_REGNUM), DEFINE_VPR(v1, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v2, LLDB_INVALID_REGNUM), DEFINE_VPR(v3, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v4, LLDB_INVALID_REGNUM), DEFINE_VPR(v5, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v6, LLDB_INVALID_REGNUM), DEFINE_VPR(v7, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v8, LLDB_INVALID_REGNUM), DEFINE_VPR(v9, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v10, LLDB_INVALID_REGNUM), DEFINE_VPR(v11, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v12, LLDB_INVALID_REGNUM), DEFINE_VPR(v13, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v14, LLDB_INVALID_REGNUM), DEFINE_VPR(v15, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v16, LLDB_INVALID_REGNUM), DEFINE_VPR(v17, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v18, LLDB_INVALID_REGNUM), DEFINE_VPR(v19, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v20, LLDB_INVALID_REGNUM), DEFINE_VPR(v21, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v22, LLDB_INVALID_REGNUM), DEFINE_VPR(v23, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v24, LLDB_INVALID_REGNUM), DEFINE_VPR(v25, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v26, LLDB_INVALID_REGNUM), DEFINE_VPR(v27, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v28, LLDB_INVALID_REGNUM), DEFINE_VPR(v29, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v30, LLDB_INVALID_REGNUM), DEFINE_VPR(v31, LLDB_INVALID_REGNUM),
+};
+
+static lldb_private::RegisterInfo g_register_infos_riscv32_csr_patch[] = {
+ DEFINE_CSR32_ALT(fflags, csr_0x001, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(frm, csr_0x002, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(fcsr, csr_0x003, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(vstart, csr_0x008, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(vxsat, csr_0x009, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(vxrm, csr_0x00a, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(vcsr, csr_0x00f, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(sstatus, csr_0x100, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(sie, csr_0x104, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(stvec, csr_0x105, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(scounteren, csr_0x106, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(senvcfg, csr_0x10a, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(sstateen0, csr_0x10c, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(sstateen1, csr_0x10d, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(sstateen2, csr_0x10e, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(sstateen3, csr_0x10f, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(scountinhibit, csr_0x120, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(sscratch, csr_0x140, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(sepc, csr_0x141, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(scause, csr_0x142, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(stval, csr_0x143, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(satp, csr_0x180, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(vsstatus, csr_0x200, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(vsie, csr_0x204, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(vstvec, csr_0x205, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(vsscratch, csr_0x240, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(vsepc, csr_0x241, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(vscause, csr_0x242, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(vstval, csr_0x243, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(vsip, csr_0x244, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(vsatp, csr_0x280, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mstatus, csr_0x300, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(misa, csr_0x301, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(medeleg, csr_0x302, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mideleg, csr_0x303, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mie, csr_0x304, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mtvec, csr_0x305, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mcounteren, csr_0x306, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(menvcfg, csr_0x30a, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mstateen0, csr_0x30c, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mstateen1, csr_0x30d, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mstateen2, csr_0x30e, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mstateen3, csr_0x30f, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mstatush, csr_0x310, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(medelegh, csr_0x312, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(menvcfgh, csr_0x31a, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mstateen0h, csr_0x31c, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mstateen1h, csr_0x31d, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mstateen2h, csr_0x31e, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mstateen3h, csr_0x31f, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mcountinhibit, csr_0x320, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent3, csr_0x323, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent4, csr_0x324, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent5, csr_0x325, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent6, csr_0x326, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent7, csr_0x327, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent8, csr_0x328, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent9, csr_0x329, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent10, csr_0x32a, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent11, csr_0x32b, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent12, csr_0x32c, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent13, csr_0x32d, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent14, csr_0x32e, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent15, csr_0x32f, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent16, csr_0x330, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent17, csr_0x331, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent18, csr_0x332, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent19, csr_0x333, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent20, csr_0x334, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent21, csr_0x335, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent22, csr_0x336, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent23, csr_0x337, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent24, csr_0x338, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent25, csr_0x339, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent26, csr_0x33a, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent27, csr_0x33b, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent28, csr_0x33c, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent29, csr_0x33d, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent30, csr_0x33e, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent31, csr_0x33f, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mscratch, csr_0x340, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mepc, csr_0x341, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mcause, csr_0x342, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mtval, csr_0x343, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mip, csr_0x344, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mtinst, csr_0x34a, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mtval2, csr_0x34b, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpcfg0, csr_0x3a0, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpcfg1, csr_0x3a1, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpcfg2, csr_0x3a2, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpcfg3, csr_0x3a3, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpcfg4, csr_0x3a4, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpcfg5, csr_0x3a5, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpcfg6, csr_0x3a6, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpcfg7, csr_0x3a7, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpcfg8, csr_0x3a8, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpcfg9, csr_0x3a9, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpcfg10, csr_0x3aa, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpcfg11, csr_0x3ab, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpcfg12, csr_0x3ac, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpcfg13, csr_0x3ad, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpcfg14, csr_0x3ae, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpcfg15, csr_0x3af, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr0, csr_0x3b0, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr1, csr_0x3b1, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr2, csr_0x3b2, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr3, csr_0x3b3, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr4, csr_0x3b4, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr5, csr_0x3b5, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr6, csr_0x3b6, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr7, csr_0x3b7, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr8, csr_0x3b8, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr9, csr_0x3b9, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr10, csr_0x3ba, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr11, csr_0x3bb, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr12, csr_0x3bc, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr13, csr_0x3bd, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr14, csr_0x3be, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr15, csr_0x3bf, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr16, csr_0x3c0, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr17, csr_0x3c1, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr18, csr_0x3c2, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr19, csr_0x3c3, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr20, csr_0x3c4, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr21, csr_0x3c5, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr22, csr_0x3c6, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr23, csr_0x3c7, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr24, csr_0x3c8, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr25, csr_0x3c9, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr26, csr_0x3ca, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr27, csr_0x3cb, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr28, csr_0x3cc, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr29, csr_0x3cd, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr30, csr_0x3ce, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr31, csr_0x3cf, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr32, csr_0x3d0, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr33, csr_0x3d1, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr34, csr_0x3d2, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr35, csr_0x3d3, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr36, csr_0x3d4, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr37, csr_0x3d5, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr38, csr_0x3d6, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr39, csr_0x3d7, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr40, csr_0x3d8, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr41, csr_0x3d9, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr42, csr_0x3da, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr43, csr_0x3db, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr44, csr_0x3dc, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr45, csr_0x3dd, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr46, csr_0x3de, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr47, csr_0x3df, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr48, csr_0x3e0, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr49, csr_0x3e1, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr50, csr_0x3e2, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr51, csr_0x3e3, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr52, csr_0x3e4, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr53, csr_0x3e5, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr54, csr_0x3e6, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr55, csr_0x3e7, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr56, csr_0x3e8, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr57, csr_0x3e9, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr58, csr_0x3ea, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr59, csr_0x3eb, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr60, csr_0x3ec, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr61, csr_0x3ed, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr62, csr_0x3ee, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr63, csr_0x3ef, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(scontext, csr_0x5a8, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hstatus, csr_0x600, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hedeleg, csr_0x602, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hideleg, csr_0x603, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hie, csr_0x604, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(htimedelta, csr_0x605, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hcounteren, csr_0x606, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hgeie, csr_0x607, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(henvcfg, csr_0x60a, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hstateen0, csr_0x60c, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hstateen1, csr_0x60d, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hstateen2, csr_0x60e, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hstateen3, csr_0x60f, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hedelegh, csr_0x612, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(htimedeltah, csr_0x615, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(henvcfgh, csr_0x61a, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hstateen0h, csr_0x61c, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hstateen1h, csr_0x61d, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hstateen2h, csr_0x61e, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hstateen3h, csr_0x61f, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(htval, csr_0x643, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hip, csr_0x644, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hvip, csr_0x645, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(htinst, csr_0x64a, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hgatp, csr_0x680, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hcontext, csr_0x6a8, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent3h, csr_0x723, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent4h, csr_0x724, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent5h, csr_0x725, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent6h, csr_0x726, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent7h, csr_0x727, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent8h, csr_0x728, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent9h, csr_0x729, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent10h, csr_0x72a, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent11h, csr_0x72b, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent12h, csr_0x72c, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent13h, csr_0x72d, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent14h, csr_0x72e, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent15h, csr_0x72f, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent16h, csr_0x730, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent17h, csr_0x731, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent18h, csr_0x732, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent19h, csr_0x733, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent20h, csr_0x734, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent21h, csr_0x735, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent22h, csr_0x736, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent23h, csr_0x737, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent24h, csr_0x738, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent25h, csr_0x739, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent26h, csr_0x73a, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent27h, csr_0x73b, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent28h, csr_0x73c, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent29h, csr_0x73d, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent30h, csr_0x73e, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent31h, csr_0x73f, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mnscratch, csr_0x740, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mnepc, csr_0x741, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mncause, csr_0x742, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mnstatus, csr_0x744, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mseccfg, csr_0x747, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mseccfgh, csr_0x757, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(tselect, csr_0x7a0, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(tdata1, csr_0x7a1, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(tdata2, csr_0x7a2, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(tdata3, csr_0x7a3, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mcontext, csr_0x7a8, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(dcsr, csr_0x7b0, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(dpc, csr_0x7b1, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(dscratch0, csr_0x7b2, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(dscratch1, csr_0x7b3, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mcycle, csr_0xb00, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(minstret, csr_0xb02, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter3, csr_0xb03, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter4, csr_0xb04, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter5, csr_0xb05, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter6, csr_0xb06, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter7, csr_0xb07, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter8, csr_0xb08, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter9, csr_0xb09, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter10, csr_0xb0a, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter11, csr_0xb0b, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter12, csr_0xb0c, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter13, csr_0xb0d, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter14, csr_0xb0e, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter15, csr_0xb0f, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter16, csr_0xb10, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter17, csr_0xb11, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter18, csr_0xb12, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter19, csr_0xb13, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter20, csr_0xb14, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter21, csr_0xb15, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter22, csr_0xb16, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter23, csr_0xb17, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter24, csr_0xb18, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter25, csr_0xb19, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter26, csr_0xb1a, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter27, csr_0xb1b, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter28, csr_0xb1c, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter29, csr_0xb1d, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter30, csr_0xb1e, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter31, csr_0xb1f, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mcycleh, csr_0xb80, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(minstreth, csr_0xb82, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter3h, csr_0xb83, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter4h, csr_0xb84, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter5h, csr_0xb85, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter6h, csr_0xb86, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter7h, csr_0xb87, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter8h, csr_0xb88, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter9h, csr_0xb89, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter10h, csr_0xb8a, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter11h, csr_0xb8b, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter12h, csr_0xb8c, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter13h, csr_0xb8d, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter14h, csr_0xb8e, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter15h, csr_0xb8f, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter16h, csr_0xb90, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter17h, csr_0xb91, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter18h, csr_0xb92, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter19h, csr_0xb93, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter20h, csr_0xb94, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter21h, csr_0xb95, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter22h, csr_0xb96, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter23h, csr_0xb97, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter24h, csr_0xb98, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter25h, csr_0xb99, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter26h, csr_0xb9a, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter27h, csr_0xb9b, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter28h, csr_0xb9c, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter29h, csr_0xb9d, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter30h, csr_0xb9e, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter31h, csr_0xb9f, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(cycle, csr_0xc00, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(time, csr_0xc01, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(instret, csr_0xc02, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter3, csr_0xc03, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter4, csr_0xc04, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter5, csr_0xc05, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter6, csr_0xc06, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter7, csr_0xc07, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter8, csr_0xc08, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter9, csr_0xc09, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter10, csr_0xc0a, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter11, csr_0xc0b, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter12, csr_0xc0c, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter13, csr_0xc0d, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter14, csr_0xc0e, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter15, csr_0xc0f, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter16, csr_0xc10, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter17, csr_0xc11, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter18, csr_0xc12, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter19, csr_0xc13, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter20, csr_0xc14, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter21, csr_0xc15, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter22, csr_0xc16, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter23, csr_0xc17, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter24, csr_0xc18, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter25, csr_0xc19, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter26, csr_0xc1a, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter27, csr_0xc1b, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter28, csr_0xc1c, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter29, csr_0xc1d, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter30, csr_0xc1e, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter31, csr_0xc1f, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(vl, csr_0xc20, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(vtype, csr_0xc21, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(vlenb, csr_0xc22, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(cycleh, csr_0xc80, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(timeh, csr_0xc81, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(instreth, csr_0xc82, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter3h, csr_0xc83, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter4h, csr_0xc84, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter5h, csr_0xc85, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter6h, csr_0xc86, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter7h, csr_0xc87, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter8h, csr_0xc88, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter9h, csr_0xc89, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter10h, csr_0xc8a, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter11h, csr_0xc8b, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter12h, csr_0xc8c, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter13h, csr_0xc8d, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter14h, csr_0xc8e, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter15h, csr_0xc8f, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter16h, csr_0xc90, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter17h, csr_0xc91, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter18h, csr_0xc92, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter19h, csr_0xc93, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter20h, csr_0xc94, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter21h, csr_0xc95, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter22h, csr_0xc96, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter23h, csr_0xc97, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter24h, csr_0xc98, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter25h, csr_0xc99, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter26h, csr_0xc9a, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter27h, csr_0xc9b, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter28h, csr_0xc9c, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter29h, csr_0xc9d, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter30h, csr_0xc9e, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter31h, csr_0xc9f, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(scountovf, csr_0xda0, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hgeip, csr_0xe12, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mvendorid, csr_0xf11, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(marchid, csr_0xf12, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mimpid, csr_0xf13, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhartid, csr_0xf14, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mconfigptr, csr_0xf15, LLDB_INVALID_REGNUM),
+};
+
+static lldb_private::RegisterInfo g_register_infos_riscv32_csr_xqci_patch[] = {
+ DEFINE_QC_CSR32_ALT(mmcr, csr_0x7c0, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mntvec, csr_0x7c3, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mstktopaddr, csr_0x7c4, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mstkbottomaddr, csr_0x7c5, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mscratch0, csr_0x7c6, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mscratch1, csr_0x7c7, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mthreadptr, csr_0x7c8, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mwpstartaddr0, csr_0x7d0, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mwpstartaddr1, csr_0x7d1, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mwpstartaddr2, csr_0x7d2, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mwpstartaddr3, csr_0x7d3, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mwpendaddr0, csr_0x7d4, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mwpendaddr1, csr_0x7d5, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mwpendaddr2, csr_0x7d6, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mwpendaddr3, csr_0x7d7, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl0, csr_0xbc0, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl1, csr_0xbc1, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl2, csr_0xbc2, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl3, csr_0xbc3, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl4, csr_0xbc4, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl5, csr_0xbc5, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl6, csr_0xbc6, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl7, csr_0xbc7, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl8, csr_0xbc8, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl9, csr_0xbc9, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl10, csr_0xbca, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl11, csr_0xbcb, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl12, csr_0xbcc, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl13, csr_0xbcd, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl14, csr_0xbce, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl15, csr_0xbcf, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl16, csr_0xbd0, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl17, csr_0xbd1, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl18, csr_0xbd2, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl19, csr_0xbd3, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl20, csr_0xbd4, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl21, csr_0xbd5, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl22, csr_0xbd6, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl23, csr_0xbd7, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl24, csr_0xbd8, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl25, csr_0xbd9, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl26, csr_0xbda, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl27, csr_0xbdb, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl28, csr_0xbdc, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl29, csr_0xbdd, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl30, csr_0xbde, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl31, csr_0xbdf, LLDB_INVALID_REGNUM),
+};
+
+static lldb_private::RegisterInfo g_register_infos_riscv32_csr_xqciint_patch[] =
+ {
+ DEFINE_QC_CSR32_ALT(mnepc, csr_0x7c1, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mncause, csr_0x7c2, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicip0, csr_0x7f0, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicip1, csr_0x7f1, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicip2, csr_0x7f2, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicip3, csr_0x7f3, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicip4, csr_0x7f4, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicip5, csr_0x7f5, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicip6, csr_0x7f6, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicip7, csr_0x7f7, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicie0, csr_0x7f8, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicie1, csr_0x7f9, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicie2, csr_0x7fa, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicie3, csr_0x7fb, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicie4, csr_0x7fc, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicie5, csr_0x7fd, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicie6, csr_0x7fe, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicie7, csr_0x7ff, LLDB_INVALID_REGNUM),
+};
+
+#endif // DECLARE_REGISTER_INFOS_RISCV32_STRUCT
diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfos_riscv64.h b/lldb/source/Register/Arch/RegisterInfos_riscv64.h
similarity index 99%
rename from lldb/source/Plugins/Process/Utility/RegisterInfos_riscv64.h
rename to lldb/source/Register/Arch/RegisterInfos_riscv64.h
index c9959168b15365..4ba73b24d456e6 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterInfos_riscv64.h
+++ b/lldb/source/Register/Arch/RegisterInfos_riscv64.h
@@ -15,7 +15,7 @@
#include "lldb/lldb-private.h"
#include "Utility/RISCV_DWARF_Registers.h"
-#include "lldb-riscv-register-enums.h"
+#include "Register/Arch/lldb-riscv-register-enums.h"
#ifndef GPR_OFFSET
#error GPR_OFFSET must be defined before including this header file
diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfos_s390x.h b/lldb/source/Register/Arch/RegisterInfos_s390x.h
similarity index 100%
rename from lldb/source/Plugins/Process/Utility/RegisterInfos_s390x.h
rename to lldb/source/Register/Arch/RegisterInfos_s390x.h
diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfos_x86_64.h b/lldb/source/Register/Arch/RegisterInfos_x86_64.h
similarity index 100%
rename from lldb/source/Plugins/Process/Utility/RegisterInfos_x86_64.h
rename to lldb/source/Register/Arch/RegisterInfos_x86_64.h
diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfos_x86_64_with_base.h b/lldb/source/Register/Arch/RegisterInfos_x86_64_with_base.h
similarity index 99%
rename from lldb/source/Plugins/Process/Utility/RegisterInfos_x86_64_with_base.h
rename to lldb/source/Register/Arch/RegisterInfos_x86_64_with_base.h
index b111d8f62d1f3d..473fc699875314 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterInfos_x86_64_with_base.h
+++ b/lldb/source/Register/Arch/RegisterInfos_x86_64_with_base.h
@@ -6,7 +6,7 @@
//
//===----------------------------------------------------------------------===//
-#include "RegisterInfos_x86_64_with_base_shared.h"
+#include "Register/Arch/RegisterInfos_x86_64_with_base_shared.h"
// This file is meant to be textually included. Do not #include modular
// headers here.
diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfos_x86_64_with_base_shared.cpp b/lldb/source/Register/Arch/RegisterInfos_x86_64_with_base_shared.cpp
similarity index 99%
rename from lldb/source/Plugins/Process/Utility/RegisterInfos_x86_64_with_base_shared.cpp
rename to lldb/source/Register/Arch/RegisterInfos_x86_64_with_base_shared.cpp
index 7b2d64de230f33..af70efef86ac28 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterInfos_x86_64_with_base_shared.cpp
+++ b/lldb/source/Register/Arch/RegisterInfos_x86_64_with_base_shared.cpp
@@ -6,7 +6,7 @@
//
//===----------------------------------------------------------------------===//
-#include "RegisterInfos_x86_64_with_base_shared.h"
+#include "Register/Arch/RegisterInfos_x86_64_with_base_shared.h"
#include "lldb/lldb-defines.h"
#include <mutex>
diff --git a/lldb/source/Register/Arch/RegisterInfos_x86_64_with_base_shared.h b/lldb/source/Register/Arch/RegisterInfos_x86_64_with_base_shared.h
new file mode 100644
index 00000000000000..8486e1fe1eb5c1
--- /dev/null
+++ b/lldb/source/Register/Arch/RegisterInfos_x86_64_with_base_shared.h
@@ -0,0 +1,142 @@
+//===-- RegisterInfos_x86_64_with_base_shared.h -----------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "Register/Arch/lldb-x86-register-enums.h"
+#include <stdint.h>
+
+#ifndef lldb_RegisterInfos_x86_64_with_base_shared_h
+#define lldb_RegisterInfos_x86_64_with_base_shared_h
+
+#include "Plugins/Process/Utility/NativeRegisterContextRegisterInfo.h"
+
+namespace lldb_private {
+
+struct RegisterInfos_x86_64_with_base_shared {
+ static uint32_t g_contained_eax[];
+ static uint32_t g_contained_ebx[];
+ static uint32_t g_contained_ecx[];
+ static uint32_t g_contained_edx[];
+ static uint32_t g_contained_edi[];
+ static uint32_t g_contained_esi[];
+ static uint32_t g_contained_ebp[];
+ static uint32_t g_contained_esp[];
+
+ static uint32_t g_invalidate_eax[];
+ static uint32_t g_invalidate_ebx[];
+ static uint32_t g_invalidate_ecx[];
+ static uint32_t g_invalidate_edx[];
+ static uint32_t g_invalidate_edi[];
+ static uint32_t g_invalidate_esi[];
+ static uint32_t g_invalidate_ebp[];
+ static uint32_t g_invalidate_esp[];
+
+ static uint32_t g_contained_rax[];
+ static uint32_t g_contained_rbx[];
+ static uint32_t g_contained_rcx[];
+ static uint32_t g_contained_rdx[];
+ static uint32_t g_contained_rdi[];
+ static uint32_t g_contained_rsi[];
+ static uint32_t g_contained_rbp[];
+ static uint32_t g_contained_rsp[];
+ static uint32_t g_contained_r8[];
+ static uint32_t g_contained_r9[];
+ static uint32_t g_contained_r10[];
+ static uint32_t g_contained_r11[];
+ static uint32_t g_contained_r12[];
+ static uint32_t g_contained_r13[];
+ static uint32_t g_contained_r14[];
+ static uint32_t g_contained_r15[];
+
+ static uint32_t g_invalidate_rax[];
+ static uint32_t g_invalidate_rbx[];
+ static uint32_t g_invalidate_rcx[];
+ static uint32_t g_invalidate_rdx[];
+ static uint32_t g_invalidate_rdi[];
+ static uint32_t g_invalidate_rsi[];
+ static uint32_t g_invalidate_rbp[];
+ static uint32_t g_invalidate_rsp[];
+ static uint32_t g_invalidate_r8[];
+ static uint32_t g_invalidate_r9[];
+ static uint32_t g_invalidate_r10[];
+ static uint32_t g_invalidate_r11[];
+ static uint32_t g_invalidate_r12[];
+ static uint32_t g_invalidate_r13[];
+ static uint32_t g_invalidate_r14[];
+ static uint32_t g_invalidate_r15[];
+
+ static uint32_t g_contained_fip[];
+ static uint32_t g_contained_fdp[];
+
+ static uint32_t g_invalidate_fip[];
+ static uint32_t g_invalidate_fdp[];
+
+ static uint32_t g_contained_st0_32[];
+ static uint32_t g_contained_st1_32[];
+ static uint32_t g_contained_st2_32[];
+ static uint32_t g_contained_st3_32[];
+ static uint32_t g_contained_st4_32[];
+ static uint32_t g_contained_st5_32[];
+ static uint32_t g_contained_st6_32[];
+ static uint32_t g_contained_st7_32[];
+
+ static uint32_t g_invalidate_st0_32[];
+ static uint32_t g_invalidate_st1_32[];
+ static uint32_t g_invalidate_st2_32[];
+ static uint32_t g_invalidate_st3_32[];
+ static uint32_t g_invalidate_st4_32[];
+ static uint32_t g_invalidate_st5_32[];
+ static uint32_t g_invalidate_st6_32[];
+ static uint32_t g_invalidate_st7_32[];
+
+ static uint32_t g_contained_st0_64[];
+ static uint32_t g_contained_st1_64[];
+ static uint32_t g_contained_st2_64[];
+ static uint32_t g_contained_st3_64[];
+ static uint32_t g_contained_st4_64[];
+ static uint32_t g_contained_st5_64[];
+ static uint32_t g_contained_st6_64[];
+ static uint32_t g_contained_st7_64[];
+
+ static uint32_t g_invalidate_st0_64[];
+ static uint32_t g_invalidate_st1_64[];
+ static uint32_t g_invalidate_st2_64[];
+ static uint32_t g_invalidate_st3_64[];
+ static uint32_t g_invalidate_st4_64[];
+ static uint32_t g_invalidate_st5_64[];
+ static uint32_t g_invalidate_st6_64[];
+ static uint32_t g_invalidate_st7_64[];
+};
+
+struct RegInfo {
+ uint32_t num_registers;
+ uint32_t num_gpr_registers;
+ uint32_t num_fpr_registers;
+ uint32_t num_avx_registers;
+
+ uint32_t last_gpr;
+ uint32_t first_fpr;
+ uint32_t last_fpr;
+
+ uint32_t first_st;
+ uint32_t last_st;
+ uint32_t first_mm;
+ uint32_t last_mm;
+ uint32_t first_xmm;
+ uint32_t last_xmm;
+ uint32_t first_ymm;
+ uint32_t last_ymm;
+
+ uint32_t first_dr;
+ uint32_t gpr_flags;
+};
+
+RegInfo &GetRegInfoShared(llvm::Triple::ArchType arch_type, bool with_base);
+
+} // namespace lldb_private
+
+#endif // ifndef lldb_RegisterInfos_x86_64_with_base_shared_h
diff --git a/lldb/source/Plugins/Process/Utility/lldb-arm-register-enums.h b/lldb/source/Register/Arch/lldb-arm-register-enums.h
similarity index 94%
rename from lldb/source/Plugins/Process/Utility/lldb-arm-register-enums.h
rename to lldb/source/Register/Arch/lldb-arm-register-enums.h
index 8f0eed4f02c902..eb0fbe1d3e34b3 100644
--- a/lldb/source/Plugins/Process/Utility/lldb-arm-register-enums.h
+++ b/lldb/source/Register/Arch/lldb-arm-register-enums.h
@@ -6,8 +6,8 @@
//
//===----------------------------------------------------------------------===//
-#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_LLDB_ARM_REGISTER_ENUMS_H
-#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_LLDB_ARM_REGISTER_ENUMS_H
+#ifndef LLDB_SOURCE_REGISTER_ARCH_LLDB_ARM_REGISTER_ENUMS_H
+#define LLDB_SOURCE_REGISTER_ARCH_LLDB_ARM_REGISTER_ENUMS_H
namespace lldb_private {
// LLDB register codes (e.g. RegisterKind == eRegisterKindLLDB)
@@ -196,4 +196,4 @@ enum {
};
}
-#endif // LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_LLDB_ARM_REGISTER_ENUMS_H
+#endif // LLDB_SOURCE_REGISTER_ARCH_LLDB_ARM_REGISTER_ENUMS_H
diff --git a/lldb/source/Plugins/Process/Utility/lldb-arm64-register-enums.h b/lldb/source/Register/Arch/lldb-arm64-register-enums.h
similarity index 95%
rename from lldb/source/Plugins/Process/Utility/lldb-arm64-register-enums.h
rename to lldb/source/Register/Arch/lldb-arm64-register-enums.h
index 39d47b8801ccf0..d89acda4f34376 100644
--- a/lldb/source/Plugins/Process/Utility/lldb-arm64-register-enums.h
+++ b/lldb/source/Register/Arch/lldb-arm64-register-enums.h
@@ -6,8 +6,8 @@
//
//===----------------------------------------------------------------------===//
-#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_LLDB_ARM64_REGISTER_ENUMS_H
-#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_LLDB_ARM64_REGISTER_ENUMS_H
+#ifndef LLDB_SOURCE_REGISTER_ARCH_LLDB_ARM64_REGISTER_ENUMS_H
+#define LLDB_SOURCE_REGISTER_ARCH_LLDB_ARM64_REGISTER_ENUMS_H
namespace lldb_private {
// LLDB register codes (e.g. RegisterKind == eRegisterKindLLDB)
@@ -261,4 +261,4 @@ enum {
};
}
-#endif // LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_LLDB_ARM64_REGISTER_ENUMS_H
+#endif // LLDB_SOURCE_REGISTER_ARCH_LLDB_ARM64_REGISTER_ENUMS_H
diff --git a/lldb/source/Plugins/Process/Utility/lldb-loongarch-register-enums.h b/lldb/source/Register/Arch/lldb-loongarch-register-enums.h
similarity index 96%
rename from lldb/source/Plugins/Process/Utility/lldb-loongarch-register-enums.h
rename to lldb/source/Register/Arch/lldb-loongarch-register-enums.h
index accd53048f93e2..22726cf98de320 100644
--- a/lldb/source/Plugins/Process/Utility/lldb-loongarch-register-enums.h
+++ b/lldb/source/Register/Arch/lldb-loongarch-register-enums.h
@@ -6,8 +6,8 @@
//
//===----------------------------------------------------------------------===//
-#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_LLDB_LOONGARCH_REGISTER_ENUMS_H
-#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_LLDB_LOONGARCH_REGISTER_ENUMS_H
+#ifndef LLDB_SOURCE_REGISTER_ARCH_LLDB_LOONGARCH_REGISTER_ENUMS_H
+#define LLDB_SOURCE_REGISTER_ARCH_LLDB_LOONGARCH_REGISTER_ENUMS_H
// LLDB register codes (e.g. RegisterKind == eRegisterKindLLDB)
@@ -245,4 +245,4 @@ enum {
k_num_registers_loongarch
};
-#endif // LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_LLDB_LOONGARCH_REGISTER_ENUMS_H
+#endif // LLDB_SOURCE_REGISTER_ARCH_LLDB_LOONGARCH_REGISTER_ENUMS_H
diff --git a/lldb/source/Plugins/Process/Utility/lldb-ppc64-register-enums.h b/lldb/source/Register/Arch/lldb-ppc64-register-enums.h
similarity index 94%
rename from lldb/source/Plugins/Process/Utility/lldb-ppc64-register-enums.h
rename to lldb/source/Register/Arch/lldb-ppc64-register-enums.h
index 19525b2c4ee34b..5f9e6604c4026d 100644
--- a/lldb/source/Plugins/Process/Utility/lldb-ppc64-register-enums.h
+++ b/lldb/source/Register/Arch/lldb-ppc64-register-enums.h
@@ -6,8 +6,8 @@
//
//===----------------------------------------------------------------------===//
-#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_LLDB_PPC64_REGISTER_ENUMS_H
-#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_LLDB_PPC64_REGISTER_ENUMS_H
+#ifndef LLDB_SOURCE_REGISTER_ARCH_LLDB_PPC64_REGISTER_ENUMS_H
+#define LLDB_SOURCE_REGISTER_ARCH_LLDB_PPC64_REGISTER_ENUMS_H
// LLDB register codes (e.g. RegisterKind == eRegisterKindLLDB)
@@ -201,4 +201,4 @@ enum {
k_num_vsx_registers_ppc64 = k_last_vsx_ppc64 - k_first_vsx_ppc64 + 1,
};
-#endif // LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_LLDB_PPC64_REGISTER_ENUMS_H
+#endif // LLDB_SOURCE_REGISTER_ARCH_LLDB_PPC64_REGISTER_ENUMS_H
diff --git a/lldb/source/Plugins/Process/Utility/lldb-ppc64le-register-enums.h b/lldb/source/Register/Arch/lldb-ppc64le-register-enums.h
similarity index 95%
rename from lldb/source/Plugins/Process/Utility/lldb-ppc64le-register-enums.h
rename to lldb/source/Register/Arch/lldb-ppc64le-register-enums.h
index a7b5bc5ad9e342..53df636bb2dfa4 100644
--- a/lldb/source/Plugins/Process/Utility/lldb-ppc64le-register-enums.h
+++ b/lldb/source/Register/Arch/lldb-ppc64le-register-enums.h
@@ -6,8 +6,8 @@
//
//===----------------------------------------------------------------------===//
-#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_LLDB_PPC64LE_REGISTER_ENUMS_H
-#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_LLDB_PPC64LE_REGISTER_ENUMS_H
+#ifndef LLDB_SOURCE_REGISTER_ARCH_LLDB_PPC64LE_REGISTER_ENUMS_H
+#define LLDB_SOURCE_REGISTER_ARCH_LLDB_PPC64LE_REGISTER_ENUMS_H
// LLDB register codes (e.g. RegisterKind == eRegisterKindLLDB)
@@ -204,4 +204,4 @@ enum {
k_num_vsx_registers_ppc64le = k_last_vsx_ppc64le - k_first_vsx_ppc64le + 1,
};
-#endif // LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_LLDB_PPC64LE_REGISTER_ENUMS_H
+#endif // LLDB_SOURCE_REGISTER_ARCH_LLDB_PPC64LE_REGISTER_ENUMS_H
diff --git a/lldb/source/Register/Arch/lldb-riscv-register-enums.h b/lldb/source/Register/Arch/lldb-riscv-register-enums.h
new file mode 100644
index 00000000000000..edad96d91e4c17
--- /dev/null
+++ b/lldb/source/Register/Arch/lldb-riscv-register-enums.h
@@ -0,0 +1,4733 @@
+//===-- lldb-riscv-register-enums.h -----------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLDB_SOURCE_REGISTER_ARCH_LLDB_RISCV_REGISTER_ENUMS_H
+#define LLDB_SOURCE_REGISTER_ARCH_LLDB_RISCV_REGISTER_ENUMS_H
+
+// LLDB register codes (e.g. RegisterKind == eRegisterKindLLDB)
+
+// Internal codes for all riscv registers.
+enum {
+ // The same order as user_regs_struct in <asm/ptrace.h>
+ // note: these enum values are used as byte_offset
+ gpr_first_riscv = 0,
+ gpr_pc_riscv = gpr_first_riscv,
+ gpr_x1_riscv,
+ gpr_x2_riscv,
+ gpr_x3_riscv,
+ gpr_x4_riscv,
+ gpr_x5_riscv,
+ gpr_x6_riscv,
+ gpr_x7_riscv,
+ gpr_x8_riscv,
+ gpr_x9_riscv,
+ gpr_x10_riscv,
+ gpr_x11_riscv,
+ gpr_x12_riscv,
+ gpr_x13_riscv,
+ gpr_x14_riscv,
+ gpr_x15_riscv,
+ gpr_x16_riscv,
+ gpr_x17_riscv,
+ gpr_x18_riscv,
+ gpr_x19_riscv,
+ gpr_x20_riscv,
+ gpr_x21_riscv,
+ gpr_x22_riscv,
+ gpr_x23_riscv,
+ gpr_x24_riscv,
+ gpr_x25_riscv,
+ gpr_x26_riscv,
+ gpr_x27_riscv,
+ gpr_x28_riscv,
+ gpr_x29_riscv,
+ gpr_x30_riscv,
+ gpr_x31_riscv,
+ gpr_x0_riscv,
+ gpr_zero_riscv = gpr_x0_riscv,
+ gpr_ra_riscv = gpr_x1_riscv,
+ gpr_sp_riscv = gpr_x2_riscv,
+ gpr_gp_riscv = gpr_x3_riscv,
+ gpr_tp_riscv = gpr_x4_riscv,
+ gpr_t0_riscv = gpr_x5_riscv,
+ gpr_t1_riscv = gpr_x6_riscv,
+ gpr_t2_riscv = gpr_x7_riscv,
+ gpr_fp_riscv = gpr_x8_riscv,
+ gpr_s1_riscv = gpr_x9_riscv,
+ gpr_a0_riscv = gpr_x10_riscv,
+ gpr_a1_riscv = gpr_x11_riscv,
+ gpr_a2_riscv = gpr_x12_riscv,
+ gpr_a3_riscv = gpr_x13_riscv,
+ gpr_a4_riscv = gpr_x14_riscv,
+ gpr_a5_riscv = gpr_x15_riscv,
+ gpr_a6_riscv = gpr_x16_riscv,
+ gpr_a7_riscv = gpr_x17_riscv,
+ gpr_s2_riscv = gpr_x18_riscv,
+ gpr_s3_riscv = gpr_x19_riscv,
+ gpr_s4_riscv = gpr_x20_riscv,
+ gpr_s5_riscv = gpr_x21_riscv,
+ gpr_s6_riscv = gpr_x22_riscv,
+ gpr_s7_riscv = gpr_x23_riscv,
+ gpr_s8_riscv = gpr_x24_riscv,
+ gpr_s9_riscv = gpr_x25_riscv,
+ gpr_s10_riscv = gpr_x26_riscv,
+ gpr_s11_riscv = gpr_x27_riscv,
+ gpr_t3_riscv = gpr_x28_riscv,
+ gpr_t4_riscv = gpr_x29_riscv,
+ gpr_t5_riscv = gpr_x30_riscv,
+ gpr_t6_riscv = gpr_x31_riscv,
+ gpr_last_riscv = gpr_x0_riscv,
+
+ fpr_first_riscv = 33,
+ fpr_f0_riscv = fpr_first_riscv,
+ fpr_f1_riscv,
+ fpr_f2_riscv,
+ fpr_f3_riscv,
+ fpr_f4_riscv,
+ fpr_f5_riscv,
+ fpr_f6_riscv,
+ fpr_f7_riscv,
+ fpr_f8_riscv,
+ fpr_f9_riscv,
+ fpr_f10_riscv,
+ fpr_f11_riscv,
+ fpr_f12_riscv,
+ fpr_f13_riscv,
+ fpr_f14_riscv,
+ fpr_f15_riscv,
+ fpr_f16_riscv,
+ fpr_f17_riscv,
+ fpr_f18_riscv,
+ fpr_f19_riscv,
+ fpr_f20_riscv,
+ fpr_f21_riscv,
+ fpr_f22_riscv,
+ fpr_f23_riscv,
+ fpr_f24_riscv,
+ fpr_f25_riscv,
+ fpr_f26_riscv,
+ fpr_f27_riscv,
+ fpr_f28_riscv,
+ fpr_f29_riscv,
+ fpr_f30_riscv,
+ fpr_f31_riscv,
+
+ fpr_fcsr_riscv,
+ fpr_ft0_riscv = fpr_f0_riscv,
+ fpr_ft1_riscv = fpr_f1_riscv,
+ fpr_ft2_riscv = fpr_f2_riscv,
+ fpr_ft3_riscv = fpr_f3_riscv,
+ fpr_ft4_riscv = fpr_f4_riscv,
+ fpr_ft5_riscv = fpr_f5_riscv,
+ fpr_ft6_riscv = fpr_f6_riscv,
+ fpr_ft7_riscv = fpr_f7_riscv,
+ fpr_fs0_riscv = fpr_f8_riscv,
+ fpr_fs1_riscv = fpr_f9_riscv,
+ fpr_fa0_riscv = fpr_f10_riscv,
+ fpr_fa1_riscv = fpr_f11_riscv,
+ fpr_fa2_riscv = fpr_f12_riscv,
+ fpr_fa3_riscv = fpr_f13_riscv,
+ fpr_fa4_riscv = fpr_f14_riscv,
+ fpr_fa5_riscv = fpr_f15_riscv,
+ fpr_fa6_riscv = fpr_f16_riscv,
+ fpr_fa7_riscv = fpr_f17_riscv,
+ fpr_fs2_riscv = fpr_f18_riscv,
+ fpr_fs3_riscv = fpr_f19_riscv,
+ fpr_fs4_riscv = fpr_f20_riscv,
+ fpr_fs5_riscv = fpr_f21_riscv,
+ fpr_fs6_riscv = fpr_f22_riscv,
+ fpr_fs7_riscv = fpr_f23_riscv,
+ fpr_fs8_riscv = fpr_f24_riscv,
+ fpr_fs9_riscv = fpr_f25_riscv,
+ fpr_fs10_riscv = fpr_f26_riscv,
+ fpr_fs11_riscv = fpr_f27_riscv,
+ fpr_ft8_riscv = fpr_f28_riscv,
+ fpr_ft9_riscv = fpr_f29_riscv,
+ fpr_ft10_riscv = fpr_f30_riscv,
+ fpr_ft11_riscv = fpr_f31_riscv,
+ fpr_last_riscv = fpr_fcsr_riscv,
+
+ vpr_first_riscv = 66,
+ vpr_v0_riscv = vpr_first_riscv,
+ vpr_v1_riscv,
+ vpr_v2_riscv,
+ vpr_v3_riscv,
+ vpr_v4_riscv,
+ vpr_v5_riscv,
+ vpr_v6_riscv,
+ vpr_v7_riscv,
+ vpr_v8_riscv,
+ vpr_v9_riscv,
+ vpr_v10_riscv,
+ vpr_v11_riscv,
+ vpr_v12_riscv,
+ vpr_v13_riscv,
+ vpr_v14_riscv,
+ vpr_v15_riscv,
+ vpr_v16_riscv,
+ vpr_v17_riscv,
+ vpr_v18_riscv,
+ vpr_v19_riscv,
+ vpr_v20_riscv,
+ vpr_v21_riscv,
+ vpr_v22_riscv,
+ vpr_v23_riscv,
+ vpr_v24_riscv,
+ vpr_v25_riscv,
+ vpr_v26_riscv,
+ vpr_v27_riscv,
+ vpr_v28_riscv,
+ vpr_v29_riscv,
+ vpr_v30_riscv,
+ vpr_v31_riscv,
+ vpr_last_riscv = vpr_v31_riscv,
+
+ csr_first_riscv = 98,
+ csr_0_riscv = csr_first_riscv,
+ csr_1_riscv,
+ csr_2_riscv,
+ csr_3_riscv,
+ csr_4_riscv,
+ csr_5_riscv,
+ csr_6_riscv,
+ csr_7_riscv,
+ csr_8_riscv,
+ csr_9_riscv,
+ csr_10_riscv,
+ csr_11_riscv,
+ csr_12_riscv,
+ csr_13_riscv,
+ csr_14_riscv,
+ csr_15_riscv,
+ csr_16_riscv,
+ csr_17_riscv,
+ csr_18_riscv,
+ csr_19_riscv,
+ csr_20_riscv,
+ csr_21_riscv,
+ csr_22_riscv,
+ csr_23_riscv,
+ csr_24_riscv,
+ csr_25_riscv,
+ csr_26_riscv,
+ csr_27_riscv,
+ csr_28_riscv,
+ csr_29_riscv,
+ csr_30_riscv,
+ csr_31_riscv,
+ csr_32_riscv,
+ csr_33_riscv,
+ csr_34_riscv,
+ csr_35_riscv,
+ csr_36_riscv,
+ csr_37_riscv,
+ csr_38_riscv,
+ csr_39_riscv,
+ csr_40_riscv,
+ csr_41_riscv,
+ csr_42_riscv,
+ csr_43_riscv,
+ csr_44_riscv,
+ csr_45_riscv,
+ csr_46_riscv,
+ csr_47_riscv,
+ csr_48_riscv,
+ csr_49_riscv,
+ csr_50_riscv,
+ csr_51_riscv,
+ csr_52_riscv,
+ csr_53_riscv,
+ csr_54_riscv,
+ csr_55_riscv,
+ csr_56_riscv,
+ csr_57_riscv,
+ csr_58_riscv,
+ csr_59_riscv,
+ csr_60_riscv,
+ csr_61_riscv,
+ csr_62_riscv,
+ csr_63_riscv,
+ csr_64_riscv,
+ csr_65_riscv,
+ csr_66_riscv,
+ csr_67_riscv,
+ csr_68_riscv,
+ csr_69_riscv,
+ csr_70_riscv,
+ csr_71_riscv,
+ csr_72_riscv,
+ csr_73_riscv,
+ csr_74_riscv,
+ csr_75_riscv,
+ csr_76_riscv,
+ csr_77_riscv,
+ csr_78_riscv,
+ csr_79_riscv,
+ csr_80_riscv,
+ csr_81_riscv,
+ csr_82_riscv,
+ csr_83_riscv,
+ csr_84_riscv,
+ csr_85_riscv,
+ csr_86_riscv,
+ csr_87_riscv,
+ csr_88_riscv,
+ csr_89_riscv,
+ csr_90_riscv,
+ csr_91_riscv,
+ csr_92_riscv,
+ csr_93_riscv,
+ csr_94_riscv,
+ csr_95_riscv,
+ csr_96_riscv,
+ csr_97_riscv,
+ csr_98_riscv,
+ csr_99_riscv,
+ csr_100_riscv,
+ csr_101_riscv,
+ csr_102_riscv,
+ csr_103_riscv,
+ csr_104_riscv,
+ csr_105_riscv,
+ csr_106_riscv,
+ csr_107_riscv,
+ csr_108_riscv,
+ csr_109_riscv,
+ csr_110_riscv,
+ csr_111_riscv,
+ csr_112_riscv,
+ csr_113_riscv,
+ csr_114_riscv,
+ csr_115_riscv,
+ csr_116_riscv,
+ csr_117_riscv,
+ csr_118_riscv,
+ csr_119_riscv,
+ csr_120_riscv,
+ csr_121_riscv,
+ csr_122_riscv,
+ csr_123_riscv,
+ csr_124_riscv,
+ csr_125_riscv,
+ csr_126_riscv,
+ csr_127_riscv,
+ csr_128_riscv,
+ csr_129_riscv,
+ csr_130_riscv,
+ csr_131_riscv,
+ csr_132_riscv,
+ csr_133_riscv,
+ csr_134_riscv,
+ csr_135_riscv,
+ csr_136_riscv,
+ csr_137_riscv,
+ csr_138_riscv,
+ csr_139_riscv,
+ csr_140_riscv,
+ csr_141_riscv,
+ csr_142_riscv,
+ csr_143_riscv,
+ csr_144_riscv,
+ csr_145_riscv,
+ csr_146_riscv,
+ csr_147_riscv,
+ csr_148_riscv,
+ csr_149_riscv,
+ csr_150_riscv,
+ csr_151_riscv,
+ csr_152_riscv,
+ csr_153_riscv,
+ csr_154_riscv,
+ csr_155_riscv,
+ csr_156_riscv,
+ csr_157_riscv,
+ csr_158_riscv,
+ csr_159_riscv,
+ csr_160_riscv,
+ csr_161_riscv,
+ csr_162_riscv,
+ csr_163_riscv,
+ csr_164_riscv,
+ csr_165_riscv,
+ csr_166_riscv,
+ csr_167_riscv,
+ csr_168_riscv,
+ csr_169_riscv,
+ csr_170_riscv,
+ csr_171_riscv,
+ csr_172_riscv,
+ csr_173_riscv,
+ csr_174_riscv,
+ csr_175_riscv,
+ csr_176_riscv,
+ csr_177_riscv,
+ csr_178_riscv,
+ csr_179_riscv,
+ csr_180_riscv,
+ csr_181_riscv,
+ csr_182_riscv,
+ csr_183_riscv,
+ csr_184_riscv,
+ csr_185_riscv,
+ csr_186_riscv,
+ csr_187_riscv,
+ csr_188_riscv,
+ csr_189_riscv,
+ csr_190_riscv,
+ csr_191_riscv,
+ csr_192_riscv,
+ csr_193_riscv,
+ csr_194_riscv,
+ csr_195_riscv,
+ csr_196_riscv,
+ csr_197_riscv,
+ csr_198_riscv,
+ csr_199_riscv,
+ csr_200_riscv,
+ csr_201_riscv,
+ csr_202_riscv,
+ csr_203_riscv,
+ csr_204_riscv,
+ csr_205_riscv,
+ csr_206_riscv,
+ csr_207_riscv,
+ csr_208_riscv,
+ csr_209_riscv,
+ csr_210_riscv,
+ csr_211_riscv,
+ csr_212_riscv,
+ csr_213_riscv,
+ csr_214_riscv,
+ csr_215_riscv,
+ csr_216_riscv,
+ csr_217_riscv,
+ csr_218_riscv,
+ csr_219_riscv,
+ csr_220_riscv,
+ csr_221_riscv,
+ csr_222_riscv,
+ csr_223_riscv,
+ csr_224_riscv,
+ csr_225_riscv,
+ csr_226_riscv,
+ csr_227_riscv,
+ csr_228_riscv,
+ csr_229_riscv,
+ csr_230_riscv,
+ csr_231_riscv,
+ csr_232_riscv,
+ csr_233_riscv,
+ csr_234_riscv,
+ csr_235_riscv,
+ csr_236_riscv,
+ csr_237_riscv,
+ csr_238_riscv,
+ csr_239_riscv,
+ csr_240_riscv,
+ csr_241_riscv,
+ csr_242_riscv,
+ csr_243_riscv,
+ csr_244_riscv,
+ csr_245_riscv,
+ csr_246_riscv,
+ csr_247_riscv,
+ csr_248_riscv,
+ csr_249_riscv,
+ csr_250_riscv,
+ csr_251_riscv,
+ csr_252_riscv,
+ csr_253_riscv,
+ csr_254_riscv,
+ csr_255_riscv,
+ csr_256_riscv,
+ csr_257_riscv,
+ csr_258_riscv,
+ csr_259_riscv,
+ csr_260_riscv,
+ csr_261_riscv,
+ csr_262_riscv,
+ csr_263_riscv,
+ csr_264_riscv,
+ csr_265_riscv,
+ csr_266_riscv,
+ csr_267_riscv,
+ csr_268_riscv,
+ csr_269_riscv,
+ csr_270_riscv,
+ csr_271_riscv,
+ csr_272_riscv,
+ csr_273_riscv,
+ csr_274_riscv,
+ csr_275_riscv,
+ csr_276_riscv,
+ csr_277_riscv,
+ csr_278_riscv,
+ csr_279_riscv,
+ csr_280_riscv,
+ csr_281_riscv,
+ csr_282_riscv,
+ csr_283_riscv,
+ csr_284_riscv,
+ csr_285_riscv,
+ csr_286_riscv,
+ csr_287_riscv,
+ csr_288_riscv,
+ csr_289_riscv,
+ csr_290_riscv,
+ csr_291_riscv,
+ csr_292_riscv,
+ csr_293_riscv,
+ csr_294_riscv,
+ csr_295_riscv,
+ csr_296_riscv,
+ csr_297_riscv,
+ csr_298_riscv,
+ csr_299_riscv,
+ csr_300_riscv,
+ csr_301_riscv,
+ csr_302_riscv,
+ csr_303_riscv,
+ csr_304_riscv,
+ csr_305_riscv,
+ csr_306_riscv,
+ csr_307_riscv,
+ csr_308_riscv,
+ csr_309_riscv,
+ csr_310_riscv,
+ csr_311_riscv,
+ csr_312_riscv,
+ csr_313_riscv,
+ csr_314_riscv,
+ csr_315_riscv,
+ csr_316_riscv,
+ csr_317_riscv,
+ csr_318_riscv,
+ csr_319_riscv,
+ csr_320_riscv,
+ csr_321_riscv,
+ csr_322_riscv,
+ csr_323_riscv,
+ csr_324_riscv,
+ csr_325_riscv,
+ csr_326_riscv,
+ csr_327_riscv,
+ csr_328_riscv,
+ csr_329_riscv,
+ csr_330_riscv,
+ csr_331_riscv,
+ csr_332_riscv,
+ csr_333_riscv,
+ csr_334_riscv,
+ csr_335_riscv,
+ csr_336_riscv,
+ csr_337_riscv,
+ csr_338_riscv,
+ csr_339_riscv,
+ csr_340_riscv,
+ csr_341_riscv,
+ csr_342_riscv,
+ csr_343_riscv,
+ csr_344_riscv,
+ csr_345_riscv,
+ csr_346_riscv,
+ csr_347_riscv,
+ csr_348_riscv,
+ csr_349_riscv,
+ csr_350_riscv,
+ csr_351_riscv,
+ csr_352_riscv,
+ csr_353_riscv,
+ csr_354_riscv,
+ csr_355_riscv,
+ csr_356_riscv,
+ csr_357_riscv,
+ csr_358_riscv,
+ csr_359_riscv,
+ csr_360_riscv,
+ csr_361_riscv,
+ csr_362_riscv,
+ csr_363_riscv,
+ csr_364_riscv,
+ csr_365_riscv,
+ csr_366_riscv,
+ csr_367_riscv,
+ csr_368_riscv,
+ csr_369_riscv,
+ csr_370_riscv,
+ csr_371_riscv,
+ csr_372_riscv,
+ csr_373_riscv,
+ csr_374_riscv,
+ csr_375_riscv,
+ csr_376_riscv,
+ csr_377_riscv,
+ csr_378_riscv,
+ csr_379_riscv,
+ csr_380_riscv,
+ csr_381_riscv,
+ csr_382_riscv,
+ csr_383_riscv,
+ csr_384_riscv,
+ csr_385_riscv,
+ csr_386_riscv,
+ csr_387_riscv,
+ csr_388_riscv,
+ csr_389_riscv,
+ csr_390_riscv,
+ csr_391_riscv,
+ csr_392_riscv,
+ csr_393_riscv,
+ csr_394_riscv,
+ csr_395_riscv,
+ csr_396_riscv,
+ csr_397_riscv,
+ csr_398_riscv,
+ csr_399_riscv,
+ csr_400_riscv,
+ csr_401_riscv,
+ csr_402_riscv,
+ csr_403_riscv,
+ csr_404_riscv,
+ csr_405_riscv,
+ csr_406_riscv,
+ csr_407_riscv,
+ csr_408_riscv,
+ csr_409_riscv,
+ csr_410_riscv,
+ csr_411_riscv,
+ csr_412_riscv,
+ csr_413_riscv,
+ csr_414_riscv,
+ csr_415_riscv,
+ csr_416_riscv,
+ csr_417_riscv,
+ csr_418_riscv,
+ csr_419_riscv,
+ csr_420_riscv,
+ csr_421_riscv,
+ csr_422_riscv,
+ csr_423_riscv,
+ csr_424_riscv,
+ csr_425_riscv,
+ csr_426_riscv,
+ csr_427_riscv,
+ csr_428_riscv,
+ csr_429_riscv,
+ csr_430_riscv,
+ csr_431_riscv,
+ csr_432_riscv,
+ csr_433_riscv,
+ csr_434_riscv,
+ csr_435_riscv,
+ csr_436_riscv,
+ csr_437_riscv,
+ csr_438_riscv,
+ csr_439_riscv,
+ csr_440_riscv,
+ csr_441_riscv,
+ csr_442_riscv,
+ csr_443_riscv,
+ csr_444_riscv,
+ csr_445_riscv,
+ csr_446_riscv,
+ csr_447_riscv,
+ csr_448_riscv,
+ csr_449_riscv,
+ csr_450_riscv,
+ csr_451_riscv,
+ csr_452_riscv,
+ csr_453_riscv,
+ csr_454_riscv,
+ csr_455_riscv,
+ csr_456_riscv,
+ csr_457_riscv,
+ csr_458_riscv,
+ csr_459_riscv,
+ csr_460_riscv,
+ csr_461_riscv,
+ csr_462_riscv,
+ csr_463_riscv,
+ csr_464_riscv,
+ csr_465_riscv,
+ csr_466_riscv,
+ csr_467_riscv,
+ csr_468_riscv,
+ csr_469_riscv,
+ csr_470_riscv,
+ csr_471_riscv,
+ csr_472_riscv,
+ csr_473_riscv,
+ csr_474_riscv,
+ csr_475_riscv,
+ csr_476_riscv,
+ csr_477_riscv,
+ csr_478_riscv,
+ csr_479_riscv,
+ csr_480_riscv,
+ csr_481_riscv,
+ csr_482_riscv,
+ csr_483_riscv,
+ csr_484_riscv,
+ csr_485_riscv,
+ csr_486_riscv,
+ csr_487_riscv,
+ csr_488_riscv,
+ csr_489_riscv,
+ csr_490_riscv,
+ csr_491_riscv,
+ csr_492_riscv,
+ csr_493_riscv,
+ csr_494_riscv,
+ csr_495_riscv,
+ csr_496_riscv,
+ csr_497_riscv,
+ csr_498_riscv,
+ csr_499_riscv,
+ csr_500_riscv,
+ csr_501_riscv,
+ csr_502_riscv,
+ csr_503_riscv,
+ csr_504_riscv,
+ csr_505_riscv,
+ csr_506_riscv,
+ csr_507_riscv,
+ csr_508_riscv,
+ csr_509_riscv,
+ csr_510_riscv,
+ csr_511_riscv,
+ csr_512_riscv,
+ csr_513_riscv,
+ csr_514_riscv,
+ csr_515_riscv,
+ csr_516_riscv,
+ csr_517_riscv,
+ csr_518_riscv,
+ csr_519_riscv,
+ csr_520_riscv,
+ csr_521_riscv,
+ csr_522_riscv,
+ csr_523_riscv,
+ csr_524_riscv,
+ csr_525_riscv,
+ csr_526_riscv,
+ csr_527_riscv,
+ csr_528_riscv,
+ csr_529_riscv,
+ csr_530_riscv,
+ csr_531_riscv,
+ csr_532_riscv,
+ csr_533_riscv,
+ csr_534_riscv,
+ csr_535_riscv,
+ csr_536_riscv,
+ csr_537_riscv,
+ csr_538_riscv,
+ csr_539_riscv,
+ csr_540_riscv,
+ csr_541_riscv,
+ csr_542_riscv,
+ csr_543_riscv,
+ csr_544_riscv,
+ csr_545_riscv,
+ csr_546_riscv,
+ csr_547_riscv,
+ csr_548_riscv,
+ csr_549_riscv,
+ csr_550_riscv,
+ csr_551_riscv,
+ csr_552_riscv,
+ csr_553_riscv,
+ csr_554_riscv,
+ csr_555_riscv,
+ csr_556_riscv,
+ csr_557_riscv,
+ csr_558_riscv,
+ csr_559_riscv,
+ csr_560_riscv,
+ csr_561_riscv,
+ csr_562_riscv,
+ csr_563_riscv,
+ csr_564_riscv,
+ csr_565_riscv,
+ csr_566_riscv,
+ csr_567_riscv,
+ csr_568_riscv,
+ csr_569_riscv,
+ csr_570_riscv,
+ csr_571_riscv,
+ csr_572_riscv,
+ csr_573_riscv,
+ csr_574_riscv,
+ csr_575_riscv,
+ csr_576_riscv,
+ csr_577_riscv,
+ csr_578_riscv,
+ csr_579_riscv,
+ csr_580_riscv,
+ csr_581_riscv,
+ csr_582_riscv,
+ csr_583_riscv,
+ csr_584_riscv,
+ csr_585_riscv,
+ csr_586_riscv,
+ csr_587_riscv,
+ csr_588_riscv,
+ csr_589_riscv,
+ csr_590_riscv,
+ csr_591_riscv,
+ csr_592_riscv,
+ csr_593_riscv,
+ csr_594_riscv,
+ csr_595_riscv,
+ csr_596_riscv,
+ csr_597_riscv,
+ csr_598_riscv,
+ csr_599_riscv,
+ csr_600_riscv,
+ csr_601_riscv,
+ csr_602_riscv,
+ csr_603_riscv,
+ csr_604_riscv,
+ csr_605_riscv,
+ csr_606_riscv,
+ csr_607_riscv,
+ csr_608_riscv,
+ csr_609_riscv,
+ csr_610_riscv,
+ csr_611_riscv,
+ csr_612_riscv,
+ csr_613_riscv,
+ csr_614_riscv,
+ csr_615_riscv,
+ csr_616_riscv,
+ csr_617_riscv,
+ csr_618_riscv,
+ csr_619_riscv,
+ csr_620_riscv,
+ csr_621_riscv,
+ csr_622_riscv,
+ csr_623_riscv,
+ csr_624_riscv,
+ csr_625_riscv,
+ csr_626_riscv,
+ csr_627_riscv,
+ csr_628_riscv,
+ csr_629_riscv,
+ csr_630_riscv,
+ csr_631_riscv,
+ csr_632_riscv,
+ csr_633_riscv,
+ csr_634_riscv,
+ csr_635_riscv,
+ csr_636_riscv,
+ csr_637_riscv,
+ csr_638_riscv,
+ csr_639_riscv,
+ csr_640_riscv,
+ csr_641_riscv,
+ csr_642_riscv,
+ csr_643_riscv,
+ csr_644_riscv,
+ csr_645_riscv,
+ csr_646_riscv,
+ csr_647_riscv,
+ csr_648_riscv,
+ csr_649_riscv,
+ csr_650_riscv,
+ csr_651_riscv,
+ csr_652_riscv,
+ csr_653_riscv,
+ csr_654_riscv,
+ csr_655_riscv,
+ csr_656_riscv,
+ csr_657_riscv,
+ csr_658_riscv,
+ csr_659_riscv,
+ csr_660_riscv,
+ csr_661_riscv,
+ csr_662_riscv,
+ csr_663_riscv,
+ csr_664_riscv,
+ csr_665_riscv,
+ csr_666_riscv,
+ csr_667_riscv,
+ csr_668_riscv,
+ csr_669_riscv,
+ csr_670_riscv,
+ csr_671_riscv,
+ csr_672_riscv,
+ csr_673_riscv,
+ csr_674_riscv,
+ csr_675_riscv,
+ csr_676_riscv,
+ csr_677_riscv,
+ csr_678_riscv,
+ csr_679_riscv,
+ csr_680_riscv,
+ csr_681_riscv,
+ csr_682_riscv,
+ csr_683_riscv,
+ csr_684_riscv,
+ csr_685_riscv,
+ csr_686_riscv,
+ csr_687_riscv,
+ csr_688_riscv,
+ csr_689_riscv,
+ csr_690_riscv,
+ csr_691_riscv,
+ csr_692_riscv,
+ csr_693_riscv,
+ csr_694_riscv,
+ csr_695_riscv,
+ csr_696_riscv,
+ csr_697_riscv,
+ csr_698_riscv,
+ csr_699_riscv,
+ csr_700_riscv,
+ csr_701_riscv,
+ csr_702_riscv,
+ csr_703_riscv,
+ csr_704_riscv,
+ csr_705_riscv,
+ csr_706_riscv,
+ csr_707_riscv,
+ csr_708_riscv,
+ csr_709_riscv,
+ csr_710_riscv,
+ csr_711_riscv,
+ csr_712_riscv,
+ csr_713_riscv,
+ csr_714_riscv,
+ csr_715_riscv,
+ csr_716_riscv,
+ csr_717_riscv,
+ csr_718_riscv,
+ csr_719_riscv,
+ csr_720_riscv,
+ csr_721_riscv,
+ csr_722_riscv,
+ csr_723_riscv,
+ csr_724_riscv,
+ csr_725_riscv,
+ csr_726_riscv,
+ csr_727_riscv,
+ csr_728_riscv,
+ csr_729_riscv,
+ csr_730_riscv,
+ csr_731_riscv,
+ csr_732_riscv,
+ csr_733_riscv,
+ csr_734_riscv,
+ csr_735_riscv,
+ csr_736_riscv,
+ csr_737_riscv,
+ csr_738_riscv,
+ csr_739_riscv,
+ csr_740_riscv,
+ csr_741_riscv,
+ csr_742_riscv,
+ csr_743_riscv,
+ csr_744_riscv,
+ csr_745_riscv,
+ csr_746_riscv,
+ csr_747_riscv,
+ csr_748_riscv,
+ csr_749_riscv,
+ csr_750_riscv,
+ csr_751_riscv,
+ csr_752_riscv,
+ csr_753_riscv,
+ csr_754_riscv,
+ csr_755_riscv,
+ csr_756_riscv,
+ csr_757_riscv,
+ csr_758_riscv,
+ csr_759_riscv,
+ csr_760_riscv,
+ csr_761_riscv,
+ csr_762_riscv,
+ csr_763_riscv,
+ csr_764_riscv,
+ csr_765_riscv,
+ csr_766_riscv,
+ csr_767_riscv,
+ csr_768_riscv,
+ csr_769_riscv,
+ csr_770_riscv,
+ csr_771_riscv,
+ csr_772_riscv,
+ csr_773_riscv,
+ csr_774_riscv,
+ csr_775_riscv,
+ csr_776_riscv,
+ csr_777_riscv,
+ csr_778_riscv,
+ csr_779_riscv,
+ csr_780_riscv,
+ csr_781_riscv,
+ csr_782_riscv,
+ csr_783_riscv,
+ csr_784_riscv,
+ csr_785_riscv,
+ csr_786_riscv,
+ csr_787_riscv,
+ csr_788_riscv,
+ csr_789_riscv,
+ csr_790_riscv,
+ csr_791_riscv,
+ csr_792_riscv,
+ csr_793_riscv,
+ csr_794_riscv,
+ csr_795_riscv,
+ csr_796_riscv,
+ csr_797_riscv,
+ csr_798_riscv,
+ csr_799_riscv,
+ csr_800_riscv,
+ csr_801_riscv,
+ csr_802_riscv,
+ csr_803_riscv,
+ csr_804_riscv,
+ csr_805_riscv,
+ csr_806_riscv,
+ csr_807_riscv,
+ csr_808_riscv,
+ csr_809_riscv,
+ csr_810_riscv,
+ csr_811_riscv,
+ csr_812_riscv,
+ csr_813_riscv,
+ csr_814_riscv,
+ csr_815_riscv,
+ csr_816_riscv,
+ csr_817_riscv,
+ csr_818_riscv,
+ csr_819_riscv,
+ csr_820_riscv,
+ csr_821_riscv,
+ csr_822_riscv,
+ csr_823_riscv,
+ csr_824_riscv,
+ csr_825_riscv,
+ csr_826_riscv,
+ csr_827_riscv,
+ csr_828_riscv,
+ csr_829_riscv,
+ csr_830_riscv,
+ csr_831_riscv,
+ csr_832_riscv,
+ csr_833_riscv,
+ csr_834_riscv,
+ csr_835_riscv,
+ csr_836_riscv,
+ csr_837_riscv,
+ csr_838_riscv,
+ csr_839_riscv,
+ csr_840_riscv,
+ csr_841_riscv,
+ csr_842_riscv,
+ csr_843_riscv,
+ csr_844_riscv,
+ csr_845_riscv,
+ csr_846_riscv,
+ csr_847_riscv,
+ csr_848_riscv,
+ csr_849_riscv,
+ csr_850_riscv,
+ csr_851_riscv,
+ csr_852_riscv,
+ csr_853_riscv,
+ csr_854_riscv,
+ csr_855_riscv,
+ csr_856_riscv,
+ csr_857_riscv,
+ csr_858_riscv,
+ csr_859_riscv,
+ csr_860_riscv,
+ csr_861_riscv,
+ csr_862_riscv,
+ csr_863_riscv,
+ csr_864_riscv,
+ csr_865_riscv,
+ csr_866_riscv,
+ csr_867_riscv,
+ csr_868_riscv,
+ csr_869_riscv,
+ csr_870_riscv,
+ csr_871_riscv,
+ csr_872_riscv,
+ csr_873_riscv,
+ csr_874_riscv,
+ csr_875_riscv,
+ csr_876_riscv,
+ csr_877_riscv,
+ csr_878_riscv,
+ csr_879_riscv,
+ csr_880_riscv,
+ csr_881_riscv,
+ csr_882_riscv,
+ csr_883_riscv,
+ csr_884_riscv,
+ csr_885_riscv,
+ csr_886_riscv,
+ csr_887_riscv,
+ csr_888_riscv,
+ csr_889_riscv,
+ csr_890_riscv,
+ csr_891_riscv,
+ csr_892_riscv,
+ csr_893_riscv,
+ csr_894_riscv,
+ csr_895_riscv,
+ csr_896_riscv,
+ csr_897_riscv,
+ csr_898_riscv,
+ csr_899_riscv,
+ csr_900_riscv,
+ csr_901_riscv,
+ csr_902_riscv,
+ csr_903_riscv,
+ csr_904_riscv,
+ csr_905_riscv,
+ csr_906_riscv,
+ csr_907_riscv,
+ csr_908_riscv,
+ csr_909_riscv,
+ csr_910_riscv,
+ csr_911_riscv,
+ csr_912_riscv,
+ csr_913_riscv,
+ csr_914_riscv,
+ csr_915_riscv,
+ csr_916_riscv,
+ csr_917_riscv,
+ csr_918_riscv,
+ csr_919_riscv,
+ csr_920_riscv,
+ csr_921_riscv,
+ csr_922_riscv,
+ csr_923_riscv,
+ csr_924_riscv,
+ csr_925_riscv,
+ csr_926_riscv,
+ csr_927_riscv,
+ csr_928_riscv,
+ csr_929_riscv,
+ csr_930_riscv,
+ csr_931_riscv,
+ csr_932_riscv,
+ csr_933_riscv,
+ csr_934_riscv,
+ csr_935_riscv,
+ csr_936_riscv,
+ csr_937_riscv,
+ csr_938_riscv,
+ csr_939_riscv,
+ csr_940_riscv,
+ csr_941_riscv,
+ csr_942_riscv,
+ csr_943_riscv,
+ csr_944_riscv,
+ csr_945_riscv,
+ csr_946_riscv,
+ csr_947_riscv,
+ csr_948_riscv,
+ csr_949_riscv,
+ csr_950_riscv,
+ csr_951_riscv,
+ csr_952_riscv,
+ csr_953_riscv,
+ csr_954_riscv,
+ csr_955_riscv,
+ csr_956_riscv,
+ csr_957_riscv,
+ csr_958_riscv,
+ csr_959_riscv,
+ csr_960_riscv,
+ csr_961_riscv,
+ csr_962_riscv,
+ csr_963_riscv,
+ csr_964_riscv,
+ csr_965_riscv,
+ csr_966_riscv,
+ csr_967_riscv,
+ csr_968_riscv,
+ csr_969_riscv,
+ csr_970_riscv,
+ csr_971_riscv,
+ csr_972_riscv,
+ csr_973_riscv,
+ csr_974_riscv,
+ csr_975_riscv,
+ csr_976_riscv,
+ csr_977_riscv,
+ csr_978_riscv,
+ csr_979_riscv,
+ csr_980_riscv,
+ csr_981_riscv,
+ csr_982_riscv,
+ csr_983_riscv,
+ csr_984_riscv,
+ csr_985_riscv,
+ csr_986_riscv,
+ csr_987_riscv,
+ csr_988_riscv,
+ csr_989_riscv,
+ csr_990_riscv,
+ csr_991_riscv,
+ csr_992_riscv,
+ csr_993_riscv,
+ csr_994_riscv,
+ csr_995_riscv,
+ csr_996_riscv,
+ csr_997_riscv,
+ csr_998_riscv,
+ csr_999_riscv,
+ csr_1000_riscv,
+ csr_1001_riscv,
+ csr_1002_riscv,
+ csr_1003_riscv,
+ csr_1004_riscv,
+ csr_1005_riscv,
+ csr_1006_riscv,
+ csr_1007_riscv,
+ csr_1008_riscv,
+ csr_1009_riscv,
+ csr_1010_riscv,
+ csr_1011_riscv,
+ csr_1012_riscv,
+ csr_1013_riscv,
+ csr_1014_riscv,
+ csr_1015_riscv,
+ csr_1016_riscv,
+ csr_1017_riscv,
+ csr_1018_riscv,
+ csr_1019_riscv,
+ csr_1020_riscv,
+ csr_1021_riscv,
+ csr_1022_riscv,
+ csr_1023_riscv,
+ csr_1024_riscv,
+ csr_1025_riscv,
+ csr_1026_riscv,
+ csr_1027_riscv,
+ csr_1028_riscv,
+ csr_1029_riscv,
+ csr_1030_riscv,
+ csr_1031_riscv,
+ csr_1032_riscv,
+ csr_1033_riscv,
+ csr_1034_riscv,
+ csr_1035_riscv,
+ csr_1036_riscv,
+ csr_1037_riscv,
+ csr_1038_riscv,
+ csr_1039_riscv,
+ csr_1040_riscv,
+ csr_1041_riscv,
+ csr_1042_riscv,
+ csr_1043_riscv,
+ csr_1044_riscv,
+ csr_1045_riscv,
+ csr_1046_riscv,
+ csr_1047_riscv,
+ csr_1048_riscv,
+ csr_1049_riscv,
+ csr_1050_riscv,
+ csr_1051_riscv,
+ csr_1052_riscv,
+ csr_1053_riscv,
+ csr_1054_riscv,
+ csr_1055_riscv,
+ csr_1056_riscv,
+ csr_1057_riscv,
+ csr_1058_riscv,
+ csr_1059_riscv,
+ csr_1060_riscv,
+ csr_1061_riscv,
+ csr_1062_riscv,
+ csr_1063_riscv,
+ csr_1064_riscv,
+ csr_1065_riscv,
+ csr_1066_riscv,
+ csr_1067_riscv,
+ csr_1068_riscv,
+ csr_1069_riscv,
+ csr_1070_riscv,
+ csr_1071_riscv,
+ csr_1072_riscv,
+ csr_1073_riscv,
+ csr_1074_riscv,
+ csr_1075_riscv,
+ csr_1076_riscv,
+ csr_1077_riscv,
+ csr_1078_riscv,
+ csr_1079_riscv,
+ csr_1080_riscv,
+ csr_1081_riscv,
+ csr_1082_riscv,
+ csr_1083_riscv,
+ csr_1084_riscv,
+ csr_1085_riscv,
+ csr_1086_riscv,
+ csr_1087_riscv,
+ csr_1088_riscv,
+ csr_1089_riscv,
+ csr_1090_riscv,
+ csr_1091_riscv,
+ csr_1092_riscv,
+ csr_1093_riscv,
+ csr_1094_riscv,
+ csr_1095_riscv,
+ csr_1096_riscv,
+ csr_1097_riscv,
+ csr_1098_riscv,
+ csr_1099_riscv,
+ csr_1100_riscv,
+ csr_1101_riscv,
+ csr_1102_riscv,
+ csr_1103_riscv,
+ csr_1104_riscv,
+ csr_1105_riscv,
+ csr_1106_riscv,
+ csr_1107_riscv,
+ csr_1108_riscv,
+ csr_1109_riscv,
+ csr_1110_riscv,
+ csr_1111_riscv,
+ csr_1112_riscv,
+ csr_1113_riscv,
+ csr_1114_riscv,
+ csr_1115_riscv,
+ csr_1116_riscv,
+ csr_1117_riscv,
+ csr_1118_riscv,
+ csr_1119_riscv,
+ csr_1120_riscv,
+ csr_1121_riscv,
+ csr_1122_riscv,
+ csr_1123_riscv,
+ csr_1124_riscv,
+ csr_1125_riscv,
+ csr_1126_riscv,
+ csr_1127_riscv,
+ csr_1128_riscv,
+ csr_1129_riscv,
+ csr_1130_riscv,
+ csr_1131_riscv,
+ csr_1132_riscv,
+ csr_1133_riscv,
+ csr_1134_riscv,
+ csr_1135_riscv,
+ csr_1136_riscv,
+ csr_1137_riscv,
+ csr_1138_riscv,
+ csr_1139_riscv,
+ csr_1140_riscv,
+ csr_1141_riscv,
+ csr_1142_riscv,
+ csr_1143_riscv,
+ csr_1144_riscv,
+ csr_1145_riscv,
+ csr_1146_riscv,
+ csr_1147_riscv,
+ csr_1148_riscv,
+ csr_1149_riscv,
+ csr_1150_riscv,
+ csr_1151_riscv,
+ csr_1152_riscv,
+ csr_1153_riscv,
+ csr_1154_riscv,
+ csr_1155_riscv,
+ csr_1156_riscv,
+ csr_1157_riscv,
+ csr_1158_riscv,
+ csr_1159_riscv,
+ csr_1160_riscv,
+ csr_1161_riscv,
+ csr_1162_riscv,
+ csr_1163_riscv,
+ csr_1164_riscv,
+ csr_1165_riscv,
+ csr_1166_riscv,
+ csr_1167_riscv,
+ csr_1168_riscv,
+ csr_1169_riscv,
+ csr_1170_riscv,
+ csr_1171_riscv,
+ csr_1172_riscv,
+ csr_1173_riscv,
+ csr_1174_riscv,
+ csr_1175_riscv,
+ csr_1176_riscv,
+ csr_1177_riscv,
+ csr_1178_riscv,
+ csr_1179_riscv,
+ csr_1180_riscv,
+ csr_1181_riscv,
+ csr_1182_riscv,
+ csr_1183_riscv,
+ csr_1184_riscv,
+ csr_1185_riscv,
+ csr_1186_riscv,
+ csr_1187_riscv,
+ csr_1188_riscv,
+ csr_1189_riscv,
+ csr_1190_riscv,
+ csr_1191_riscv,
+ csr_1192_riscv,
+ csr_1193_riscv,
+ csr_1194_riscv,
+ csr_1195_riscv,
+ csr_1196_riscv,
+ csr_1197_riscv,
+ csr_1198_riscv,
+ csr_1199_riscv,
+ csr_1200_riscv,
+ csr_1201_riscv,
+ csr_1202_riscv,
+ csr_1203_riscv,
+ csr_1204_riscv,
+ csr_1205_riscv,
+ csr_1206_riscv,
+ csr_1207_riscv,
+ csr_1208_riscv,
+ csr_1209_riscv,
+ csr_1210_riscv,
+ csr_1211_riscv,
+ csr_1212_riscv,
+ csr_1213_riscv,
+ csr_1214_riscv,
+ csr_1215_riscv,
+ csr_1216_riscv,
+ csr_1217_riscv,
+ csr_1218_riscv,
+ csr_1219_riscv,
+ csr_1220_riscv,
+ csr_1221_riscv,
+ csr_1222_riscv,
+ csr_1223_riscv,
+ csr_1224_riscv,
+ csr_1225_riscv,
+ csr_1226_riscv,
+ csr_1227_riscv,
+ csr_1228_riscv,
+ csr_1229_riscv,
+ csr_1230_riscv,
+ csr_1231_riscv,
+ csr_1232_riscv,
+ csr_1233_riscv,
+ csr_1234_riscv,
+ csr_1235_riscv,
+ csr_1236_riscv,
+ csr_1237_riscv,
+ csr_1238_riscv,
+ csr_1239_riscv,
+ csr_1240_riscv,
+ csr_1241_riscv,
+ csr_1242_riscv,
+ csr_1243_riscv,
+ csr_1244_riscv,
+ csr_1245_riscv,
+ csr_1246_riscv,
+ csr_1247_riscv,
+ csr_1248_riscv,
+ csr_1249_riscv,
+ csr_1250_riscv,
+ csr_1251_riscv,
+ csr_1252_riscv,
+ csr_1253_riscv,
+ csr_1254_riscv,
+ csr_1255_riscv,
+ csr_1256_riscv,
+ csr_1257_riscv,
+ csr_1258_riscv,
+ csr_1259_riscv,
+ csr_1260_riscv,
+ csr_1261_riscv,
+ csr_1262_riscv,
+ csr_1263_riscv,
+ csr_1264_riscv,
+ csr_1265_riscv,
+ csr_1266_riscv,
+ csr_1267_riscv,
+ csr_1268_riscv,
+ csr_1269_riscv,
+ csr_1270_riscv,
+ csr_1271_riscv,
+ csr_1272_riscv,
+ csr_1273_riscv,
+ csr_1274_riscv,
+ csr_1275_riscv,
+ csr_1276_riscv,
+ csr_1277_riscv,
+ csr_1278_riscv,
+ csr_1279_riscv,
+ csr_1280_riscv,
+ csr_1281_riscv,
+ csr_1282_riscv,
+ csr_1283_riscv,
+ csr_1284_riscv,
+ csr_1285_riscv,
+ csr_1286_riscv,
+ csr_1287_riscv,
+ csr_1288_riscv,
+ csr_1289_riscv,
+ csr_1290_riscv,
+ csr_1291_riscv,
+ csr_1292_riscv,
+ csr_1293_riscv,
+ csr_1294_riscv,
+ csr_1295_riscv,
+ csr_1296_riscv,
+ csr_1297_riscv,
+ csr_1298_riscv,
+ csr_1299_riscv,
+ csr_1300_riscv,
+ csr_1301_riscv,
+ csr_1302_riscv,
+ csr_1303_riscv,
+ csr_1304_riscv,
+ csr_1305_riscv,
+ csr_1306_riscv,
+ csr_1307_riscv,
+ csr_1308_riscv,
+ csr_1309_riscv,
+ csr_1310_riscv,
+ csr_1311_riscv,
+ csr_1312_riscv,
+ csr_1313_riscv,
+ csr_1314_riscv,
+ csr_1315_riscv,
+ csr_1316_riscv,
+ csr_1317_riscv,
+ csr_1318_riscv,
+ csr_1319_riscv,
+ csr_1320_riscv,
+ csr_1321_riscv,
+ csr_1322_riscv,
+ csr_1323_riscv,
+ csr_1324_riscv,
+ csr_1325_riscv,
+ csr_1326_riscv,
+ csr_1327_riscv,
+ csr_1328_riscv,
+ csr_1329_riscv,
+ csr_1330_riscv,
+ csr_1331_riscv,
+ csr_1332_riscv,
+ csr_1333_riscv,
+ csr_1334_riscv,
+ csr_1335_riscv,
+ csr_1336_riscv,
+ csr_1337_riscv,
+ csr_1338_riscv,
+ csr_1339_riscv,
+ csr_1340_riscv,
+ csr_1341_riscv,
+ csr_1342_riscv,
+ csr_1343_riscv,
+ csr_1344_riscv,
+ csr_1345_riscv,
+ csr_1346_riscv,
+ csr_1347_riscv,
+ csr_1348_riscv,
+ csr_1349_riscv,
+ csr_1350_riscv,
+ csr_1351_riscv,
+ csr_1352_riscv,
+ csr_1353_riscv,
+ csr_1354_riscv,
+ csr_1355_riscv,
+ csr_1356_riscv,
+ csr_1357_riscv,
+ csr_1358_riscv,
+ csr_1359_riscv,
+ csr_1360_riscv,
+ csr_1361_riscv,
+ csr_1362_riscv,
+ csr_1363_riscv,
+ csr_1364_riscv,
+ csr_1365_riscv,
+ csr_1366_riscv,
+ csr_1367_riscv,
+ csr_1368_riscv,
+ csr_1369_riscv,
+ csr_1370_riscv,
+ csr_1371_riscv,
+ csr_1372_riscv,
+ csr_1373_riscv,
+ csr_1374_riscv,
+ csr_1375_riscv,
+ csr_1376_riscv,
+ csr_1377_riscv,
+ csr_1378_riscv,
+ csr_1379_riscv,
+ csr_1380_riscv,
+ csr_1381_riscv,
+ csr_1382_riscv,
+ csr_1383_riscv,
+ csr_1384_riscv,
+ csr_1385_riscv,
+ csr_1386_riscv,
+ csr_1387_riscv,
+ csr_1388_riscv,
+ csr_1389_riscv,
+ csr_1390_riscv,
+ csr_1391_riscv,
+ csr_1392_riscv,
+ csr_1393_riscv,
+ csr_1394_riscv,
+ csr_1395_riscv,
+ csr_1396_riscv,
+ csr_1397_riscv,
+ csr_1398_riscv,
+ csr_1399_riscv,
+ csr_1400_riscv,
+ csr_1401_riscv,
+ csr_1402_riscv,
+ csr_1403_riscv,
+ csr_1404_riscv,
+ csr_1405_riscv,
+ csr_1406_riscv,
+ csr_1407_riscv,
+ csr_1408_riscv,
+ csr_1409_riscv,
+ csr_1410_riscv,
+ csr_1411_riscv,
+ csr_1412_riscv,
+ csr_1413_riscv,
+ csr_1414_riscv,
+ csr_1415_riscv,
+ csr_1416_riscv,
+ csr_1417_riscv,
+ csr_1418_riscv,
+ csr_1419_riscv,
+ csr_1420_riscv,
+ csr_1421_riscv,
+ csr_1422_riscv,
+ csr_1423_riscv,
+ csr_1424_riscv,
+ csr_1425_riscv,
+ csr_1426_riscv,
+ csr_1427_riscv,
+ csr_1428_riscv,
+ csr_1429_riscv,
+ csr_1430_riscv,
+ csr_1431_riscv,
+ csr_1432_riscv,
+ csr_1433_riscv,
+ csr_1434_riscv,
+ csr_1435_riscv,
+ csr_1436_riscv,
+ csr_1437_riscv,
+ csr_1438_riscv,
+ csr_1439_riscv,
+ csr_1440_riscv,
+ csr_1441_riscv,
+ csr_1442_riscv,
+ csr_1443_riscv,
+ csr_1444_riscv,
+ csr_1445_riscv,
+ csr_1446_riscv,
+ csr_1447_riscv,
+ csr_1448_riscv,
+ csr_1449_riscv,
+ csr_1450_riscv,
+ csr_1451_riscv,
+ csr_1452_riscv,
+ csr_1453_riscv,
+ csr_1454_riscv,
+ csr_1455_riscv,
+ csr_1456_riscv,
+ csr_1457_riscv,
+ csr_1458_riscv,
+ csr_1459_riscv,
+ csr_1460_riscv,
+ csr_1461_riscv,
+ csr_1462_riscv,
+ csr_1463_riscv,
+ csr_1464_riscv,
+ csr_1465_riscv,
+ csr_1466_riscv,
+ csr_1467_riscv,
+ csr_1468_riscv,
+ csr_1469_riscv,
+ csr_1470_riscv,
+ csr_1471_riscv,
+ csr_1472_riscv,
+ csr_1473_riscv,
+ csr_1474_riscv,
+ csr_1475_riscv,
+ csr_1476_riscv,
+ csr_1477_riscv,
+ csr_1478_riscv,
+ csr_1479_riscv,
+ csr_1480_riscv,
+ csr_1481_riscv,
+ csr_1482_riscv,
+ csr_1483_riscv,
+ csr_1484_riscv,
+ csr_1485_riscv,
+ csr_1486_riscv,
+ csr_1487_riscv,
+ csr_1488_riscv,
+ csr_1489_riscv,
+ csr_1490_riscv,
+ csr_1491_riscv,
+ csr_1492_riscv,
+ csr_1493_riscv,
+ csr_1494_riscv,
+ csr_1495_riscv,
+ csr_1496_riscv,
+ csr_1497_riscv,
+ csr_1498_riscv,
+ csr_1499_riscv,
+ csr_1500_riscv,
+ csr_1501_riscv,
+ csr_1502_riscv,
+ csr_1503_riscv,
+ csr_1504_riscv,
+ csr_1505_riscv,
+ csr_1506_riscv,
+ csr_1507_riscv,
+ csr_1508_riscv,
+ csr_1509_riscv,
+ csr_1510_riscv,
+ csr_1511_riscv,
+ csr_1512_riscv,
+ csr_1513_riscv,
+ csr_1514_riscv,
+ csr_1515_riscv,
+ csr_1516_riscv,
+ csr_1517_riscv,
+ csr_1518_riscv,
+ csr_1519_riscv,
+ csr_1520_riscv,
+ csr_1521_riscv,
+ csr_1522_riscv,
+ csr_1523_riscv,
+ csr_1524_riscv,
+ csr_1525_riscv,
+ csr_1526_riscv,
+ csr_1527_riscv,
+ csr_1528_riscv,
+ csr_1529_riscv,
+ csr_1530_riscv,
+ csr_1531_riscv,
+ csr_1532_riscv,
+ csr_1533_riscv,
+ csr_1534_riscv,
+ csr_1535_riscv,
+ csr_1536_riscv,
+ csr_1537_riscv,
+ csr_1538_riscv,
+ csr_1539_riscv,
+ csr_1540_riscv,
+ csr_1541_riscv,
+ csr_1542_riscv,
+ csr_1543_riscv,
+ csr_1544_riscv,
+ csr_1545_riscv,
+ csr_1546_riscv,
+ csr_1547_riscv,
+ csr_1548_riscv,
+ csr_1549_riscv,
+ csr_1550_riscv,
+ csr_1551_riscv,
+ csr_1552_riscv,
+ csr_1553_riscv,
+ csr_1554_riscv,
+ csr_1555_riscv,
+ csr_1556_riscv,
+ csr_1557_riscv,
+ csr_1558_riscv,
+ csr_1559_riscv,
+ csr_1560_riscv,
+ csr_1561_riscv,
+ csr_1562_riscv,
+ csr_1563_riscv,
+ csr_1564_riscv,
+ csr_1565_riscv,
+ csr_1566_riscv,
+ csr_1567_riscv,
+ csr_1568_riscv,
+ csr_1569_riscv,
+ csr_1570_riscv,
+ csr_1571_riscv,
+ csr_1572_riscv,
+ csr_1573_riscv,
+ csr_1574_riscv,
+ csr_1575_riscv,
+ csr_1576_riscv,
+ csr_1577_riscv,
+ csr_1578_riscv,
+ csr_1579_riscv,
+ csr_1580_riscv,
+ csr_1581_riscv,
+ csr_1582_riscv,
+ csr_1583_riscv,
+ csr_1584_riscv,
+ csr_1585_riscv,
+ csr_1586_riscv,
+ csr_1587_riscv,
+ csr_1588_riscv,
+ csr_1589_riscv,
+ csr_1590_riscv,
+ csr_1591_riscv,
+ csr_1592_riscv,
+ csr_1593_riscv,
+ csr_1594_riscv,
+ csr_1595_riscv,
+ csr_1596_riscv,
+ csr_1597_riscv,
+ csr_1598_riscv,
+ csr_1599_riscv,
+ csr_1600_riscv,
+ csr_1601_riscv,
+ csr_1602_riscv,
+ csr_1603_riscv,
+ csr_1604_riscv,
+ csr_1605_riscv,
+ csr_1606_riscv,
+ csr_1607_riscv,
+ csr_1608_riscv,
+ csr_1609_riscv,
+ csr_1610_riscv,
+ csr_1611_riscv,
+ csr_1612_riscv,
+ csr_1613_riscv,
+ csr_1614_riscv,
+ csr_1615_riscv,
+ csr_1616_riscv,
+ csr_1617_riscv,
+ csr_1618_riscv,
+ csr_1619_riscv,
+ csr_1620_riscv,
+ csr_1621_riscv,
+ csr_1622_riscv,
+ csr_1623_riscv,
+ csr_1624_riscv,
+ csr_1625_riscv,
+ csr_1626_riscv,
+ csr_1627_riscv,
+ csr_1628_riscv,
+ csr_1629_riscv,
+ csr_1630_riscv,
+ csr_1631_riscv,
+ csr_1632_riscv,
+ csr_1633_riscv,
+ csr_1634_riscv,
+ csr_1635_riscv,
+ csr_1636_riscv,
+ csr_1637_riscv,
+ csr_1638_riscv,
+ csr_1639_riscv,
+ csr_1640_riscv,
+ csr_1641_riscv,
+ csr_1642_riscv,
+ csr_1643_riscv,
+ csr_1644_riscv,
+ csr_1645_riscv,
+ csr_1646_riscv,
+ csr_1647_riscv,
+ csr_1648_riscv,
+ csr_1649_riscv,
+ csr_1650_riscv,
+ csr_1651_riscv,
+ csr_1652_riscv,
+ csr_1653_riscv,
+ csr_1654_riscv,
+ csr_1655_riscv,
+ csr_1656_riscv,
+ csr_1657_riscv,
+ csr_1658_riscv,
+ csr_1659_riscv,
+ csr_1660_riscv,
+ csr_1661_riscv,
+ csr_1662_riscv,
+ csr_1663_riscv,
+ csr_1664_riscv,
+ csr_1665_riscv,
+ csr_1666_riscv,
+ csr_1667_riscv,
+ csr_1668_riscv,
+ csr_1669_riscv,
+ csr_1670_riscv,
+ csr_1671_riscv,
+ csr_1672_riscv,
+ csr_1673_riscv,
+ csr_1674_riscv,
+ csr_1675_riscv,
+ csr_1676_riscv,
+ csr_1677_riscv,
+ csr_1678_riscv,
+ csr_1679_riscv,
+ csr_1680_riscv,
+ csr_1681_riscv,
+ csr_1682_riscv,
+ csr_1683_riscv,
+ csr_1684_riscv,
+ csr_1685_riscv,
+ csr_1686_riscv,
+ csr_1687_riscv,
+ csr_1688_riscv,
+ csr_1689_riscv,
+ csr_1690_riscv,
+ csr_1691_riscv,
+ csr_1692_riscv,
+ csr_1693_riscv,
+ csr_1694_riscv,
+ csr_1695_riscv,
+ csr_1696_riscv,
+ csr_1697_riscv,
+ csr_1698_riscv,
+ csr_1699_riscv,
+ csr_1700_riscv,
+ csr_1701_riscv,
+ csr_1702_riscv,
+ csr_1703_riscv,
+ csr_1704_riscv,
+ csr_1705_riscv,
+ csr_1706_riscv,
+ csr_1707_riscv,
+ csr_1708_riscv,
+ csr_1709_riscv,
+ csr_1710_riscv,
+ csr_1711_riscv,
+ csr_1712_riscv,
+ csr_1713_riscv,
+ csr_1714_riscv,
+ csr_1715_riscv,
+ csr_1716_riscv,
+ csr_1717_riscv,
+ csr_1718_riscv,
+ csr_1719_riscv,
+ csr_1720_riscv,
+ csr_1721_riscv,
+ csr_1722_riscv,
+ csr_1723_riscv,
+ csr_1724_riscv,
+ csr_1725_riscv,
+ csr_1726_riscv,
+ csr_1727_riscv,
+ csr_1728_riscv,
+ csr_1729_riscv,
+ csr_1730_riscv,
+ csr_1731_riscv,
+ csr_1732_riscv,
+ csr_1733_riscv,
+ csr_1734_riscv,
+ csr_1735_riscv,
+ csr_1736_riscv,
+ csr_1737_riscv,
+ csr_1738_riscv,
+ csr_1739_riscv,
+ csr_1740_riscv,
+ csr_1741_riscv,
+ csr_1742_riscv,
+ csr_1743_riscv,
+ csr_1744_riscv,
+ csr_1745_riscv,
+ csr_1746_riscv,
+ csr_1747_riscv,
+ csr_1748_riscv,
+ csr_1749_riscv,
+ csr_1750_riscv,
+ csr_1751_riscv,
+ csr_1752_riscv,
+ csr_1753_riscv,
+ csr_1754_riscv,
+ csr_1755_riscv,
+ csr_1756_riscv,
+ csr_1757_riscv,
+ csr_1758_riscv,
+ csr_1759_riscv,
+ csr_1760_riscv,
+ csr_1761_riscv,
+ csr_1762_riscv,
+ csr_1763_riscv,
+ csr_1764_riscv,
+ csr_1765_riscv,
+ csr_1766_riscv,
+ csr_1767_riscv,
+ csr_1768_riscv,
+ csr_1769_riscv,
+ csr_1770_riscv,
+ csr_1771_riscv,
+ csr_1772_riscv,
+ csr_1773_riscv,
+ csr_1774_riscv,
+ csr_1775_riscv,
+ csr_1776_riscv,
+ csr_1777_riscv,
+ csr_1778_riscv,
+ csr_1779_riscv,
+ csr_1780_riscv,
+ csr_1781_riscv,
+ csr_1782_riscv,
+ csr_1783_riscv,
+ csr_1784_riscv,
+ csr_1785_riscv,
+ csr_1786_riscv,
+ csr_1787_riscv,
+ csr_1788_riscv,
+ csr_1789_riscv,
+ csr_1790_riscv,
+ csr_1791_riscv,
+ csr_1792_riscv,
+ csr_1793_riscv,
+ csr_1794_riscv,
+ csr_1795_riscv,
+ csr_1796_riscv,
+ csr_1797_riscv,
+ csr_1798_riscv,
+ csr_1799_riscv,
+ csr_1800_riscv,
+ csr_1801_riscv,
+ csr_1802_riscv,
+ csr_1803_riscv,
+ csr_1804_riscv,
+ csr_1805_riscv,
+ csr_1806_riscv,
+ csr_1807_riscv,
+ csr_1808_riscv,
+ csr_1809_riscv,
+ csr_1810_riscv,
+ csr_1811_riscv,
+ csr_1812_riscv,
+ csr_1813_riscv,
+ csr_1814_riscv,
+ csr_1815_riscv,
+ csr_1816_riscv,
+ csr_1817_riscv,
+ csr_1818_riscv,
+ csr_1819_riscv,
+ csr_1820_riscv,
+ csr_1821_riscv,
+ csr_1822_riscv,
+ csr_1823_riscv,
+ csr_1824_riscv,
+ csr_1825_riscv,
+ csr_1826_riscv,
+ csr_1827_riscv,
+ csr_1828_riscv,
+ csr_1829_riscv,
+ csr_1830_riscv,
+ csr_1831_riscv,
+ csr_1832_riscv,
+ csr_1833_riscv,
+ csr_1834_riscv,
+ csr_1835_riscv,
+ csr_1836_riscv,
+ csr_1837_riscv,
+ csr_1838_riscv,
+ csr_1839_riscv,
+ csr_1840_riscv,
+ csr_1841_riscv,
+ csr_1842_riscv,
+ csr_1843_riscv,
+ csr_1844_riscv,
+ csr_1845_riscv,
+ csr_1846_riscv,
+ csr_1847_riscv,
+ csr_1848_riscv,
+ csr_1849_riscv,
+ csr_1850_riscv,
+ csr_1851_riscv,
+ csr_1852_riscv,
+ csr_1853_riscv,
+ csr_1854_riscv,
+ csr_1855_riscv,
+ csr_1856_riscv,
+ csr_1857_riscv,
+ csr_1858_riscv,
+ csr_1859_riscv,
+ csr_1860_riscv,
+ csr_1861_riscv,
+ csr_1862_riscv,
+ csr_1863_riscv,
+ csr_1864_riscv,
+ csr_1865_riscv,
+ csr_1866_riscv,
+ csr_1867_riscv,
+ csr_1868_riscv,
+ csr_1869_riscv,
+ csr_1870_riscv,
+ csr_1871_riscv,
+ csr_1872_riscv,
+ csr_1873_riscv,
+ csr_1874_riscv,
+ csr_1875_riscv,
+ csr_1876_riscv,
+ csr_1877_riscv,
+ csr_1878_riscv,
+ csr_1879_riscv,
+ csr_1880_riscv,
+ csr_1881_riscv,
+ csr_1882_riscv,
+ csr_1883_riscv,
+ csr_1884_riscv,
+ csr_1885_riscv,
+ csr_1886_riscv,
+ csr_1887_riscv,
+ csr_1888_riscv,
+ csr_1889_riscv,
+ csr_1890_riscv,
+ csr_1891_riscv,
+ csr_1892_riscv,
+ csr_1893_riscv,
+ csr_1894_riscv,
+ csr_1895_riscv,
+ csr_1896_riscv,
+ csr_1897_riscv,
+ csr_1898_riscv,
+ csr_1899_riscv,
+ csr_1900_riscv,
+ csr_1901_riscv,
+ csr_1902_riscv,
+ csr_1903_riscv,
+ csr_1904_riscv,
+ csr_1905_riscv,
+ csr_1906_riscv,
+ csr_1907_riscv,
+ csr_1908_riscv,
+ csr_1909_riscv,
+ csr_1910_riscv,
+ csr_1911_riscv,
+ csr_1912_riscv,
+ csr_1913_riscv,
+ csr_1914_riscv,
+ csr_1915_riscv,
+ csr_1916_riscv,
+ csr_1917_riscv,
+ csr_1918_riscv,
+ csr_1919_riscv,
+ csr_1920_riscv,
+ csr_1921_riscv,
+ csr_1922_riscv,
+ csr_1923_riscv,
+ csr_1924_riscv,
+ csr_1925_riscv,
+ csr_1926_riscv,
+ csr_1927_riscv,
+ csr_1928_riscv,
+ csr_1929_riscv,
+ csr_1930_riscv,
+ csr_1931_riscv,
+ csr_1932_riscv,
+ csr_1933_riscv,
+ csr_1934_riscv,
+ csr_1935_riscv,
+ csr_1936_riscv,
+ csr_1937_riscv,
+ csr_1938_riscv,
+ csr_1939_riscv,
+ csr_1940_riscv,
+ csr_1941_riscv,
+ csr_1942_riscv,
+ csr_1943_riscv,
+ csr_1944_riscv,
+ csr_1945_riscv,
+ csr_1946_riscv,
+ csr_1947_riscv,
+ csr_1948_riscv,
+ csr_1949_riscv,
+ csr_1950_riscv,
+ csr_1951_riscv,
+ csr_1952_riscv,
+ csr_1953_riscv,
+ csr_1954_riscv,
+ csr_1955_riscv,
+ csr_1956_riscv,
+ csr_1957_riscv,
+ csr_1958_riscv,
+ csr_1959_riscv,
+ csr_1960_riscv,
+ csr_1961_riscv,
+ csr_1962_riscv,
+ csr_1963_riscv,
+ csr_1964_riscv,
+ csr_1965_riscv,
+ csr_1966_riscv,
+ csr_1967_riscv,
+ csr_1968_riscv,
+ csr_1969_riscv,
+ csr_1970_riscv,
+ csr_1971_riscv,
+ csr_1972_riscv,
+ csr_1973_riscv,
+ csr_1974_riscv,
+ csr_1975_riscv,
+ csr_1976_riscv,
+ csr_1977_riscv,
+ csr_1978_riscv,
+ csr_1979_riscv,
+ csr_1980_riscv,
+ csr_1981_riscv,
+ csr_1982_riscv,
+ csr_1983_riscv,
+ csr_1984_riscv,
+ csr_1985_riscv,
+ csr_1986_riscv,
+ csr_1987_riscv,
+ csr_1988_riscv,
+ csr_1989_riscv,
+ csr_1990_riscv,
+ csr_1991_riscv,
+ csr_1992_riscv,
+ csr_1993_riscv,
+ csr_1994_riscv,
+ csr_1995_riscv,
+ csr_1996_riscv,
+ csr_1997_riscv,
+ csr_1998_riscv,
+ csr_1999_riscv,
+ csr_2000_riscv,
+ csr_2001_riscv,
+ csr_2002_riscv,
+ csr_2003_riscv,
+ csr_2004_riscv,
+ csr_2005_riscv,
+ csr_2006_riscv,
+ csr_2007_riscv,
+ csr_2008_riscv,
+ csr_2009_riscv,
+ csr_2010_riscv,
+ csr_2011_riscv,
+ csr_2012_riscv,
+ csr_2013_riscv,
+ csr_2014_riscv,
+ csr_2015_riscv,
+ csr_2016_riscv,
+ csr_2017_riscv,
+ csr_2018_riscv,
+ csr_2019_riscv,
+ csr_2020_riscv,
+ csr_2021_riscv,
+ csr_2022_riscv,
+ csr_2023_riscv,
+ csr_2024_riscv,
+ csr_2025_riscv,
+ csr_2026_riscv,
+ csr_2027_riscv,
+ csr_2028_riscv,
+ csr_2029_riscv,
+ csr_2030_riscv,
+ csr_2031_riscv,
+ csr_2032_riscv,
+ csr_2033_riscv,
+ csr_2034_riscv,
+ csr_2035_riscv,
+ csr_2036_riscv,
+ csr_2037_riscv,
+ csr_2038_riscv,
+ csr_2039_riscv,
+ csr_2040_riscv,
+ csr_2041_riscv,
+ csr_2042_riscv,
+ csr_2043_riscv,
+ csr_2044_riscv,
+ csr_2045_riscv,
+ csr_2046_riscv,
+ csr_2047_riscv,
+ csr_2048_riscv,
+ csr_2049_riscv,
+ csr_2050_riscv,
+ csr_2051_riscv,
+ csr_2052_riscv,
+ csr_2053_riscv,
+ csr_2054_riscv,
+ csr_2055_riscv,
+ csr_2056_riscv,
+ csr_2057_riscv,
+ csr_2058_riscv,
+ csr_2059_riscv,
+ csr_2060_riscv,
+ csr_2061_riscv,
+ csr_2062_riscv,
+ csr_2063_riscv,
+ csr_2064_riscv,
+ csr_2065_riscv,
+ csr_2066_riscv,
+ csr_2067_riscv,
+ csr_2068_riscv,
+ csr_2069_riscv,
+ csr_2070_riscv,
+ csr_2071_riscv,
+ csr_2072_riscv,
+ csr_2073_riscv,
+ csr_2074_riscv,
+ csr_2075_riscv,
+ csr_2076_riscv,
+ csr_2077_riscv,
+ csr_2078_riscv,
+ csr_2079_riscv,
+ csr_2080_riscv,
+ csr_2081_riscv,
+ csr_2082_riscv,
+ csr_2083_riscv,
+ csr_2084_riscv,
+ csr_2085_riscv,
+ csr_2086_riscv,
+ csr_2087_riscv,
+ csr_2088_riscv,
+ csr_2089_riscv,
+ csr_2090_riscv,
+ csr_2091_riscv,
+ csr_2092_riscv,
+ csr_2093_riscv,
+ csr_2094_riscv,
+ csr_2095_riscv,
+ csr_2096_riscv,
+ csr_2097_riscv,
+ csr_2098_riscv,
+ csr_2099_riscv,
+ csr_2100_riscv,
+ csr_2101_riscv,
+ csr_2102_riscv,
+ csr_2103_riscv,
+ csr_2104_riscv,
+ csr_2105_riscv,
+ csr_2106_riscv,
+ csr_2107_riscv,
+ csr_2108_riscv,
+ csr_2109_riscv,
+ csr_2110_riscv,
+ csr_2111_riscv,
+ csr_2112_riscv,
+ csr_2113_riscv,
+ csr_2114_riscv,
+ csr_2115_riscv,
+ csr_2116_riscv,
+ csr_2117_riscv,
+ csr_2118_riscv,
+ csr_2119_riscv,
+ csr_2120_riscv,
+ csr_2121_riscv,
+ csr_2122_riscv,
+ csr_2123_riscv,
+ csr_2124_riscv,
+ csr_2125_riscv,
+ csr_2126_riscv,
+ csr_2127_riscv,
+ csr_2128_riscv,
+ csr_2129_riscv,
+ csr_2130_riscv,
+ csr_2131_riscv,
+ csr_2132_riscv,
+ csr_2133_riscv,
+ csr_2134_riscv,
+ csr_2135_riscv,
+ csr_2136_riscv,
+ csr_2137_riscv,
+ csr_2138_riscv,
+ csr_2139_riscv,
+ csr_2140_riscv,
+ csr_2141_riscv,
+ csr_2142_riscv,
+ csr_2143_riscv,
+ csr_2144_riscv,
+ csr_2145_riscv,
+ csr_2146_riscv,
+ csr_2147_riscv,
+ csr_2148_riscv,
+ csr_2149_riscv,
+ csr_2150_riscv,
+ csr_2151_riscv,
+ csr_2152_riscv,
+ csr_2153_riscv,
+ csr_2154_riscv,
+ csr_2155_riscv,
+ csr_2156_riscv,
+ csr_2157_riscv,
+ csr_2158_riscv,
+ csr_2159_riscv,
+ csr_2160_riscv,
+ csr_2161_riscv,
+ csr_2162_riscv,
+ csr_2163_riscv,
+ csr_2164_riscv,
+ csr_2165_riscv,
+ csr_2166_riscv,
+ csr_2167_riscv,
+ csr_2168_riscv,
+ csr_2169_riscv,
+ csr_2170_riscv,
+ csr_2171_riscv,
+ csr_2172_riscv,
+ csr_2173_riscv,
+ csr_2174_riscv,
+ csr_2175_riscv,
+ csr_2176_riscv,
+ csr_2177_riscv,
+ csr_2178_riscv,
+ csr_2179_riscv,
+ csr_2180_riscv,
+ csr_2181_riscv,
+ csr_2182_riscv,
+ csr_2183_riscv,
+ csr_2184_riscv,
+ csr_2185_riscv,
+ csr_2186_riscv,
+ csr_2187_riscv,
+ csr_2188_riscv,
+ csr_2189_riscv,
+ csr_2190_riscv,
+ csr_2191_riscv,
+ csr_2192_riscv,
+ csr_2193_riscv,
+ csr_2194_riscv,
+ csr_2195_riscv,
+ csr_2196_riscv,
+ csr_2197_riscv,
+ csr_2198_riscv,
+ csr_2199_riscv,
+ csr_2200_riscv,
+ csr_2201_riscv,
+ csr_2202_riscv,
+ csr_2203_riscv,
+ csr_2204_riscv,
+ csr_2205_riscv,
+ csr_2206_riscv,
+ csr_2207_riscv,
+ csr_2208_riscv,
+ csr_2209_riscv,
+ csr_2210_riscv,
+ csr_2211_riscv,
+ csr_2212_riscv,
+ csr_2213_riscv,
+ csr_2214_riscv,
+ csr_2215_riscv,
+ csr_2216_riscv,
+ csr_2217_riscv,
+ csr_2218_riscv,
+ csr_2219_riscv,
+ csr_2220_riscv,
+ csr_2221_riscv,
+ csr_2222_riscv,
+ csr_2223_riscv,
+ csr_2224_riscv,
+ csr_2225_riscv,
+ csr_2226_riscv,
+ csr_2227_riscv,
+ csr_2228_riscv,
+ csr_2229_riscv,
+ csr_2230_riscv,
+ csr_2231_riscv,
+ csr_2232_riscv,
+ csr_2233_riscv,
+ csr_2234_riscv,
+ csr_2235_riscv,
+ csr_2236_riscv,
+ csr_2237_riscv,
+ csr_2238_riscv,
+ csr_2239_riscv,
+ csr_2240_riscv,
+ csr_2241_riscv,
+ csr_2242_riscv,
+ csr_2243_riscv,
+ csr_2244_riscv,
+ csr_2245_riscv,
+ csr_2246_riscv,
+ csr_2247_riscv,
+ csr_2248_riscv,
+ csr_2249_riscv,
+ csr_2250_riscv,
+ csr_2251_riscv,
+ csr_2252_riscv,
+ csr_2253_riscv,
+ csr_2254_riscv,
+ csr_2255_riscv,
+ csr_2256_riscv,
+ csr_2257_riscv,
+ csr_2258_riscv,
+ csr_2259_riscv,
+ csr_2260_riscv,
+ csr_2261_riscv,
+ csr_2262_riscv,
+ csr_2263_riscv,
+ csr_2264_riscv,
+ csr_2265_riscv,
+ csr_2266_riscv,
+ csr_2267_riscv,
+ csr_2268_riscv,
+ csr_2269_riscv,
+ csr_2270_riscv,
+ csr_2271_riscv,
+ csr_2272_riscv,
+ csr_2273_riscv,
+ csr_2274_riscv,
+ csr_2275_riscv,
+ csr_2276_riscv,
+ csr_2277_riscv,
+ csr_2278_riscv,
+ csr_2279_riscv,
+ csr_2280_riscv,
+ csr_2281_riscv,
+ csr_2282_riscv,
+ csr_2283_riscv,
+ csr_2284_riscv,
+ csr_2285_riscv,
+ csr_2286_riscv,
+ csr_2287_riscv,
+ csr_2288_riscv,
+ csr_2289_riscv,
+ csr_2290_riscv,
+ csr_2291_riscv,
+ csr_2292_riscv,
+ csr_2293_riscv,
+ csr_2294_riscv,
+ csr_2295_riscv,
+ csr_2296_riscv,
+ csr_2297_riscv,
+ csr_2298_riscv,
+ csr_2299_riscv,
+ csr_2300_riscv,
+ csr_2301_riscv,
+ csr_2302_riscv,
+ csr_2303_riscv,
+ csr_2304_riscv,
+ csr_2305_riscv,
+ csr_2306_riscv,
+ csr_2307_riscv,
+ csr_2308_riscv,
+ csr_2309_riscv,
+ csr_2310_riscv,
+ csr_2311_riscv,
+ csr_2312_riscv,
+ csr_2313_riscv,
+ csr_2314_riscv,
+ csr_2315_riscv,
+ csr_2316_riscv,
+ csr_2317_riscv,
+ csr_2318_riscv,
+ csr_2319_riscv,
+ csr_2320_riscv,
+ csr_2321_riscv,
+ csr_2322_riscv,
+ csr_2323_riscv,
+ csr_2324_riscv,
+ csr_2325_riscv,
+ csr_2326_riscv,
+ csr_2327_riscv,
+ csr_2328_riscv,
+ csr_2329_riscv,
+ csr_2330_riscv,
+ csr_2331_riscv,
+ csr_2332_riscv,
+ csr_2333_riscv,
+ csr_2334_riscv,
+ csr_2335_riscv,
+ csr_2336_riscv,
+ csr_2337_riscv,
+ csr_2338_riscv,
+ csr_2339_riscv,
+ csr_2340_riscv,
+ csr_2341_riscv,
+ csr_2342_riscv,
+ csr_2343_riscv,
+ csr_2344_riscv,
+ csr_2345_riscv,
+ csr_2346_riscv,
+ csr_2347_riscv,
+ csr_2348_riscv,
+ csr_2349_riscv,
+ csr_2350_riscv,
+ csr_2351_riscv,
+ csr_2352_riscv,
+ csr_2353_riscv,
+ csr_2354_riscv,
+ csr_2355_riscv,
+ csr_2356_riscv,
+ csr_2357_riscv,
+ csr_2358_riscv,
+ csr_2359_riscv,
+ csr_2360_riscv,
+ csr_2361_riscv,
+ csr_2362_riscv,
+ csr_2363_riscv,
+ csr_2364_riscv,
+ csr_2365_riscv,
+ csr_2366_riscv,
+ csr_2367_riscv,
+ csr_2368_riscv,
+ csr_2369_riscv,
+ csr_2370_riscv,
+ csr_2371_riscv,
+ csr_2372_riscv,
+ csr_2373_riscv,
+ csr_2374_riscv,
+ csr_2375_riscv,
+ csr_2376_riscv,
+ csr_2377_riscv,
+ csr_2378_riscv,
+ csr_2379_riscv,
+ csr_2380_riscv,
+ csr_2381_riscv,
+ csr_2382_riscv,
+ csr_2383_riscv,
+ csr_2384_riscv,
+ csr_2385_riscv,
+ csr_2386_riscv,
+ csr_2387_riscv,
+ csr_2388_riscv,
+ csr_2389_riscv,
+ csr_2390_riscv,
+ csr_2391_riscv,
+ csr_2392_riscv,
+ csr_2393_riscv,
+ csr_2394_riscv,
+ csr_2395_riscv,
+ csr_2396_riscv,
+ csr_2397_riscv,
+ csr_2398_riscv,
+ csr_2399_riscv,
+ csr_2400_riscv,
+ csr_2401_riscv,
+ csr_2402_riscv,
+ csr_2403_riscv,
+ csr_2404_riscv,
+ csr_2405_riscv,
+ csr_2406_riscv,
+ csr_2407_riscv,
+ csr_2408_riscv,
+ csr_2409_riscv,
+ csr_2410_riscv,
+ csr_2411_riscv,
+ csr_2412_riscv,
+ csr_2413_riscv,
+ csr_2414_riscv,
+ csr_2415_riscv,
+ csr_2416_riscv,
+ csr_2417_riscv,
+ csr_2418_riscv,
+ csr_2419_riscv,
+ csr_2420_riscv,
+ csr_2421_riscv,
+ csr_2422_riscv,
+ csr_2423_riscv,
+ csr_2424_riscv,
+ csr_2425_riscv,
+ csr_2426_riscv,
+ csr_2427_riscv,
+ csr_2428_riscv,
+ csr_2429_riscv,
+ csr_2430_riscv,
+ csr_2431_riscv,
+ csr_2432_riscv,
+ csr_2433_riscv,
+ csr_2434_riscv,
+ csr_2435_riscv,
+ csr_2436_riscv,
+ csr_2437_riscv,
+ csr_2438_riscv,
+ csr_2439_riscv,
+ csr_2440_riscv,
+ csr_2441_riscv,
+ csr_2442_riscv,
+ csr_2443_riscv,
+ csr_2444_riscv,
+ csr_2445_riscv,
+ csr_2446_riscv,
+ csr_2447_riscv,
+ csr_2448_riscv,
+ csr_2449_riscv,
+ csr_2450_riscv,
+ csr_2451_riscv,
+ csr_2452_riscv,
+ csr_2453_riscv,
+ csr_2454_riscv,
+ csr_2455_riscv,
+ csr_2456_riscv,
+ csr_2457_riscv,
+ csr_2458_riscv,
+ csr_2459_riscv,
+ csr_2460_riscv,
+ csr_2461_riscv,
+ csr_2462_riscv,
+ csr_2463_riscv,
+ csr_2464_riscv,
+ csr_2465_riscv,
+ csr_2466_riscv,
+ csr_2467_riscv,
+ csr_2468_riscv,
+ csr_2469_riscv,
+ csr_2470_riscv,
+ csr_2471_riscv,
+ csr_2472_riscv,
+ csr_2473_riscv,
+ csr_2474_riscv,
+ csr_2475_riscv,
+ csr_2476_riscv,
+ csr_2477_riscv,
+ csr_2478_riscv,
+ csr_2479_riscv,
+ csr_2480_riscv,
+ csr_2481_riscv,
+ csr_2482_riscv,
+ csr_2483_riscv,
+ csr_2484_riscv,
+ csr_2485_riscv,
+ csr_2486_riscv,
+ csr_2487_riscv,
+ csr_2488_riscv,
+ csr_2489_riscv,
+ csr_2490_riscv,
+ csr_2491_riscv,
+ csr_2492_riscv,
+ csr_2493_riscv,
+ csr_2494_riscv,
+ csr_2495_riscv,
+ csr_2496_riscv,
+ csr_2497_riscv,
+ csr_2498_riscv,
+ csr_2499_riscv,
+ csr_2500_riscv,
+ csr_2501_riscv,
+ csr_2502_riscv,
+ csr_2503_riscv,
+ csr_2504_riscv,
+ csr_2505_riscv,
+ csr_2506_riscv,
+ csr_2507_riscv,
+ csr_2508_riscv,
+ csr_2509_riscv,
+ csr_2510_riscv,
+ csr_2511_riscv,
+ csr_2512_riscv,
+ csr_2513_riscv,
+ csr_2514_riscv,
+ csr_2515_riscv,
+ csr_2516_riscv,
+ csr_2517_riscv,
+ csr_2518_riscv,
+ csr_2519_riscv,
+ csr_2520_riscv,
+ csr_2521_riscv,
+ csr_2522_riscv,
+ csr_2523_riscv,
+ csr_2524_riscv,
+ csr_2525_riscv,
+ csr_2526_riscv,
+ csr_2527_riscv,
+ csr_2528_riscv,
+ csr_2529_riscv,
+ csr_2530_riscv,
+ csr_2531_riscv,
+ csr_2532_riscv,
+ csr_2533_riscv,
+ csr_2534_riscv,
+ csr_2535_riscv,
+ csr_2536_riscv,
+ csr_2537_riscv,
+ csr_2538_riscv,
+ csr_2539_riscv,
+ csr_2540_riscv,
+ csr_2541_riscv,
+ csr_2542_riscv,
+ csr_2543_riscv,
+ csr_2544_riscv,
+ csr_2545_riscv,
+ csr_2546_riscv,
+ csr_2547_riscv,
+ csr_2548_riscv,
+ csr_2549_riscv,
+ csr_2550_riscv,
+ csr_2551_riscv,
+ csr_2552_riscv,
+ csr_2553_riscv,
+ csr_2554_riscv,
+ csr_2555_riscv,
+ csr_2556_riscv,
+ csr_2557_riscv,
+ csr_2558_riscv,
+ csr_2559_riscv,
+ csr_2560_riscv,
+ csr_2561_riscv,
+ csr_2562_riscv,
+ csr_2563_riscv,
+ csr_2564_riscv,
+ csr_2565_riscv,
+ csr_2566_riscv,
+ csr_2567_riscv,
+ csr_2568_riscv,
+ csr_2569_riscv,
+ csr_2570_riscv,
+ csr_2571_riscv,
+ csr_2572_riscv,
+ csr_2573_riscv,
+ csr_2574_riscv,
+ csr_2575_riscv,
+ csr_2576_riscv,
+ csr_2577_riscv,
+ csr_2578_riscv,
+ csr_2579_riscv,
+ csr_2580_riscv,
+ csr_2581_riscv,
+ csr_2582_riscv,
+ csr_2583_riscv,
+ csr_2584_riscv,
+ csr_2585_riscv,
+ csr_2586_riscv,
+ csr_2587_riscv,
+ csr_2588_riscv,
+ csr_2589_riscv,
+ csr_2590_riscv,
+ csr_2591_riscv,
+ csr_2592_riscv,
+ csr_2593_riscv,
+ csr_2594_riscv,
+ csr_2595_riscv,
+ csr_2596_riscv,
+ csr_2597_riscv,
+ csr_2598_riscv,
+ csr_2599_riscv,
+ csr_2600_riscv,
+ csr_2601_riscv,
+ csr_2602_riscv,
+ csr_2603_riscv,
+ csr_2604_riscv,
+ csr_2605_riscv,
+ csr_2606_riscv,
+ csr_2607_riscv,
+ csr_2608_riscv,
+ csr_2609_riscv,
+ csr_2610_riscv,
+ csr_2611_riscv,
+ csr_2612_riscv,
+ csr_2613_riscv,
+ csr_2614_riscv,
+ csr_2615_riscv,
+ csr_2616_riscv,
+ csr_2617_riscv,
+ csr_2618_riscv,
+ csr_2619_riscv,
+ csr_2620_riscv,
+ csr_2621_riscv,
+ csr_2622_riscv,
+ csr_2623_riscv,
+ csr_2624_riscv,
+ csr_2625_riscv,
+ csr_2626_riscv,
+ csr_2627_riscv,
+ csr_2628_riscv,
+ csr_2629_riscv,
+ csr_2630_riscv,
+ csr_2631_riscv,
+ csr_2632_riscv,
+ csr_2633_riscv,
+ csr_2634_riscv,
+ csr_2635_riscv,
+ csr_2636_riscv,
+ csr_2637_riscv,
+ csr_2638_riscv,
+ csr_2639_riscv,
+ csr_2640_riscv,
+ csr_2641_riscv,
+ csr_2642_riscv,
+ csr_2643_riscv,
+ csr_2644_riscv,
+ csr_2645_riscv,
+ csr_2646_riscv,
+ csr_2647_riscv,
+ csr_2648_riscv,
+ csr_2649_riscv,
+ csr_2650_riscv,
+ csr_2651_riscv,
+ csr_2652_riscv,
+ csr_2653_riscv,
+ csr_2654_riscv,
+ csr_2655_riscv,
+ csr_2656_riscv,
+ csr_2657_riscv,
+ csr_2658_riscv,
+ csr_2659_riscv,
+ csr_2660_riscv,
+ csr_2661_riscv,
+ csr_2662_riscv,
+ csr_2663_riscv,
+ csr_2664_riscv,
+ csr_2665_riscv,
+ csr_2666_riscv,
+ csr_2667_riscv,
+ csr_2668_riscv,
+ csr_2669_riscv,
+ csr_2670_riscv,
+ csr_2671_riscv,
+ csr_2672_riscv,
+ csr_2673_riscv,
+ csr_2674_riscv,
+ csr_2675_riscv,
+ csr_2676_riscv,
+ csr_2677_riscv,
+ csr_2678_riscv,
+ csr_2679_riscv,
+ csr_2680_riscv,
+ csr_2681_riscv,
+ csr_2682_riscv,
+ csr_2683_riscv,
+ csr_2684_riscv,
+ csr_2685_riscv,
+ csr_2686_riscv,
+ csr_2687_riscv,
+ csr_2688_riscv,
+ csr_2689_riscv,
+ csr_2690_riscv,
+ csr_2691_riscv,
+ csr_2692_riscv,
+ csr_2693_riscv,
+ csr_2694_riscv,
+ csr_2695_riscv,
+ csr_2696_riscv,
+ csr_2697_riscv,
+ csr_2698_riscv,
+ csr_2699_riscv,
+ csr_2700_riscv,
+ csr_2701_riscv,
+ csr_2702_riscv,
+ csr_2703_riscv,
+ csr_2704_riscv,
+ csr_2705_riscv,
+ csr_2706_riscv,
+ csr_2707_riscv,
+ csr_2708_riscv,
+ csr_2709_riscv,
+ csr_2710_riscv,
+ csr_2711_riscv,
+ csr_2712_riscv,
+ csr_2713_riscv,
+ csr_2714_riscv,
+ csr_2715_riscv,
+ csr_2716_riscv,
+ csr_2717_riscv,
+ csr_2718_riscv,
+ csr_2719_riscv,
+ csr_2720_riscv,
+ csr_2721_riscv,
+ csr_2722_riscv,
+ csr_2723_riscv,
+ csr_2724_riscv,
+ csr_2725_riscv,
+ csr_2726_riscv,
+ csr_2727_riscv,
+ csr_2728_riscv,
+ csr_2729_riscv,
+ csr_2730_riscv,
+ csr_2731_riscv,
+ csr_2732_riscv,
+ csr_2733_riscv,
+ csr_2734_riscv,
+ csr_2735_riscv,
+ csr_2736_riscv,
+ csr_2737_riscv,
+ csr_2738_riscv,
+ csr_2739_riscv,
+ csr_2740_riscv,
+ csr_2741_riscv,
+ csr_2742_riscv,
+ csr_2743_riscv,
+ csr_2744_riscv,
+ csr_2745_riscv,
+ csr_2746_riscv,
+ csr_2747_riscv,
+ csr_2748_riscv,
+ csr_2749_riscv,
+ csr_2750_riscv,
+ csr_2751_riscv,
+ csr_2752_riscv,
+ csr_2753_riscv,
+ csr_2754_riscv,
+ csr_2755_riscv,
+ csr_2756_riscv,
+ csr_2757_riscv,
+ csr_2758_riscv,
+ csr_2759_riscv,
+ csr_2760_riscv,
+ csr_2761_riscv,
+ csr_2762_riscv,
+ csr_2763_riscv,
+ csr_2764_riscv,
+ csr_2765_riscv,
+ csr_2766_riscv,
+ csr_2767_riscv,
+ csr_2768_riscv,
+ csr_2769_riscv,
+ csr_2770_riscv,
+ csr_2771_riscv,
+ csr_2772_riscv,
+ csr_2773_riscv,
+ csr_2774_riscv,
+ csr_2775_riscv,
+ csr_2776_riscv,
+ csr_2777_riscv,
+ csr_2778_riscv,
+ csr_2779_riscv,
+ csr_2780_riscv,
+ csr_2781_riscv,
+ csr_2782_riscv,
+ csr_2783_riscv,
+ csr_2784_riscv,
+ csr_2785_riscv,
+ csr_2786_riscv,
+ csr_2787_riscv,
+ csr_2788_riscv,
+ csr_2789_riscv,
+ csr_2790_riscv,
+ csr_2791_riscv,
+ csr_2792_riscv,
+ csr_2793_riscv,
+ csr_2794_riscv,
+ csr_2795_riscv,
+ csr_2796_riscv,
+ csr_2797_riscv,
+ csr_2798_riscv,
+ csr_2799_riscv,
+ csr_2800_riscv,
+ csr_2801_riscv,
+ csr_2802_riscv,
+ csr_2803_riscv,
+ csr_2804_riscv,
+ csr_2805_riscv,
+ csr_2806_riscv,
+ csr_2807_riscv,
+ csr_2808_riscv,
+ csr_2809_riscv,
+ csr_2810_riscv,
+ csr_2811_riscv,
+ csr_2812_riscv,
+ csr_2813_riscv,
+ csr_2814_riscv,
+ csr_2815_riscv,
+ csr_2816_riscv,
+ csr_2817_riscv,
+ csr_2818_riscv,
+ csr_2819_riscv,
+ csr_2820_riscv,
+ csr_2821_riscv,
+ csr_2822_riscv,
+ csr_2823_riscv,
+ csr_2824_riscv,
+ csr_2825_riscv,
+ csr_2826_riscv,
+ csr_2827_riscv,
+ csr_2828_riscv,
+ csr_2829_riscv,
+ csr_2830_riscv,
+ csr_2831_riscv,
+ csr_2832_riscv,
+ csr_2833_riscv,
+ csr_2834_riscv,
+ csr_2835_riscv,
+ csr_2836_riscv,
+ csr_2837_riscv,
+ csr_2838_riscv,
+ csr_2839_riscv,
+ csr_2840_riscv,
+ csr_2841_riscv,
+ csr_2842_riscv,
+ csr_2843_riscv,
+ csr_2844_riscv,
+ csr_2845_riscv,
+ csr_2846_riscv,
+ csr_2847_riscv,
+ csr_2848_riscv,
+ csr_2849_riscv,
+ csr_2850_riscv,
+ csr_2851_riscv,
+ csr_2852_riscv,
+ csr_2853_riscv,
+ csr_2854_riscv,
+ csr_2855_riscv,
+ csr_2856_riscv,
+ csr_2857_riscv,
+ csr_2858_riscv,
+ csr_2859_riscv,
+ csr_2860_riscv,
+ csr_2861_riscv,
+ csr_2862_riscv,
+ csr_2863_riscv,
+ csr_2864_riscv,
+ csr_2865_riscv,
+ csr_2866_riscv,
+ csr_2867_riscv,
+ csr_2868_riscv,
+ csr_2869_riscv,
+ csr_2870_riscv,
+ csr_2871_riscv,
+ csr_2872_riscv,
+ csr_2873_riscv,
+ csr_2874_riscv,
+ csr_2875_riscv,
+ csr_2876_riscv,
+ csr_2877_riscv,
+ csr_2878_riscv,
+ csr_2879_riscv,
+ csr_2880_riscv,
+ csr_2881_riscv,
+ csr_2882_riscv,
+ csr_2883_riscv,
+ csr_2884_riscv,
+ csr_2885_riscv,
+ csr_2886_riscv,
+ csr_2887_riscv,
+ csr_2888_riscv,
+ csr_2889_riscv,
+ csr_2890_riscv,
+ csr_2891_riscv,
+ csr_2892_riscv,
+ csr_2893_riscv,
+ csr_2894_riscv,
+ csr_2895_riscv,
+ csr_2896_riscv,
+ csr_2897_riscv,
+ csr_2898_riscv,
+ csr_2899_riscv,
+ csr_2900_riscv,
+ csr_2901_riscv,
+ csr_2902_riscv,
+ csr_2903_riscv,
+ csr_2904_riscv,
+ csr_2905_riscv,
+ csr_2906_riscv,
+ csr_2907_riscv,
+ csr_2908_riscv,
+ csr_2909_riscv,
+ csr_2910_riscv,
+ csr_2911_riscv,
+ csr_2912_riscv,
+ csr_2913_riscv,
+ csr_2914_riscv,
+ csr_2915_riscv,
+ csr_2916_riscv,
+ csr_2917_riscv,
+ csr_2918_riscv,
+ csr_2919_riscv,
+ csr_2920_riscv,
+ csr_2921_riscv,
+ csr_2922_riscv,
+ csr_2923_riscv,
+ csr_2924_riscv,
+ csr_2925_riscv,
+ csr_2926_riscv,
+ csr_2927_riscv,
+ csr_2928_riscv,
+ csr_2929_riscv,
+ csr_2930_riscv,
+ csr_2931_riscv,
+ csr_2932_riscv,
+ csr_2933_riscv,
+ csr_2934_riscv,
+ csr_2935_riscv,
+ csr_2936_riscv,
+ csr_2937_riscv,
+ csr_2938_riscv,
+ csr_2939_riscv,
+ csr_2940_riscv,
+ csr_2941_riscv,
+ csr_2942_riscv,
+ csr_2943_riscv,
+ csr_2944_riscv,
+ csr_2945_riscv,
+ csr_2946_riscv,
+ csr_2947_riscv,
+ csr_2948_riscv,
+ csr_2949_riscv,
+ csr_2950_riscv,
+ csr_2951_riscv,
+ csr_2952_riscv,
+ csr_2953_riscv,
+ csr_2954_riscv,
+ csr_2955_riscv,
+ csr_2956_riscv,
+ csr_2957_riscv,
+ csr_2958_riscv,
+ csr_2959_riscv,
+ csr_2960_riscv,
+ csr_2961_riscv,
+ csr_2962_riscv,
+ csr_2963_riscv,
+ csr_2964_riscv,
+ csr_2965_riscv,
+ csr_2966_riscv,
+ csr_2967_riscv,
+ csr_2968_riscv,
+ csr_2969_riscv,
+ csr_2970_riscv,
+ csr_2971_riscv,
+ csr_2972_riscv,
+ csr_2973_riscv,
+ csr_2974_riscv,
+ csr_2975_riscv,
+ csr_2976_riscv,
+ csr_2977_riscv,
+ csr_2978_riscv,
+ csr_2979_riscv,
+ csr_2980_riscv,
+ csr_2981_riscv,
+ csr_2982_riscv,
+ csr_2983_riscv,
+ csr_2984_riscv,
+ csr_2985_riscv,
+ csr_2986_riscv,
+ csr_2987_riscv,
+ csr_2988_riscv,
+ csr_2989_riscv,
+ csr_2990_riscv,
+ csr_2991_riscv,
+ csr_2992_riscv,
+ csr_2993_riscv,
+ csr_2994_riscv,
+ csr_2995_riscv,
+ csr_2996_riscv,
+ csr_2997_riscv,
+ csr_2998_riscv,
+ csr_2999_riscv,
+ csr_3000_riscv,
+ csr_3001_riscv,
+ csr_3002_riscv,
+ csr_3003_riscv,
+ csr_3004_riscv,
+ csr_3005_riscv,
+ csr_3006_riscv,
+ csr_3007_riscv,
+ csr_3008_riscv,
+ csr_3009_riscv,
+ csr_3010_riscv,
+ csr_3011_riscv,
+ csr_3012_riscv,
+ csr_3013_riscv,
+ csr_3014_riscv,
+ csr_3015_riscv,
+ csr_3016_riscv,
+ csr_3017_riscv,
+ csr_3018_riscv,
+ csr_3019_riscv,
+ csr_3020_riscv,
+ csr_3021_riscv,
+ csr_3022_riscv,
+ csr_3023_riscv,
+ csr_3024_riscv,
+ csr_3025_riscv,
+ csr_3026_riscv,
+ csr_3027_riscv,
+ csr_3028_riscv,
+ csr_3029_riscv,
+ csr_3030_riscv,
+ csr_3031_riscv,
+ csr_3032_riscv,
+ csr_3033_riscv,
+ csr_3034_riscv,
+ csr_3035_riscv,
+ csr_3036_riscv,
+ csr_3037_riscv,
+ csr_3038_riscv,
+ csr_3039_riscv,
+ csr_3040_riscv,
+ csr_3041_riscv,
+ csr_3042_riscv,
+ csr_3043_riscv,
+ csr_3044_riscv,
+ csr_3045_riscv,
+ csr_3046_riscv,
+ csr_3047_riscv,
+ csr_3048_riscv,
+ csr_3049_riscv,
+ csr_3050_riscv,
+ csr_3051_riscv,
+ csr_3052_riscv,
+ csr_3053_riscv,
+ csr_3054_riscv,
+ csr_3055_riscv,
+ csr_3056_riscv,
+ csr_3057_riscv,
+ csr_3058_riscv,
+ csr_3059_riscv,
+ csr_3060_riscv,
+ csr_3061_riscv,
+ csr_3062_riscv,
+ csr_3063_riscv,
+ csr_3064_riscv,
+ csr_3065_riscv,
+ csr_3066_riscv,
+ csr_3067_riscv,
+ csr_3068_riscv,
+ csr_3069_riscv,
+ csr_3070_riscv,
+ csr_3071_riscv,
+ csr_3072_riscv,
+ csr_3073_riscv,
+ csr_3074_riscv,
+ csr_3075_riscv,
+ csr_3076_riscv,
+ csr_3077_riscv,
+ csr_3078_riscv,
+ csr_3079_riscv,
+ csr_3080_riscv,
+ csr_3081_riscv,
+ csr_3082_riscv,
+ csr_3083_riscv,
+ csr_3084_riscv,
+ csr_3085_riscv,
+ csr_3086_riscv,
+ csr_3087_riscv,
+ csr_3088_riscv,
+ csr_3089_riscv,
+ csr_3090_riscv,
+ csr_3091_riscv,
+ csr_3092_riscv,
+ csr_3093_riscv,
+ csr_3094_riscv,
+ csr_3095_riscv,
+ csr_3096_riscv,
+ csr_3097_riscv,
+ csr_3098_riscv,
+ csr_3099_riscv,
+ csr_3100_riscv,
+ csr_3101_riscv,
+ csr_3102_riscv,
+ csr_3103_riscv,
+ csr_3104_riscv,
+ csr_3105_riscv,
+ csr_3106_riscv,
+ csr_3107_riscv,
+ csr_3108_riscv,
+ csr_3109_riscv,
+ csr_3110_riscv,
+ csr_3111_riscv,
+ csr_3112_riscv,
+ csr_3113_riscv,
+ csr_3114_riscv,
+ csr_3115_riscv,
+ csr_3116_riscv,
+ csr_3117_riscv,
+ csr_3118_riscv,
+ csr_3119_riscv,
+ csr_3120_riscv,
+ csr_3121_riscv,
+ csr_3122_riscv,
+ csr_3123_riscv,
+ csr_3124_riscv,
+ csr_3125_riscv,
+ csr_3126_riscv,
+ csr_3127_riscv,
+ csr_3128_riscv,
+ csr_3129_riscv,
+ csr_3130_riscv,
+ csr_3131_riscv,
+ csr_3132_riscv,
+ csr_3133_riscv,
+ csr_3134_riscv,
+ csr_3135_riscv,
+ csr_3136_riscv,
+ csr_3137_riscv,
+ csr_3138_riscv,
+ csr_3139_riscv,
+ csr_3140_riscv,
+ csr_3141_riscv,
+ csr_3142_riscv,
+ csr_3143_riscv,
+ csr_3144_riscv,
+ csr_3145_riscv,
+ csr_3146_riscv,
+ csr_3147_riscv,
+ csr_3148_riscv,
+ csr_3149_riscv,
+ csr_3150_riscv,
+ csr_3151_riscv,
+ csr_3152_riscv,
+ csr_3153_riscv,
+ csr_3154_riscv,
+ csr_3155_riscv,
+ csr_3156_riscv,
+ csr_3157_riscv,
+ csr_3158_riscv,
+ csr_3159_riscv,
+ csr_3160_riscv,
+ csr_3161_riscv,
+ csr_3162_riscv,
+ csr_3163_riscv,
+ csr_3164_riscv,
+ csr_3165_riscv,
+ csr_3166_riscv,
+ csr_3167_riscv,
+ csr_3168_riscv,
+ csr_3169_riscv,
+ csr_3170_riscv,
+ csr_3171_riscv,
+ csr_3172_riscv,
+ csr_3173_riscv,
+ csr_3174_riscv,
+ csr_3175_riscv,
+ csr_3176_riscv,
+ csr_3177_riscv,
+ csr_3178_riscv,
+ csr_3179_riscv,
+ csr_3180_riscv,
+ csr_3181_riscv,
+ csr_3182_riscv,
+ csr_3183_riscv,
+ csr_3184_riscv,
+ csr_3185_riscv,
+ csr_3186_riscv,
+ csr_3187_riscv,
+ csr_3188_riscv,
+ csr_3189_riscv,
+ csr_3190_riscv,
+ csr_3191_riscv,
+ csr_3192_riscv,
+ csr_3193_riscv,
+ csr_3194_riscv,
+ csr_3195_riscv,
+ csr_3196_riscv,
+ csr_3197_riscv,
+ csr_3198_riscv,
+ csr_3199_riscv,
+ csr_3200_riscv,
+ csr_3201_riscv,
+ csr_3202_riscv,
+ csr_3203_riscv,
+ csr_3204_riscv,
+ csr_3205_riscv,
+ csr_3206_riscv,
+ csr_3207_riscv,
+ csr_3208_riscv,
+ csr_3209_riscv,
+ csr_3210_riscv,
+ csr_3211_riscv,
+ csr_3212_riscv,
+ csr_3213_riscv,
+ csr_3214_riscv,
+ csr_3215_riscv,
+ csr_3216_riscv,
+ csr_3217_riscv,
+ csr_3218_riscv,
+ csr_3219_riscv,
+ csr_3220_riscv,
+ csr_3221_riscv,
+ csr_3222_riscv,
+ csr_3223_riscv,
+ csr_3224_riscv,
+ csr_3225_riscv,
+ csr_3226_riscv,
+ csr_3227_riscv,
+ csr_3228_riscv,
+ csr_3229_riscv,
+ csr_3230_riscv,
+ csr_3231_riscv,
+ csr_3232_riscv,
+ csr_3233_riscv,
+ csr_3234_riscv,
+ csr_3235_riscv,
+ csr_3236_riscv,
+ csr_3237_riscv,
+ csr_3238_riscv,
+ csr_3239_riscv,
+ csr_3240_riscv,
+ csr_3241_riscv,
+ csr_3242_riscv,
+ csr_3243_riscv,
+ csr_3244_riscv,
+ csr_3245_riscv,
+ csr_3246_riscv,
+ csr_3247_riscv,
+ csr_3248_riscv,
+ csr_3249_riscv,
+ csr_3250_riscv,
+ csr_3251_riscv,
+ csr_3252_riscv,
+ csr_3253_riscv,
+ csr_3254_riscv,
+ csr_3255_riscv,
+ csr_3256_riscv,
+ csr_3257_riscv,
+ csr_3258_riscv,
+ csr_3259_riscv,
+ csr_3260_riscv,
+ csr_3261_riscv,
+ csr_3262_riscv,
+ csr_3263_riscv,
+ csr_3264_riscv,
+ csr_3265_riscv,
+ csr_3266_riscv,
+ csr_3267_riscv,
+ csr_3268_riscv,
+ csr_3269_riscv,
+ csr_3270_riscv,
+ csr_3271_riscv,
+ csr_3272_riscv,
+ csr_3273_riscv,
+ csr_3274_riscv,
+ csr_3275_riscv,
+ csr_3276_riscv,
+ csr_3277_riscv,
+ csr_3278_riscv,
+ csr_3279_riscv,
+ csr_3280_riscv,
+ csr_3281_riscv,
+ csr_3282_riscv,
+ csr_3283_riscv,
+ csr_3284_riscv,
+ csr_3285_riscv,
+ csr_3286_riscv,
+ csr_3287_riscv,
+ csr_3288_riscv,
+ csr_3289_riscv,
+ csr_3290_riscv,
+ csr_3291_riscv,
+ csr_3292_riscv,
+ csr_3293_riscv,
+ csr_3294_riscv,
+ csr_3295_riscv,
+ csr_3296_riscv,
+ csr_3297_riscv,
+ csr_3298_riscv,
+ csr_3299_riscv,
+ csr_3300_riscv,
+ csr_3301_riscv,
+ csr_3302_riscv,
+ csr_3303_riscv,
+ csr_3304_riscv,
+ csr_3305_riscv,
+ csr_3306_riscv,
+ csr_3307_riscv,
+ csr_3308_riscv,
+ csr_3309_riscv,
+ csr_3310_riscv,
+ csr_3311_riscv,
+ csr_3312_riscv,
+ csr_3313_riscv,
+ csr_3314_riscv,
+ csr_3315_riscv,
+ csr_3316_riscv,
+ csr_3317_riscv,
+ csr_3318_riscv,
+ csr_3319_riscv,
+ csr_3320_riscv,
+ csr_3321_riscv,
+ csr_3322_riscv,
+ csr_3323_riscv,
+ csr_3324_riscv,
+ csr_3325_riscv,
+ csr_3326_riscv,
+ csr_3327_riscv,
+ csr_3328_riscv,
+ csr_3329_riscv,
+ csr_3330_riscv,
+ csr_3331_riscv,
+ csr_3332_riscv,
+ csr_3333_riscv,
+ csr_3334_riscv,
+ csr_3335_riscv,
+ csr_3336_riscv,
+ csr_3337_riscv,
+ csr_3338_riscv,
+ csr_3339_riscv,
+ csr_3340_riscv,
+ csr_3341_riscv,
+ csr_3342_riscv,
+ csr_3343_riscv,
+ csr_3344_riscv,
+ csr_3345_riscv,
+ csr_3346_riscv,
+ csr_3347_riscv,
+ csr_3348_riscv,
+ csr_3349_riscv,
+ csr_3350_riscv,
+ csr_3351_riscv,
+ csr_3352_riscv,
+ csr_3353_riscv,
+ csr_3354_riscv,
+ csr_3355_riscv,
+ csr_3356_riscv,
+ csr_3357_riscv,
+ csr_3358_riscv,
+ csr_3359_riscv,
+ csr_3360_riscv,
+ csr_3361_riscv,
+ csr_3362_riscv,
+ csr_3363_riscv,
+ csr_3364_riscv,
+ csr_3365_riscv,
+ csr_3366_riscv,
+ csr_3367_riscv,
+ csr_3368_riscv,
+ csr_3369_riscv,
+ csr_3370_riscv,
+ csr_3371_riscv,
+ csr_3372_riscv,
+ csr_3373_riscv,
+ csr_3374_riscv,
+ csr_3375_riscv,
+ csr_3376_riscv,
+ csr_3377_riscv,
+ csr_3378_riscv,
+ csr_3379_riscv,
+ csr_3380_riscv,
+ csr_3381_riscv,
+ csr_3382_riscv,
+ csr_3383_riscv,
+ csr_3384_riscv,
+ csr_3385_riscv,
+ csr_3386_riscv,
+ csr_3387_riscv,
+ csr_3388_riscv,
+ csr_3389_riscv,
+ csr_3390_riscv,
+ csr_3391_riscv,
+ csr_3392_riscv,
+ csr_3393_riscv,
+ csr_3394_riscv,
+ csr_3395_riscv,
+ csr_3396_riscv,
+ csr_3397_riscv,
+ csr_3398_riscv,
+ csr_3399_riscv,
+ csr_3400_riscv,
+ csr_3401_riscv,
+ csr_3402_riscv,
+ csr_3403_riscv,
+ csr_3404_riscv,
+ csr_3405_riscv,
+ csr_3406_riscv,
+ csr_3407_riscv,
+ csr_3408_riscv,
+ csr_3409_riscv,
+ csr_3410_riscv,
+ csr_3411_riscv,
+ csr_3412_riscv,
+ csr_3413_riscv,
+ csr_3414_riscv,
+ csr_3415_riscv,
+ csr_3416_riscv,
+ csr_3417_riscv,
+ csr_3418_riscv,
+ csr_3419_riscv,
+ csr_3420_riscv,
+ csr_3421_riscv,
+ csr_3422_riscv,
+ csr_3423_riscv,
+ csr_3424_riscv,
+ csr_3425_riscv,
+ csr_3426_riscv,
+ csr_3427_riscv,
+ csr_3428_riscv,
+ csr_3429_riscv,
+ csr_3430_riscv,
+ csr_3431_riscv,
+ csr_3432_riscv,
+ csr_3433_riscv,
+ csr_3434_riscv,
+ csr_3435_riscv,
+ csr_3436_riscv,
+ csr_3437_riscv,
+ csr_3438_riscv,
+ csr_3439_riscv,
+ csr_3440_riscv,
+ csr_3441_riscv,
+ csr_3442_riscv,
+ csr_3443_riscv,
+ csr_3444_riscv,
+ csr_3445_riscv,
+ csr_3446_riscv,
+ csr_3447_riscv,
+ csr_3448_riscv,
+ csr_3449_riscv,
+ csr_3450_riscv,
+ csr_3451_riscv,
+ csr_3452_riscv,
+ csr_3453_riscv,
+ csr_3454_riscv,
+ csr_3455_riscv,
+ csr_3456_riscv,
+ csr_3457_riscv,
+ csr_3458_riscv,
+ csr_3459_riscv,
+ csr_3460_riscv,
+ csr_3461_riscv,
+ csr_3462_riscv,
+ csr_3463_riscv,
+ csr_3464_riscv,
+ csr_3465_riscv,
+ csr_3466_riscv,
+ csr_3467_riscv,
+ csr_3468_riscv,
+ csr_3469_riscv,
+ csr_3470_riscv,
+ csr_3471_riscv,
+ csr_3472_riscv,
+ csr_3473_riscv,
+ csr_3474_riscv,
+ csr_3475_riscv,
+ csr_3476_riscv,
+ csr_3477_riscv,
+ csr_3478_riscv,
+ csr_3479_riscv,
+ csr_3480_riscv,
+ csr_3481_riscv,
+ csr_3482_riscv,
+ csr_3483_riscv,
+ csr_3484_riscv,
+ csr_3485_riscv,
+ csr_3486_riscv,
+ csr_3487_riscv,
+ csr_3488_riscv,
+ csr_3489_riscv,
+ csr_3490_riscv,
+ csr_3491_riscv,
+ csr_3492_riscv,
+ csr_3493_riscv,
+ csr_3494_riscv,
+ csr_3495_riscv,
+ csr_3496_riscv,
+ csr_3497_riscv,
+ csr_3498_riscv,
+ csr_3499_riscv,
+ csr_3500_riscv,
+ csr_3501_riscv,
+ csr_3502_riscv,
+ csr_3503_riscv,
+ csr_3504_riscv,
+ csr_3505_riscv,
+ csr_3506_riscv,
+ csr_3507_riscv,
+ csr_3508_riscv,
+ csr_3509_riscv,
+ csr_3510_riscv,
+ csr_3511_riscv,
+ csr_3512_riscv,
+ csr_3513_riscv,
+ csr_3514_riscv,
+ csr_3515_riscv,
+ csr_3516_riscv,
+ csr_3517_riscv,
+ csr_3518_riscv,
+ csr_3519_riscv,
+ csr_3520_riscv,
+ csr_3521_riscv,
+ csr_3522_riscv,
+ csr_3523_riscv,
+ csr_3524_riscv,
+ csr_3525_riscv,
+ csr_3526_riscv,
+ csr_3527_riscv,
+ csr_3528_riscv,
+ csr_3529_riscv,
+ csr_3530_riscv,
+ csr_3531_riscv,
+ csr_3532_riscv,
+ csr_3533_riscv,
+ csr_3534_riscv,
+ csr_3535_riscv,
+ csr_3536_riscv,
+ csr_3537_riscv,
+ csr_3538_riscv,
+ csr_3539_riscv,
+ csr_3540_riscv,
+ csr_3541_riscv,
+ csr_3542_riscv,
+ csr_3543_riscv,
+ csr_3544_riscv,
+ csr_3545_riscv,
+ csr_3546_riscv,
+ csr_3547_riscv,
+ csr_3548_riscv,
+ csr_3549_riscv,
+ csr_3550_riscv,
+ csr_3551_riscv,
+ csr_3552_riscv,
+ csr_3553_riscv,
+ csr_3554_riscv,
+ csr_3555_riscv,
+ csr_3556_riscv,
+ csr_3557_riscv,
+ csr_3558_riscv,
+ csr_3559_riscv,
+ csr_3560_riscv,
+ csr_3561_riscv,
+ csr_3562_riscv,
+ csr_3563_riscv,
+ csr_3564_riscv,
+ csr_3565_riscv,
+ csr_3566_riscv,
+ csr_3567_riscv,
+ csr_3568_riscv,
+ csr_3569_riscv,
+ csr_3570_riscv,
+ csr_3571_riscv,
+ csr_3572_riscv,
+ csr_3573_riscv,
+ csr_3574_riscv,
+ csr_3575_riscv,
+ csr_3576_riscv,
+ csr_3577_riscv,
+ csr_3578_riscv,
+ csr_3579_riscv,
+ csr_3580_riscv,
+ csr_3581_riscv,
+ csr_3582_riscv,
+ csr_3583_riscv,
+ csr_3584_riscv,
+ csr_3585_riscv,
+ csr_3586_riscv,
+ csr_3587_riscv,
+ csr_3588_riscv,
+ csr_3589_riscv,
+ csr_3590_riscv,
+ csr_3591_riscv,
+ csr_3592_riscv,
+ csr_3593_riscv,
+ csr_3594_riscv,
+ csr_3595_riscv,
+ csr_3596_riscv,
+ csr_3597_riscv,
+ csr_3598_riscv,
+ csr_3599_riscv,
+ csr_3600_riscv,
+ csr_3601_riscv,
+ csr_3602_riscv,
+ csr_3603_riscv,
+ csr_3604_riscv,
+ csr_3605_riscv,
+ csr_3606_riscv,
+ csr_3607_riscv,
+ csr_3608_riscv,
+ csr_3609_riscv,
+ csr_3610_riscv,
+ csr_3611_riscv,
+ csr_3612_riscv,
+ csr_3613_riscv,
+ csr_3614_riscv,
+ csr_3615_riscv,
+ csr_3616_riscv,
+ csr_3617_riscv,
+ csr_3618_riscv,
+ csr_3619_riscv,
+ csr_3620_riscv,
+ csr_3621_riscv,
+ csr_3622_riscv,
+ csr_3623_riscv,
+ csr_3624_riscv,
+ csr_3625_riscv,
+ csr_3626_riscv,
+ csr_3627_riscv,
+ csr_3628_riscv,
+ csr_3629_riscv,
+ csr_3630_riscv,
+ csr_3631_riscv,
+ csr_3632_riscv,
+ csr_3633_riscv,
+ csr_3634_riscv,
+ csr_3635_riscv,
+ csr_3636_riscv,
+ csr_3637_riscv,
+ csr_3638_riscv,
+ csr_3639_riscv,
+ csr_3640_riscv,
+ csr_3641_riscv,
+ csr_3642_riscv,
+ csr_3643_riscv,
+ csr_3644_riscv,
+ csr_3645_riscv,
+ csr_3646_riscv,
+ csr_3647_riscv,
+ csr_3648_riscv,
+ csr_3649_riscv,
+ csr_3650_riscv,
+ csr_3651_riscv,
+ csr_3652_riscv,
+ csr_3653_riscv,
+ csr_3654_riscv,
+ csr_3655_riscv,
+ csr_3656_riscv,
+ csr_3657_riscv,
+ csr_3658_riscv,
+ csr_3659_riscv,
+ csr_3660_riscv,
+ csr_3661_riscv,
+ csr_3662_riscv,
+ csr_3663_riscv,
+ csr_3664_riscv,
+ csr_3665_riscv,
+ csr_3666_riscv,
+ csr_3667_riscv,
+ csr_3668_riscv,
+ csr_3669_riscv,
+ csr_3670_riscv,
+ csr_3671_riscv,
+ csr_3672_riscv,
+ csr_3673_riscv,
+ csr_3674_riscv,
+ csr_3675_riscv,
+ csr_3676_riscv,
+ csr_3677_riscv,
+ csr_3678_riscv,
+ csr_3679_riscv,
+ csr_3680_riscv,
+ csr_3681_riscv,
+ csr_3682_riscv,
+ csr_3683_riscv,
+ csr_3684_riscv,
+ csr_3685_riscv,
+ csr_3686_riscv,
+ csr_3687_riscv,
+ csr_3688_riscv,
+ csr_3689_riscv,
+ csr_3690_riscv,
+ csr_3691_riscv,
+ csr_3692_riscv,
+ csr_3693_riscv,
+ csr_3694_riscv,
+ csr_3695_riscv,
+ csr_3696_riscv,
+ csr_3697_riscv,
+ csr_3698_riscv,
+ csr_3699_riscv,
+ csr_3700_riscv,
+ csr_3701_riscv,
+ csr_3702_riscv,
+ csr_3703_riscv,
+ csr_3704_riscv,
+ csr_3705_riscv,
+ csr_3706_riscv,
+ csr_3707_riscv,
+ csr_3708_riscv,
+ csr_3709_riscv,
+ csr_3710_riscv,
+ csr_3711_riscv,
+ csr_3712_riscv,
+ csr_3713_riscv,
+ csr_3714_riscv,
+ csr_3715_riscv,
+ csr_3716_riscv,
+ csr_3717_riscv,
+ csr_3718_riscv,
+ csr_3719_riscv,
+ csr_3720_riscv,
+ csr_3721_riscv,
+ csr_3722_riscv,
+ csr_3723_riscv,
+ csr_3724_riscv,
+ csr_3725_riscv,
+ csr_3726_riscv,
+ csr_3727_riscv,
+ csr_3728_riscv,
+ csr_3729_riscv,
+ csr_3730_riscv,
+ csr_3731_riscv,
+ csr_3732_riscv,
+ csr_3733_riscv,
+ csr_3734_riscv,
+ csr_3735_riscv,
+ csr_3736_riscv,
+ csr_3737_riscv,
+ csr_3738_riscv,
+ csr_3739_riscv,
+ csr_3740_riscv,
+ csr_3741_riscv,
+ csr_3742_riscv,
+ csr_3743_riscv,
+ csr_3744_riscv,
+ csr_3745_riscv,
+ csr_3746_riscv,
+ csr_3747_riscv,
+ csr_3748_riscv,
+ csr_3749_riscv,
+ csr_3750_riscv,
+ csr_3751_riscv,
+ csr_3752_riscv,
+ csr_3753_riscv,
+ csr_3754_riscv,
+ csr_3755_riscv,
+ csr_3756_riscv,
+ csr_3757_riscv,
+ csr_3758_riscv,
+ csr_3759_riscv,
+ csr_3760_riscv,
+ csr_3761_riscv,
+ csr_3762_riscv,
+ csr_3763_riscv,
+ csr_3764_riscv,
+ csr_3765_riscv,
+ csr_3766_riscv,
+ csr_3767_riscv,
+ csr_3768_riscv,
+ csr_3769_riscv,
+ csr_3770_riscv,
+ csr_3771_riscv,
+ csr_3772_riscv,
+ csr_3773_riscv,
+ csr_3774_riscv,
+ csr_3775_riscv,
+ csr_3776_riscv,
+ csr_3777_riscv,
+ csr_3778_riscv,
+ csr_3779_riscv,
+ csr_3780_riscv,
+ csr_3781_riscv,
+ csr_3782_riscv,
+ csr_3783_riscv,
+ csr_3784_riscv,
+ csr_3785_riscv,
+ csr_3786_riscv,
+ csr_3787_riscv,
+ csr_3788_riscv,
+ csr_3789_riscv,
+ csr_3790_riscv,
+ csr_3791_riscv,
+ csr_3792_riscv,
+ csr_3793_riscv,
+ csr_3794_riscv,
+ csr_3795_riscv,
+ csr_3796_riscv,
+ csr_3797_riscv,
+ csr_3798_riscv,
+ csr_3799_riscv,
+ csr_3800_riscv,
+ csr_3801_riscv,
+ csr_3802_riscv,
+ csr_3803_riscv,
+ csr_3804_riscv,
+ csr_3805_riscv,
+ csr_3806_riscv,
+ csr_3807_riscv,
+ csr_3808_riscv,
+ csr_3809_riscv,
+ csr_3810_riscv,
+ csr_3811_riscv,
+ csr_3812_riscv,
+ csr_3813_riscv,
+ csr_3814_riscv,
+ csr_3815_riscv,
+ csr_3816_riscv,
+ csr_3817_riscv,
+ csr_3818_riscv,
+ csr_3819_riscv,
+ csr_3820_riscv,
+ csr_3821_riscv,
+ csr_3822_riscv,
+ csr_3823_riscv,
+ csr_3824_riscv,
+ csr_3825_riscv,
+ csr_3826_riscv,
+ csr_3827_riscv,
+ csr_3828_riscv,
+ csr_3829_riscv,
+ csr_3830_riscv,
+ csr_3831_riscv,
+ csr_3832_riscv,
+ csr_3833_riscv,
+ csr_3834_riscv,
+ csr_3835_riscv,
+ csr_3836_riscv,
+ csr_3837_riscv,
+ csr_3838_riscv,
+ csr_3839_riscv,
+ csr_3840_riscv,
+ csr_3841_riscv,
+ csr_3842_riscv,
+ csr_3843_riscv,
+ csr_3844_riscv,
+ csr_3845_riscv,
+ csr_3846_riscv,
+ csr_3847_riscv,
+ csr_3848_riscv,
+ csr_3849_riscv,
+ csr_3850_riscv,
+ csr_3851_riscv,
+ csr_3852_riscv,
+ csr_3853_riscv,
+ csr_3854_riscv,
+ csr_3855_riscv,
+ csr_3856_riscv,
+ csr_3857_riscv,
+ csr_3858_riscv,
+ csr_3859_riscv,
+ csr_3860_riscv,
+ csr_3861_riscv,
+ csr_3862_riscv,
+ csr_3863_riscv,
+ csr_3864_riscv,
+ csr_3865_riscv,
+ csr_3866_riscv,
+ csr_3867_riscv,
+ csr_3868_riscv,
+ csr_3869_riscv,
+ csr_3870_riscv,
+ csr_3871_riscv,
+ csr_3872_riscv,
+ csr_3873_riscv,
+ csr_3874_riscv,
+ csr_3875_riscv,
+ csr_3876_riscv,
+ csr_3877_riscv,
+ csr_3878_riscv,
+ csr_3879_riscv,
+ csr_3880_riscv,
+ csr_3881_riscv,
+ csr_3882_riscv,
+ csr_3883_riscv,
+ csr_3884_riscv,
+ csr_3885_riscv,
+ csr_3886_riscv,
+ csr_3887_riscv,
+ csr_3888_riscv,
+ csr_3889_riscv,
+ csr_3890_riscv,
+ csr_3891_riscv,
+ csr_3892_riscv,
+ csr_3893_riscv,
+ csr_3894_riscv,
+ csr_3895_riscv,
+ csr_3896_riscv,
+ csr_3897_riscv,
+ csr_3898_riscv,
+ csr_3899_riscv,
+ csr_3900_riscv,
+ csr_3901_riscv,
+ csr_3902_riscv,
+ csr_3903_riscv,
+ csr_3904_riscv,
+ csr_3905_riscv,
+ csr_3906_riscv,
+ csr_3907_riscv,
+ csr_3908_riscv,
+ csr_3909_riscv,
+ csr_3910_riscv,
+ csr_3911_riscv,
+ csr_3912_riscv,
+ csr_3913_riscv,
+ csr_3914_riscv,
+ csr_3915_riscv,
+ csr_3916_riscv,
+ csr_3917_riscv,
+ csr_3918_riscv,
+ csr_3919_riscv,
+ csr_3920_riscv,
+ csr_3921_riscv,
+ csr_3922_riscv,
+ csr_3923_riscv,
+ csr_3924_riscv,
+ csr_3925_riscv,
+ csr_3926_riscv,
+ csr_3927_riscv,
+ csr_3928_riscv,
+ csr_3929_riscv,
+ csr_3930_riscv,
+ csr_3931_riscv,
+ csr_3932_riscv,
+ csr_3933_riscv,
+ csr_3934_riscv,
+ csr_3935_riscv,
+ csr_3936_riscv,
+ csr_3937_riscv,
+ csr_3938_riscv,
+ csr_3939_riscv,
+ csr_3940_riscv,
+ csr_3941_riscv,
+ csr_3942_riscv,
+ csr_3943_riscv,
+ csr_3944_riscv,
+ csr_3945_riscv,
+ csr_3946_riscv,
+ csr_3947_riscv,
+ csr_3948_riscv,
+ csr_3949_riscv,
+ csr_3950_riscv,
+ csr_3951_riscv,
+ csr_3952_riscv,
+ csr_3953_riscv,
+ csr_3954_riscv,
+ csr_3955_riscv,
+ csr_3956_riscv,
+ csr_3957_riscv,
+ csr_3958_riscv,
+ csr_3959_riscv,
+ csr_3960_riscv,
+ csr_3961_riscv,
+ csr_3962_riscv,
+ csr_3963_riscv,
+ csr_3964_riscv,
+ csr_3965_riscv,
+ csr_3966_riscv,
+ csr_3967_riscv,
+ csr_3968_riscv,
+ csr_3969_riscv,
+ csr_3970_riscv,
+ csr_3971_riscv,
+ csr_3972_riscv,
+ csr_3973_riscv,
+ csr_3974_riscv,
+ csr_3975_riscv,
+ csr_3976_riscv,
+ csr_3977_riscv,
+ csr_3978_riscv,
+ csr_3979_riscv,
+ csr_3980_riscv,
+ csr_3981_riscv,
+ csr_3982_riscv,
+ csr_3983_riscv,
+ csr_3984_riscv,
+ csr_3985_riscv,
+ csr_3986_riscv,
+ csr_3987_riscv,
+ csr_3988_riscv,
+ csr_3989_riscv,
+ csr_3990_riscv,
+ csr_3991_riscv,
+ csr_3992_riscv,
+ csr_3993_riscv,
+ csr_3994_riscv,
+ csr_3995_riscv,
+ csr_3996_riscv,
+ csr_3997_riscv,
+ csr_3998_riscv,
+ csr_3999_riscv,
+ csr_4000_riscv,
+ csr_4001_riscv,
+ csr_4002_riscv,
+ csr_4003_riscv,
+ csr_4004_riscv,
+ csr_4005_riscv,
+ csr_4006_riscv,
+ csr_4007_riscv,
+ csr_4008_riscv,
+ csr_4009_riscv,
+ csr_4010_riscv,
+ csr_4011_riscv,
+ csr_4012_riscv,
+ csr_4013_riscv,
+ csr_4014_riscv,
+ csr_4015_riscv,
+ csr_4016_riscv,
+ csr_4017_riscv,
+ csr_4018_riscv,
+ csr_4019_riscv,
+ csr_4020_riscv,
+ csr_4021_riscv,
+ csr_4022_riscv,
+ csr_4023_riscv,
+ csr_4024_riscv,
+ csr_4025_riscv,
+ csr_4026_riscv,
+ csr_4027_riscv,
+ csr_4028_riscv,
+ csr_4029_riscv,
+ csr_4030_riscv,
+ csr_4031_riscv,
+ csr_4032_riscv,
+ csr_4033_riscv,
+ csr_4034_riscv,
+ csr_4035_riscv,
+ csr_4036_riscv,
+ csr_4037_riscv,
+ csr_4038_riscv,
+ csr_4039_riscv,
+ csr_4040_riscv,
+ csr_4041_riscv,
+ csr_4042_riscv,
+ csr_4043_riscv,
+ csr_4044_riscv,
+ csr_4045_riscv,
+ csr_4046_riscv,
+ csr_4047_riscv,
+ csr_4048_riscv,
+ csr_4049_riscv,
+ csr_4050_riscv,
+ csr_4051_riscv,
+ csr_4052_riscv,
+ csr_4053_riscv,
+ csr_4054_riscv,
+ csr_4055_riscv,
+ csr_4056_riscv,
+ csr_4057_riscv,
+ csr_4058_riscv,
+ csr_4059_riscv,
+ csr_4060_riscv,
+ csr_4061_riscv,
+ csr_4062_riscv,
+ csr_4063_riscv,
+ csr_4064_riscv,
+ csr_4065_riscv,
+ csr_4066_riscv,
+ csr_4067_riscv,
+ csr_4068_riscv,
+ csr_4069_riscv,
+ csr_4070_riscv,
+ csr_4071_riscv,
+ csr_4072_riscv,
+ csr_4073_riscv,
+ csr_4074_riscv,
+ csr_4075_riscv,
+ csr_4076_riscv,
+ csr_4077_riscv,
+ csr_4078_riscv,
+ csr_4079_riscv,
+ csr_4080_riscv,
+ csr_4081_riscv,
+ csr_4082_riscv,
+ csr_4083_riscv,
+ csr_4084_riscv,
+ csr_4085_riscv,
+ csr_4086_riscv,
+ csr_4087_riscv,
+ csr_4088_riscv,
+ csr_4089_riscv,
+ csr_4090_riscv,
+ csr_4091_riscv,
+ csr_4092_riscv,
+ csr_4093_riscv,
+ csr_4094_riscv,
+ csr_4095_riscv,
+ csr_fflags_riscv = csr_1_riscv,
+ csr_frm_riscv = csr_2_riscv,
+ csr_fcsr_riscv = csr_3_riscv,
+ csr_vstart_riscv = csr_8_riscv,
+ csr_vxsat_riscv = csr_9_riscv,
+ csr_vxrm_riscv = csr_10_riscv,
+ csr_vcsr_riscv = csr_15_riscv,
+ csr_sstatus_riscv = csr_256_riscv,
+ csr_sie_riscv = csr_260_riscv,
+ csr_stvec_riscv = csr_261_riscv,
+ csr_scounteren_riscv = csr_262_riscv,
+ csr_senvcfg_riscv = csr_266_riscv,
+ csr_sstateen0_riscv = csr_268_riscv,
+ csr_sstateen1_riscv = csr_269_riscv,
+ csr_sstateen2_riscv = csr_270_riscv,
+ csr_sstateen3_riscv = csr_271_riscv,
+ csr_scountinhibit_riscv = csr_288_riscv,
+ csr_sscratch_riscv = csr_320_riscv,
+ csr_sepc_riscv = csr_321_riscv,
+ csr_scause_riscv = csr_322_riscv,
+ csr_stval_riscv = csr_323_riscv,
+ csr_sip_riscv = csr_324_riscv,
+ csr_satp_riscv = csr_384_riscv,
+ csr_vsstatus_riscv = csr_512_riscv,
+ csr_vsie_riscv = csr_516_riscv,
+ csr_vstvec_riscv = csr_517_riscv,
+ csr_vsscratch_riscv = csr_576_riscv,
+ csr_vsepc_riscv = csr_577_riscv,
+ csr_vscause_riscv = csr_578_riscv,
+ csr_vstval_riscv = csr_579_riscv,
+ csr_vsip_riscv = csr_580_riscv,
+ csr_vsatp_riscv = csr_640_riscv,
+ csr_mstatus_riscv = csr_768_riscv,
+ csr_misa_riscv = csr_769_riscv,
+ csr_medeleg_riscv = csr_770_riscv,
+ csr_mideleg_riscv = csr_771_riscv,
+ csr_mie_riscv = csr_772_riscv,
+ csr_mtvec_riscv = csr_773_riscv,
+ csr_mcounteren_riscv = csr_774_riscv,
+ csr_menvcfg_riscv = csr_778_riscv,
+ csr_mstateen0_riscv = csr_780_riscv,
+ csr_mstateen1_riscv = csr_781_riscv,
+ csr_mstateen2_riscv = csr_782_riscv,
+ csr_mstateen3_riscv = csr_783_riscv,
+ csr_mstatush_riscv = csr_784_riscv,
+ csr_medelegh_riscv = csr_786_riscv,
+ csr_menvcfgh_riscv = csr_794_riscv,
+ csr_mstateen0h_riscv = csr_796_riscv,
+ csr_mstateen1h_riscv = csr_797_riscv,
+ csr_mstateen2h_riscv = csr_798_riscv,
+ csr_mstateen3h_riscv = csr_799_riscv,
+ csr_mcountinhibit_riscv = csr_800_riscv,
+ csr_mhpmevent3_riscv = csr_803_riscv,
+ csr_mhpmevent4_riscv = csr_804_riscv,
+ csr_mhpmevent5_riscv = csr_805_riscv,
+ csr_mhpmevent6_riscv = csr_806_riscv,
+ csr_mhpmevent7_riscv = csr_807_riscv,
+ csr_mhpmevent8_riscv = csr_808_riscv,
+ csr_mhpmevent9_riscv = csr_809_riscv,
+ csr_mhpmevent10_riscv = csr_810_riscv,
+ csr_mhpmevent11_riscv = csr_811_riscv,
+ csr_mhpmevent12_riscv = csr_812_riscv,
+ csr_mhpmevent13_riscv = csr_813_riscv,
+ csr_mhpmevent14_riscv = csr_814_riscv,
+ csr_mhpmevent15_riscv = csr_815_riscv,
+ csr_mhpmevent16_riscv = csr_816_riscv,
+ csr_mhpmevent17_riscv = csr_817_riscv,
+ csr_mhpmevent18_riscv = csr_818_riscv,
+ csr_mhpmevent19_riscv = csr_819_riscv,
+ csr_mhpmevent20_riscv = csr_820_riscv,
+ csr_mhpmevent21_riscv = csr_821_riscv,
+ csr_mhpmevent22_riscv = csr_822_riscv,
+ csr_mhpmevent23_riscv = csr_823_riscv,
+ csr_mhpmevent24_riscv = csr_824_riscv,
+ csr_mhpmevent25_riscv = csr_825_riscv,
+ csr_mhpmevent26_riscv = csr_826_riscv,
+ csr_mhpmevent27_riscv = csr_827_riscv,
+ csr_mhpmevent28_riscv = csr_828_riscv,
+ csr_mhpmevent29_riscv = csr_829_riscv,
+ csr_mhpmevent30_riscv = csr_830_riscv,
+ csr_mhpmevent31_riscv = csr_831_riscv,
+ csr_mscratch_riscv = csr_832_riscv,
+ csr_mepc_riscv = csr_833_riscv,
+ csr_mcause_riscv = csr_834_riscv,
+ csr_mtval_riscv = csr_835_riscv,
+ csr_mip_riscv = csr_836_riscv,
+ csr_mtinst_riscv = csr_842_riscv,
+ csr_mtval2_riscv = csr_843_riscv,
+ csr_pmpcfg0_riscv = csr_928_riscv,
+ csr_pmpcfg1_riscv = csr_929_riscv,
+ csr_pmpcfg2_riscv = csr_930_riscv,
+ csr_pmpcfg3_riscv = csr_931_riscv,
+ csr_pmpcfg4_riscv = csr_932_riscv,
+ csr_pmpcfg5_riscv = csr_933_riscv,
+ csr_pmpcfg6_riscv = csr_934_riscv,
+ csr_pmpcfg7_riscv = csr_935_riscv,
+ csr_pmpcfg8_riscv = csr_936_riscv,
+ csr_pmpcfg9_riscv = csr_937_riscv,
+ csr_pmpcfg10_riscv = csr_938_riscv,
+ csr_pmpcfg11_riscv = csr_939_riscv,
+ csr_pmpcfg12_riscv = csr_940_riscv,
+ csr_pmpcfg13_riscv = csr_941_riscv,
+ csr_pmpcfg14_riscv = csr_942_riscv,
+ csr_pmpcfg15_riscv = csr_943_riscv,
+ csr_pmpaddr0_riscv = csr_944_riscv,
+ csr_pmpaddr1_riscv = csr_945_riscv,
+ csr_pmpaddr2_riscv = csr_946_riscv,
+ csr_pmpaddr3_riscv = csr_947_riscv,
+ csr_pmpaddr4_riscv = csr_948_riscv,
+ csr_pmpaddr5_riscv = csr_949_riscv,
+ csr_pmpaddr6_riscv = csr_950_riscv,
+ csr_pmpaddr7_riscv = csr_951_riscv,
+ csr_pmpaddr8_riscv = csr_952_riscv,
+ csr_pmpaddr9_riscv = csr_953_riscv,
+ csr_pmpaddr10_riscv = csr_954_riscv,
+ csr_pmpaddr11_riscv = csr_955_riscv,
+ csr_pmpaddr12_riscv = csr_956_riscv,
+ csr_pmpaddr13_riscv = csr_957_riscv,
+ csr_pmpaddr14_riscv = csr_958_riscv,
+ csr_pmpaddr15_riscv = csr_959_riscv,
+ csr_pmpaddr16_riscv = csr_960_riscv,
+ csr_pmpaddr17_riscv = csr_961_riscv,
+ csr_pmpaddr18_riscv = csr_962_riscv,
+ csr_pmpaddr19_riscv = csr_963_riscv,
+ csr_pmpaddr20_riscv = csr_964_riscv,
+ csr_pmpaddr21_riscv = csr_965_riscv,
+ csr_pmpaddr22_riscv = csr_966_riscv,
+ csr_pmpaddr23_riscv = csr_967_riscv,
+ csr_pmpaddr24_riscv = csr_968_riscv,
+ csr_pmpaddr25_riscv = csr_969_riscv,
+ csr_pmpaddr26_riscv = csr_970_riscv,
+ csr_pmpaddr27_riscv = csr_971_riscv,
+ csr_pmpaddr28_riscv = csr_972_riscv,
+ csr_pmpaddr29_riscv = csr_973_riscv,
+ csr_pmpaddr30_riscv = csr_974_riscv,
+ csr_pmpaddr31_riscv = csr_975_riscv,
+ csr_pmpaddr32_riscv = csr_976_riscv,
+ csr_pmpaddr33_riscv = csr_977_riscv,
+ csr_pmpaddr34_riscv = csr_978_riscv,
+ csr_pmpaddr35_riscv = csr_979_riscv,
+ csr_pmpaddr36_riscv = csr_980_riscv,
+ csr_pmpaddr37_riscv = csr_981_riscv,
+ csr_pmpaddr38_riscv = csr_982_riscv,
+ csr_pmpaddr39_riscv = csr_983_riscv,
+ csr_pmpaddr40_riscv = csr_984_riscv,
+ csr_pmpaddr41_riscv = csr_985_riscv,
+ csr_pmpaddr42_riscv = csr_986_riscv,
+ csr_pmpaddr43_riscv = csr_987_riscv,
+ csr_pmpaddr44_riscv = csr_988_riscv,
+ csr_pmpaddr45_riscv = csr_989_riscv,
+ csr_pmpaddr46_riscv = csr_990_riscv,
+ csr_pmpaddr47_riscv = csr_991_riscv,
+ csr_pmpaddr48_riscv = csr_992_riscv,
+ csr_pmpaddr49_riscv = csr_993_riscv,
+ csr_pmpaddr50_riscv = csr_994_riscv,
+ csr_pmpaddr51_riscv = csr_995_riscv,
+ csr_pmpaddr52_riscv = csr_996_riscv,
+ csr_pmpaddr53_riscv = csr_997_riscv,
+ csr_pmpaddr54_riscv = csr_998_riscv,
+ csr_pmpaddr55_riscv = csr_999_riscv,
+ csr_pmpaddr56_riscv = csr_1000_riscv,
+ csr_pmpaddr57_riscv = csr_1001_riscv,
+ csr_pmpaddr58_riscv = csr_1002_riscv,
+ csr_pmpaddr59_riscv = csr_1003_riscv,
+ csr_pmpaddr60_riscv = csr_1004_riscv,
+ csr_pmpaddr61_riscv = csr_1005_riscv,
+ csr_pmpaddr62_riscv = csr_1006_riscv,
+ csr_pmpaddr63_riscv = csr_1007_riscv,
+ csr_scontext_riscv = csr_1448_riscv,
+ csr_hstatus_riscv = csr_1536_riscv,
+ csr_hedeleg_riscv = csr_1538_riscv,
+ csr_hideleg_riscv = csr_1539_riscv,
+ csr_hie_riscv = csr_1540_riscv,
+ csr_htimedelta_riscv = csr_1541_riscv,
+ csr_hcounteren_riscv = csr_1542_riscv,
+ csr_hgeie_riscv = csr_1543_riscv,
+ csr_henvcfg_riscv = csr_1546_riscv,
+ csr_hstateen0_riscv = csr_1548_riscv,
+ csr_hstateen1_riscv = csr_1549_riscv,
+ csr_hstateen2_riscv = csr_1550_riscv,
+ csr_hstateen3_riscv = csr_1551_riscv,
+ csr_hedelegh_riscv = csr_1554_riscv,
+ csr_htimedeltah_riscv = csr_1557_riscv,
+ csr_henvcfgh_riscv = csr_1562_riscv,
+ csr_hstateen0h_riscv = csr_1564_riscv,
+ csr_hstateen1h_riscv = csr_1565_riscv,
+ csr_hstateen2h_riscv = csr_1566_riscv,
+ csr_hstateen3h_riscv = csr_1567_riscv,
+ csr_htval_riscv = csr_1603_riscv,
+ csr_hip_riscv = csr_1604_riscv,
+ csr_hvip_riscv = csr_1605_riscv,
+ csr_htinst_riscv = csr_1610_riscv,
+ csr_hgatp_riscv = csr_1664_riscv,
+ csr_hcontext_riscv = csr_1704_riscv,
+ csr_mhpmevent3h_riscv = csr_1827_riscv,
+ csr_mhpmevent4h_riscv = csr_1828_riscv,
+ csr_mhpmevent5h_riscv = csr_1829_riscv,
+ csr_mhpmevent6h_riscv = csr_1830_riscv,
+ csr_mhpmevent7h_riscv = csr_1831_riscv,
+ csr_mhpmevent8h_riscv = csr_1832_riscv,
+ csr_mhpmevent9h_riscv = csr_1833_riscv,
+ csr_mhpmevent10h_riscv = csr_1834_riscv,
+ csr_mhpmevent11h_riscv = csr_1835_riscv,
+ csr_mhpmevent12h_riscv = csr_1836_riscv,
+ csr_mhpmevent13h_riscv = csr_1837_riscv,
+ csr_mhpmevent14h_riscv = csr_1838_riscv,
+ csr_mhpmevent15h_riscv = csr_1839_riscv,
+ csr_mhpmevent16h_riscv = csr_1840_riscv,
+ csr_mhpmevent17h_riscv = csr_1841_riscv,
+ csr_mhpmevent18h_riscv = csr_1842_riscv,
+ csr_mhpmevent19h_riscv = csr_1843_riscv,
+ csr_mhpmevent20h_riscv = csr_1844_riscv,
+ csr_mhpmevent21h_riscv = csr_1845_riscv,
+ csr_mhpmevent22h_riscv = csr_1846_riscv,
+ csr_mhpmevent23h_riscv = csr_1847_riscv,
+ csr_mhpmevent24h_riscv = csr_1848_riscv,
+ csr_mhpmevent25h_riscv = csr_1849_riscv,
+ csr_mhpmevent26h_riscv = csr_1850_riscv,
+ csr_mhpmevent27h_riscv = csr_1851_riscv,
+ csr_mhpmevent28h_riscv = csr_1852_riscv,
+ csr_mhpmevent29h_riscv = csr_1853_riscv,
+ csr_mhpmevent30h_riscv = csr_1854_riscv,
+ csr_mhpmevent31h_riscv = csr_1855_riscv,
+ csr_mnscratch_riscv = csr_1856_riscv,
+ csr_mnepc_riscv = csr_1857_riscv,
+ csr_mncause_riscv = csr_1858_riscv,
+ csr_mnstatus_riscv = csr_1860_riscv,
+ csr_mseccfg_riscv = csr_1863_riscv,
+ csr_mseccfgh_riscv = csr_1879_riscv,
+ csr_tselect_riscv = csr_1952_riscv,
+ csr_tdata1_riscv = csr_1953_riscv,
+ csr_tdata2_riscv = csr_1954_riscv,
+ csr_tdata3_riscv = csr_1955_riscv,
+ csr_mcontext_riscv = csr_1960_riscv,
+ csr_dcsr_riscv = csr_1968_riscv,
+ csr_dpc_riscv = csr_1969_riscv,
+ csr_dscratch0_riscv = csr_1970_riscv,
+ csr_dscratch1_riscv = csr_1971_riscv,
+ csr_mcycle_riscv = csr_2816_riscv,
+ csr_minstret_riscv = csr_2818_riscv,
+ csr_mhpmcounter3_riscv = csr_2819_riscv,
+ csr_mhpmcounter4_riscv = csr_2820_riscv,
+ csr_mhpmcounter5_riscv = csr_2821_riscv,
+ csr_mhpmcounter6_riscv = csr_2822_riscv,
+ csr_mhpmcounter7_riscv = csr_2823_riscv,
+ csr_mhpmcounter8_riscv = csr_2824_riscv,
+ csr_mhpmcounter9_riscv = csr_2825_riscv,
+ csr_mhpmcounter10_riscv = csr_2826_riscv,
+ csr_mhpmcounter11_riscv = csr_2827_riscv,
+ csr_mhpmcounter12_riscv = csr_2828_riscv,
+ csr_mhpmcounter13_riscv = csr_2829_riscv,
+ csr_mhpmcounter14_riscv = csr_2830_riscv,
+ csr_mhpmcounter15_riscv = csr_2831_riscv,
+ csr_mhpmcounter16_riscv = csr_2832_riscv,
+ csr_mhpmcounter17_riscv = csr_2833_riscv,
+ csr_mhpmcounter18_riscv = csr_2834_riscv,
+ csr_mhpmcounter19_riscv = csr_2835_riscv,
+ csr_mhpmcounter20_riscv = csr_2836_riscv,
+ csr_mhpmcounter21_riscv = csr_2837_riscv,
+ csr_mhpmcounter22_riscv = csr_2838_riscv,
+ csr_mhpmcounter23_riscv = csr_2839_riscv,
+ csr_mhpmcounter24_riscv = csr_2840_riscv,
+ csr_mhpmcounter25_riscv = csr_2841_riscv,
+ csr_mhpmcounter26_riscv = csr_2842_riscv,
+ csr_mhpmcounter27_riscv = csr_2843_riscv,
+ csr_mhpmcounter28_riscv = csr_2844_riscv,
+ csr_mhpmcounter29_riscv = csr_2845_riscv,
+ csr_mhpmcounter30_riscv = csr_2846_riscv,
+ csr_mhpmcounter31_riscv = csr_2847_riscv,
+ csr_mcycleh_riscv = csr_2944_riscv,
+ csr_minstreth_riscv = csr_2946_riscv,
+ csr_mhpmcounter3h_riscv = csr_2947_riscv,
+ csr_mhpmcounter4h_riscv = csr_2948_riscv,
+ csr_mhpmcounter5h_riscv = csr_2949_riscv,
+ csr_mhpmcounter6h_riscv = csr_2950_riscv,
+ csr_mhpmcounter7h_riscv = csr_2951_riscv,
+ csr_mhpmcounter8h_riscv = csr_2952_riscv,
+ csr_mhpmcounter9h_riscv = csr_2953_riscv,
+ csr_mhpmcounter10h_riscv = csr_2954_riscv,
+ csr_mhpmcounter11h_riscv = csr_2955_riscv,
+ csr_mhpmcounter12h_riscv = csr_2956_riscv,
+ csr_mhpmcounter13h_riscv = csr_2957_riscv,
+ csr_mhpmcounter14h_riscv = csr_2958_riscv,
+ csr_mhpmcounter15h_riscv = csr_2959_riscv,
+ csr_mhpmcounter16h_riscv = csr_2960_riscv,
+ csr_mhpmcounter17h_riscv = csr_2961_riscv,
+ csr_mhpmcounter18h_riscv = csr_2962_riscv,
+ csr_mhpmcounter19h_riscv = csr_2963_riscv,
+ csr_mhpmcounter20h_riscv = csr_2964_riscv,
+ csr_mhpmcounter21h_riscv = csr_2965_riscv,
+ csr_mhpmcounter22h_riscv = csr_2966_riscv,
+ csr_mhpmcounter23h_riscv = csr_2967_riscv,
+ csr_mhpmcounter24h_riscv = csr_2968_riscv,
+ csr_mhpmcounter25h_riscv = csr_2969_riscv,
+ csr_mhpmcounter26h_riscv = csr_2970_riscv,
+ csr_mhpmcounter27h_riscv = csr_2971_riscv,
+ csr_mhpmcounter28h_riscv = csr_2972_riscv,
+ csr_mhpmcounter29h_riscv = csr_2973_riscv,
+ csr_mhpmcounter30h_riscv = csr_2974_riscv,
+ csr_mhpmcounter31h_riscv = csr_2975_riscv,
+ csr_cycle_riscv = csr_3072_riscv,
+ csr_time_riscv = csr_3073_riscv,
+ csr_instret_riscv = csr_3074_riscv,
+ csr_hpmcounter3_riscv = csr_3075_riscv,
+ csr_hpmcounter4_riscv = csr_3076_riscv,
+ csr_hpmcounter5_riscv = csr_3077_riscv,
+ csr_hpmcounter6_riscv = csr_3078_riscv,
+ csr_hpmcounter7_riscv = csr_3079_riscv,
+ csr_hpmcounter8_riscv = csr_3080_riscv,
+ csr_hpmcounter9_riscv = csr_3081_riscv,
+ csr_hpmcounter10_riscv = csr_3082_riscv,
+ csr_hpmcounter11_riscv = csr_3083_riscv,
+ csr_hpmcounter12_riscv = csr_3084_riscv,
+ csr_hpmcounter13_riscv = csr_3085_riscv,
+ csr_hpmcounter14_riscv = csr_3086_riscv,
+ csr_hpmcounter15_riscv = csr_3087_riscv,
+ csr_hpmcounter16_riscv = csr_3088_riscv,
+ csr_hpmcounter17_riscv = csr_3089_riscv,
+ csr_hpmcounter18_riscv = csr_3090_riscv,
+ csr_hpmcounter19_riscv = csr_3091_riscv,
+ csr_hpmcounter20_riscv = csr_3092_riscv,
+ csr_hpmcounter21_riscv = csr_3093_riscv,
+ csr_hpmcounter22_riscv = csr_3094_riscv,
+ csr_hpmcounter23_riscv = csr_3095_riscv,
+ csr_hpmcounter24_riscv = csr_3096_riscv,
+ csr_hpmcounter25_riscv = csr_3097_riscv,
+ csr_hpmcounter26_riscv = csr_3098_riscv,
+ csr_hpmcounter27_riscv = csr_3099_riscv,
+ csr_hpmcounter28_riscv = csr_3100_riscv,
+ csr_hpmcounter29_riscv = csr_3101_riscv,
+ csr_hpmcounter30_riscv = csr_3102_riscv,
+ csr_hpmcounter31_riscv = csr_3103_riscv,
+ csr_vl_riscv = csr_3104_riscv,
+ csr_vtype_riscv = csr_3105_riscv,
+ csr_vlenb_riscv = csr_3106_riscv,
+ csr_cycleh_riscv = csr_3200_riscv,
+ csr_timeh_riscv = csr_3201_riscv,
+ csr_instreth_riscv = csr_3202_riscv,
+ csr_hpmcounter3h_riscv = csr_3203_riscv,
+ csr_hpmcounter4h_riscv = csr_3204_riscv,
+ csr_hpmcounter5h_riscv = csr_3205_riscv,
+ csr_hpmcounter6h_riscv = csr_3206_riscv,
+ csr_hpmcounter7h_riscv = csr_3207_riscv,
+ csr_hpmcounter8h_riscv = csr_3208_riscv,
+ csr_hpmcounter9h_riscv = csr_3209_riscv,
+ csr_hpmcounter10h_riscv = csr_3210_riscv,
+ csr_hpmcounter11h_riscv = csr_3211_riscv,
+ csr_hpmcounter12h_riscv = csr_3212_riscv,
+ csr_hpmcounter13h_riscv = csr_3213_riscv,
+ csr_hpmcounter14h_riscv = csr_3214_riscv,
+ csr_hpmcounter15h_riscv = csr_3215_riscv,
+ csr_hpmcounter16h_riscv = csr_3216_riscv,
+ csr_hpmcounter17h_riscv = csr_3217_riscv,
+ csr_hpmcounter18h_riscv = csr_3218_riscv,
+ csr_hpmcounter19h_riscv = csr_3219_riscv,
+ csr_hpmcounter20h_riscv = csr_3220_riscv,
+ csr_hpmcounter21h_riscv = csr_3221_riscv,
+ csr_hpmcounter22h_riscv = csr_3222_riscv,
+ csr_hpmcounter23h_riscv = csr_3223_riscv,
+ csr_hpmcounter24h_riscv = csr_3224_riscv,
+ csr_hpmcounter25h_riscv = csr_3225_riscv,
+ csr_hpmcounter26h_riscv = csr_3226_riscv,
+ csr_hpmcounter27h_riscv = csr_3227_riscv,
+ csr_hpmcounter28h_riscv = csr_3228_riscv,
+ csr_hpmcounter29h_riscv = csr_3229_riscv,
+ csr_hpmcounter30h_riscv = csr_3230_riscv,
+ csr_hpmcounter31h_riscv = csr_3231_riscv,
+ csr_scountovf_riscv = csr_3488_riscv,
+ csr_hgeip_riscv = csr_3602_riscv,
+ csr_mvendorid_riscv = csr_3857_riscv,
+ csr_marchid_riscv = csr_3858_riscv,
+ csr_mimpid_riscv = csr_3859_riscv,
+ csr_mhartid_riscv = csr_3860_riscv,
+ csr_mconfigptr_riscv = csr_3861_riscv,
+ csr_last_riscv = csr_4095_riscv,
+
+ // Custom CSRs specified by 'Xqci' and its sub-extensions.
+ csr_qc_mmcr_riscv = csr_1984_riscv,
+ csr_qc_mnepc_riscv = csr_1985_riscv,
+ csr_qc_mncause_riscv = csr_1986_riscv,
+ csr_qc_mntvec_riscv = csr_1987_riscv,
+ csr_qc_mstktopaddr_riscv = csr_1988_riscv,
+ csr_qc_mstkbottomaddr_riscv = csr_1989_riscv,
+ csr_qc_mscratch0_riscv = csr_1990_riscv,
+ csr_qc_mscratch1_riscv = csr_1991_riscv,
+ csr_qc_mthreadptr_riscv = csr_1992_riscv,
+ csr_qc_mwpstartaddr0_riscv = csr_2000_riscv,
+ csr_qc_mwpstartaddr1_riscv = csr_2001_riscv,
+ csr_qc_mwpstartaddr2_riscv = csr_2002_riscv,
+ csr_qc_mwpstartaddr3_riscv = csr_2003_riscv,
+ csr_qc_mwpendaddr0_riscv = csr_2004_riscv,
+ csr_qc_mwpendaddr1_riscv = csr_2005_riscv,
+ csr_qc_mwpendaddr2_riscv = csr_2006_riscv,
+ csr_qc_mwpendaddr3_riscv = csr_2007_riscv,
+ csr_qc_mclicip0_riscv = csr_2032_riscv,
+ csr_qc_mclicip1_riscv = csr_2033_riscv,
+ csr_qc_mclicip2_riscv = csr_2034_riscv,
+ csr_qc_mclicip3_riscv = csr_2035_riscv,
+ csr_qc_mclicip4_riscv = csr_2036_riscv,
+ csr_qc_mclicip5_riscv = csr_2037_riscv,
+ csr_qc_mclicip6_riscv = csr_2038_riscv,
+ csr_qc_mclicip7_riscv = csr_2039_riscv,
+ csr_qc_mclicie0_riscv = csr_2040_riscv,
+ csr_qc_mclicie1_riscv = csr_2041_riscv,
+ csr_qc_mclicie2_riscv = csr_2042_riscv,
+ csr_qc_mclicie3_riscv = csr_2043_riscv,
+ csr_qc_mclicie4_riscv = csr_2044_riscv,
+ csr_qc_mclicie5_riscv = csr_2045_riscv,
+ csr_qc_mclicie6_riscv = csr_2046_riscv,
+ csr_qc_mclicie7_riscv = csr_2047_riscv,
+ csr_qc_mclicilvl0_riscv = csr_3008_riscv,
+ csr_qc_mclicilvl1_riscv = csr_3009_riscv,
+ csr_qc_mclicilvl2_riscv = csr_3010_riscv,
+ csr_qc_mclicilvl3_riscv = csr_3011_riscv,
+ csr_qc_mclicilvl4_riscv = csr_3012_riscv,
+ csr_qc_mclicilvl5_riscv = csr_3013_riscv,
+ csr_qc_mclicilvl6_riscv = csr_3014_riscv,
+ csr_qc_mclicilvl7_riscv = csr_3015_riscv,
+ csr_qc_mclicilvl8_riscv = csr_3016_riscv,
+ csr_qc_mclicilvl9_riscv = csr_3017_riscv,
+ csr_qc_mclicilvl10_riscv = csr_3018_riscv,
+ csr_qc_mclicilvl11_riscv = csr_3019_riscv,
+ csr_qc_mclicilvl12_riscv = csr_3020_riscv,
+ csr_qc_mclicilvl13_riscv = csr_3021_riscv,
+ csr_qc_mclicilvl14_riscv = csr_3022_riscv,
+ csr_qc_mclicilvl15_riscv = csr_3023_riscv,
+ csr_qc_mclicilvl16_riscv = csr_3024_riscv,
+ csr_qc_mclicilvl17_riscv = csr_3025_riscv,
+ csr_qc_mclicilvl18_riscv = csr_3026_riscv,
+ csr_qc_mclicilvl19_riscv = csr_3027_riscv,
+ csr_qc_mclicilvl20_riscv = csr_3028_riscv,
+ csr_qc_mclicilvl21_riscv = csr_3029_riscv,
+ csr_qc_mclicilvl22_riscv = csr_3030_riscv,
+ csr_qc_mclicilvl23_riscv = csr_3031_riscv,
+ csr_qc_mclicilvl24_riscv = csr_3032_riscv,
+ csr_qc_mclicilvl25_riscv = csr_3033_riscv,
+ csr_qc_mclicilvl26_riscv = csr_3034_riscv,
+ csr_qc_mclicilvl27_riscv = csr_3035_riscv,
+ csr_qc_mclicilvl28_riscv = csr_3036_riscv,
+ csr_qc_mclicilvl29_riscv = csr_3037_riscv,
+ csr_qc_mclicilvl30_riscv = csr_3038_riscv,
+ csr_qc_mclicilvl31_riscv = csr_3039_riscv,
+
+ k_num_registers_riscv
+};
+
+#endif // LLDB_SOURCE_REGISTER_ARCH_LLDB_RISCV_REGISTER_ENUMS_H
diff --git a/lldb/source/Plugins/Process/Utility/lldb-s390x-register-enums.h b/lldb/source/Register/Arch/lldb-s390x-register-enums.h
similarity index 90%
rename from lldb/source/Plugins/Process/Utility/lldb-s390x-register-enums.h
rename to lldb/source/Register/Arch/lldb-s390x-register-enums.h
index 23c441e1c8038e..4b2d09ae968e2f 100644
--- a/lldb/source/Plugins/Process/Utility/lldb-s390x-register-enums.h
+++ b/lldb/source/Register/Arch/lldb-s390x-register-enums.h
@@ -6,8 +6,8 @@
//
//===----------------------------------------------------------------------===//
-#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_LLDB_S390X_REGISTER_ENUMS_H
-#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_LLDB_S390X_REGISTER_ENUMS_H
+#ifndef LLDB_SOURCE_REGISTER_ARCH_LLDB_S390X_REGISTER_ENUMS_H
+#define LLDB_SOURCE_REGISTER_ARCH_LLDB_S390X_REGISTER_ENUMS_H
namespace lldb_private {
// LLDB register codes (e.g. RegisterKind == eRegisterKindLLDB)
@@ -87,4 +87,4 @@ enum {
};
}
-#endif // LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_LLDB_S390X_REGISTER_ENUMS_H
+#endif // LLDB_SOURCE_REGISTER_ARCH_LLDB_S390X_REGISTER_ENUMS_H
diff --git a/lldb/source/Plugins/Process/Utility/lldb-x86-register-enums.h b/lldb/source/Register/Arch/lldb-x86-register-enums.h
similarity index 98%
rename from lldb/source/Plugins/Process/Utility/lldb-x86-register-enums.h
rename to lldb/source/Register/Arch/lldb-x86-register-enums.h
index 85aa254d662123..211160184ce2b8 100644
--- a/lldb/source/Plugins/Process/Utility/lldb-x86-register-enums.h
+++ b/lldb/source/Register/Arch/lldb-x86-register-enums.h
@@ -6,8 +6,8 @@
//
//===----------------------------------------------------------------------===//
-#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_LLDB_X86_REGISTER_ENUMS_H
-#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_LLDB_X86_REGISTER_ENUMS_H
+#ifndef LLDB_SOURCE_REGISTER_ARCH_LLDB_X86_REGISTER_ENUMS_H
+#define LLDB_SOURCE_REGISTER_ARCH_LLDB_X86_REGISTER_ENUMS_H
namespace lldb_private {
// LLDB register codes (e.g. RegisterKind == eRegisterKindLLDB)
@@ -514,4 +514,4 @@ enum {
}
-#endif // LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_LLDB_X86_REGISTER_ENUMS_H
+#endif // LLDB_SOURCE_REGISTER_ARCH_LLDB_X86_REGISTER_ENUMS_H
diff --git a/lldb/source/Register/CMakeLists.txt b/lldb/source/Register/CMakeLists.txt
new file mode 100644
index 00000000000000..f3e26ab75c3824
--- /dev/null
+++ b/lldb/source/Register/CMakeLists.txt
@@ -0,0 +1,33 @@
+add_lldb_library(lldbRegister NO_PLUGIN_DEPENDENCIES
+ Arch/RegisterContext_x86.cpp
+ Arch/RegisterInfos_x86_64_with_base_shared.cpp
+ Common/RegisterInfoCommonDynamic_riscv32.cpp
+ Common/RegisterInfoCommon_arm.cpp
+ Common/RegisterInfoCommon_arm64.cpp
+ Common/RegisterInfoCommon_loongarch64.cpp
+ Common/RegisterInfoCommon_ppc64.cpp
+ Common/RegisterInfoCommon_ppc64le.cpp
+ Common/RegisterInfoCommon_riscv32.cpp
+ Common/RegisterInfoCommon_riscv64.cpp
+ Common/RegisterTypeDetector_arm64.cpp
+ FreeBSD/RegisterInfoFreeBSD_i386.cpp
+ FreeBSD/RegisterInfoFreeBSD_powerpc.cpp
+ FreeBSD/RegisterInfoFreeBSD_x86_64.cpp
+ Linux/RegisterInfoLinux_i386.cpp
+ Linux/RegisterInfoLinux_s390x.cpp
+ Linux/RegisterInfoLinux_x86_64.cpp
+ NetBSD/RegisterInfoNetBSD_i386.cpp
+ NetBSD/RegisterInfoNetBSD_x86_64.cpp
+ OpenBSD/RegisterInfoOpenBSD_i386.cpp
+ OpenBSD/RegisterInfoOpenBSD_x86_64.cpp
+ Windows/RegisterInfoWindows_i386.cpp
+ Windows/RegisterInfoWindows_x86_64.cpp
+
+ LINK_COMPONENTS
+ Support
+ TargetParser
+ LINK_LIBS
+ lldbUtility
+ ALLOWED_INTERNAL_DEPENDENCIES
+ lldbUtility
+ )
diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfoCommonDynamic_riscv32.cpp b/lldb/source/Register/Common/RegisterInfoCommonDynamic_riscv32.cpp
similarity index 97%
rename from lldb/source/Plugins/Process/Utility/RegisterInfoCommonDynamic_riscv32.cpp
rename to lldb/source/Register/Common/RegisterInfoCommonDynamic_riscv32.cpp
index 0fc22c04d26db8..1c5fbd39f4b7f3 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterInfoCommonDynamic_riscv32.cpp
+++ b/lldb/source/Register/Common/RegisterInfoCommonDynamic_riscv32.cpp
@@ -6,9 +6,9 @@
//
//===----------------------------------------------------------------------===//
-#include "RegisterInfoCommonDynamic_riscv32.h"
+#include "Register/Common/RegisterInfoCommonDynamic_riscv32.h"
-#include "lldb-riscv-register-enums.h"
+#include "Register/Arch/lldb-riscv-register-enums.h"
#include "lldb/lldb-defines.h"
#include "llvm/ADT/StringMap.h"
#include "llvm/Support/Compiler.h"
@@ -19,7 +19,7 @@
#define FPR_OFFSET(idx) ((idx) * sizeof(uint32_t))
#define DECLARE_REGISTER_INFOS_RISCV32_STRUCT
-#include "Plugins/Process/Utility/RegisterInfos_riscv32.h"
+#include "Register/Arch/RegisterInfos_riscv32.h"
#undef DECLARE_REGISTER_INFOS_RISCV32_STRUCT
RegisterInfoCommonDynamic_riscv32::RegisterInfoCommonDynamic_riscv32(
diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfoCommonDynamic_riscv32.h b/lldb/source/Register/Common/RegisterInfoCommonDynamic_riscv32.h
similarity index 89%
rename from lldb/source/Plugins/Process/Utility/RegisterInfoCommonDynamic_riscv32.h
rename to lldb/source/Register/Common/RegisterInfoCommonDynamic_riscv32.h
index c02662de68dd2c..7707d8588cdfac 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterInfoCommonDynamic_riscv32.h
+++ b/lldb/source/Register/Common/RegisterInfoCommonDynamic_riscv32.h
@@ -6,10 +6,10 @@
//
//===----------------------------------------------------------------------===//
-#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOCOMMONDYNAMIC_RISCV32_H
-#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOCOMMONDYNAMIC_RISCV32_H
+#ifndef LLDB_SOURCE_REGISTER_COMMON_REGISTERINFOCOMMONDYNAMIC_RISCV32_H
+#define LLDB_SOURCE_REGISTER_COMMON_REGISTERINFOCOMMONDYNAMIC_RISCV32_H
-#include "RegisterInfoAndSetInterface.h"
+#include "Register/RegisterInfoAndSetInterface.h"
#include "lldb/Target/DynamicRegisterInfo.h"
#include "lldb/Target/RegisterContext.h"
#include "lldb/lldb-private.h"
@@ -67,4 +67,4 @@ class RegisterInfoCommonDynamic_riscv32
llvm::SmallVectorImpl<lldb_private::RegisterInfo> &cs_reg_infos);
};
-#endif // LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOCOMMONDYNAMIC_RISCV32_H
+#endif // LLDB_SOURCE_REGISTER_COMMON_REGISTERINFOCOMMONDYNAMIC_RISCV32_H
diff --git a/lldb/source/Register/Common/RegisterInfoCommon_arm.cpp b/lldb/source/Register/Common/RegisterInfoCommon_arm.cpp
new file mode 100644
index 00000000000000..3963362e025223
--- /dev/null
+++ b/lldb/source/Register/Common/RegisterInfoCommon_arm.cpp
@@ -0,0 +1,211 @@
+//===-- RegisterInfoCommon_arm.cpp -----------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===---------------------------------------------------------------------===//
+
+#include <cassert>
+#include <cstddef>
+#include <vector>
+
+#include "lldb/lldb-defines.h"
+#include "llvm/Support/Compiler.h"
+
+#include "Register/Common/RegisterInfoCommon_arm.h"
+
+using namespace lldb;
+using namespace lldb_private;
+
+// Based on RegisterContextDarwin_arm.cpp
+#define GPR_OFFSET(idx) ((idx)*4)
+#define FPU_OFFSET(idx) ((idx)*4 + sizeof(RegisterInfoCommon_arm::GPR))
+#define FPSCR_OFFSET \
+ (LLVM_EXTENSION offsetof(RegisterInfoCommon_arm::FPU, fpscr) + \
+ sizeof(RegisterInfoCommon_arm::GPR))
+#define TLS_OFFSET \
+ (sizeof(RegisterInfoCommon_arm::GPR) + sizeof(RegisterInfoCommon_arm::FPU))
+#define EXC_OFFSET(idx) \
+ ((idx) * 4 + sizeof(RegisterInfoCommon_arm::GPR) + \
+ sizeof(RegisterInfoCommon_arm::FPU) + sizeof(RegisterInfoCommon_arm::TLS))
+#define DBG_OFFSET(reg) \
+ ((LLVM_EXTENSION offsetof(RegisterInfoCommon_arm::DBG, reg) + \
+ sizeof(RegisterInfoCommon_arm::GPR) + sizeof(RegisterInfoCommon_arm::FPU) + \
+ sizeof(RegisterInfoCommon_arm::TLS) + sizeof(RegisterInfoCommon_arm::EXC)))
+
+#define DEFINE_DBG(reg, i) \
+ #reg, NULL, sizeof(((RegisterInfoCommon_arm::DBG *) NULL)->reg[i]), \
+ DBG_OFFSET(reg[i]), eEncodingUint, eFormatHex, \
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \
+ LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \
+ dbg_##reg##i }, \
+ NULL, NULL, NULL,
+#define REG_CONTEXT_SIZE \
+ (sizeof(RegisterInfoCommon_arm::GPR) + sizeof(RegisterInfoCommon_arm::FPU) + \
+ sizeof(RegisterInfoCommon_arm::EXC))
+
+// Include RegisterInfos_arm to declare our g_register_infos_arm structure.
+#define DECLARE_REGISTER_INFOS_ARM_STRUCT
+#include "Register/Arch/RegisterInfos_arm.h"
+#undef DECLARE_REGISTER_INFOS_ARM_STRUCT
+
+static const lldb_private::RegisterInfo *
+GetRegisterInfoPtr(const lldb_private::ArchSpec &target_arch) {
+ switch (target_arch.GetMachine()) {
+ case llvm::Triple::arm:
+ return g_register_infos_arm;
+ default:
+ assert(false && "Unhandled target architecture.");
+ return nullptr;
+ }
+}
+
+static uint32_t
+GetRegisterInfoCount(const lldb_private::ArchSpec &target_arch) {
+ switch (target_arch.GetMachine()) {
+ case llvm::Triple::arm:
+ return static_cast<uint32_t>(sizeof(g_register_infos_arm) /
+ sizeof(g_register_infos_arm[0]));
+ default:
+ assert(false && "Unhandled target architecture.");
+ return 0;
+ }
+}
+
+// Number of register sets provided by this context.
+enum {
+ k_num_gpr_registers = gpr_cpsr - gpr_r0 + 1,
+ k_num_fpr_registers = fpu_q15 - fpu_s0 + 1,
+ k_num_tls_registers = 1,
+ k_num_register_sets_without_tls = 2,
+ k_num_register_sets_with_tls = 3
+};
+
+// arm general purpose registers.
+static const uint32_t g_gpr_regnums_arm[] = {
+ gpr_r0, gpr_r1,
+ gpr_r2, gpr_r3,
+ gpr_r4, gpr_r5,
+ gpr_r6, gpr_r7,
+ gpr_r8, gpr_r9,
+ gpr_r10, gpr_r11,
+ gpr_r12, gpr_sp,
+ gpr_lr, gpr_pc,
+ gpr_cpsr, LLDB_INVALID_REGNUM // register sets need to end with this flag
+};
+static_assert(((sizeof g_gpr_regnums_arm / sizeof g_gpr_regnums_arm[0]) - 1) ==
+ k_num_gpr_registers,
+ "g_gpr_regnums_arm has wrong number of register infos");
+
+// arm floating point registers.
+static const uint32_t g_fpu_regnums_arm[] = {
+ fpu_s0, fpu_s1,
+ fpu_s2, fpu_s3,
+ fpu_s4, fpu_s5,
+ fpu_s6, fpu_s7,
+ fpu_s8, fpu_s9,
+ fpu_s10, fpu_s11,
+ fpu_s12, fpu_s13,
+ fpu_s14, fpu_s15,
+ fpu_s16, fpu_s17,
+ fpu_s18, fpu_s19,
+ fpu_s20, fpu_s21,
+ fpu_s22, fpu_s23,
+ fpu_s24, fpu_s25,
+ fpu_s26, fpu_s27,
+ fpu_s28, fpu_s29,
+ fpu_s30, fpu_s31,
+ fpu_fpscr, fpu_d0,
+ fpu_d1, fpu_d2,
+ fpu_d3, fpu_d4,
+ fpu_d5, fpu_d6,
+ fpu_d7, fpu_d8,
+ fpu_d9, fpu_d10,
+ fpu_d11, fpu_d12,
+ fpu_d13, fpu_d14,
+ fpu_d15, fpu_d16,
+ fpu_d17, fpu_d18,
+ fpu_d19, fpu_d20,
+ fpu_d21, fpu_d22,
+ fpu_d23, fpu_d24,
+ fpu_d25, fpu_d26,
+ fpu_d27, fpu_d28,
+ fpu_d29, fpu_d30,
+ fpu_d31, fpu_q0,
+ fpu_q1, fpu_q2,
+ fpu_q3, fpu_q4,
+ fpu_q5, fpu_q6,
+ fpu_q7, fpu_q8,
+ fpu_q9, fpu_q10,
+ fpu_q11, fpu_q12,
+ fpu_q13, fpu_q14,
+ fpu_q15, LLDB_INVALID_REGNUM // register sets need to end with this flag
+};
+static_assert(((sizeof g_fpu_regnums_arm / sizeof g_fpu_regnums_arm[0]) - 1) ==
+ k_num_fpr_registers,
+ "g_fpu_regnums_arm has wrong number of register infos");
+
+// arm thread local storage registers.
+static const uint32_t g_tls_regnums_arm[] = {
+ tls_tpidruro,
+ LLDB_INVALID_REGNUM // register sets need to end with this flag
+};
+static_assert(((sizeof g_tls_regnums_arm / sizeof g_tls_regnums_arm[0]) - 1) ==
+ k_num_tls_registers,
+ "g_tls_regnums_arm has wrong number of register infos");
+
+// Register sets for arm.
+static const RegisterSet g_reg_sets_arm[k_num_register_sets_with_tls] = {
+ {"General Purpose Registers", "gpr", k_num_gpr_registers,
+ g_gpr_regnums_arm},
+ {"Floating Point Registers", "fpu", k_num_fpr_registers, g_fpu_regnums_arm},
+ {"Thread Local Storage Registers", "tls", k_num_tls_registers,
+ g_tls_regnums_arm}};
+
+RegisterInfoCommon_arm::RegisterInfoCommon_arm(
+ const lldb_private::ArchSpec &target_arch, bool has_tls_reg)
+ : lldb_private::RegisterInfoAndSetInterface(target_arch),
+ m_register_info_p(GetRegisterInfoPtr(target_arch)),
+ m_register_info_count(GetRegisterInfoCount(target_arch)),
+ m_has_tls_reg(has_tls_reg) {}
+
+size_t RegisterInfoCommon_arm::GetGPRSize() const {
+ return sizeof(struct RegisterInfoCommon_arm::GPR);
+}
+
+size_t RegisterInfoCommon_arm::GetFPRSize() const {
+ return sizeof(struct RegisterInfoCommon_arm::FPU);
+}
+
+const lldb_private::RegisterInfo *
+RegisterInfoCommon_arm::GetRegisterInfo() const {
+ return m_register_info_p;
+}
+
+size_t RegisterInfoCommon_arm::GetRegisterSetCount() const {
+ return m_has_tls_reg ? k_num_register_sets_with_tls
+ : k_num_register_sets_without_tls;
+}
+
+size_t RegisterInfoCommon_arm::GetRegisterSetFromRegisterIndex(
+ uint32_t reg_index) const {
+ if (reg_index <= gpr_cpsr)
+ return GPRegSet;
+ if (reg_index <= fpu_q15)
+ return FPRegSet;
+ if (reg_index == tls_tpidruro && m_has_tls_reg)
+ return TLSRegSet;
+ return LLDB_INVALID_REGNUM;
+}
+
+const lldb_private::RegisterSet *
+RegisterInfoCommon_arm::GetRegisterSet(size_t set_index) const {
+ if (set_index < GetRegisterSetCount())
+ return &g_reg_sets_arm[set_index];
+ return nullptr;
+}
+
+uint32_t RegisterInfoCommon_arm::GetRegisterCount() const {
+ return m_register_info_count;
+}
diff --git a/lldb/source/Register/Common/RegisterInfoCommon_arm.h b/lldb/source/Register/Common/RegisterInfoCommon_arm.h
new file mode 100644
index 00000000000000..edeec29834bbf2
--- /dev/null
+++ b/lldb/source/Register/Common/RegisterInfoCommon_arm.h
@@ -0,0 +1,80 @@
+//===-- RegisterInfoCommon_arm.h ---------------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLDB_SOURCE_REGISTER_COMMON_REGISTERINFOCOMMON_ARM_H
+#define LLDB_SOURCE_REGISTER_COMMON_REGISTERINFOCOMMON_ARM_H
+
+#include "Register/RegisterInfoAndSetInterface.h"
+#include "lldb/Target/RegisterContext.h"
+#include "lldb/lldb-private.h"
+
+class RegisterInfoCommon_arm : public lldb_private::RegisterInfoAndSetInterface {
+public:
+ enum { GPRegSet = 0, FPRegSet, TLSRegSet };
+
+ struct GPR {
+ uint32_t r[16]; // R0-R15
+ uint32_t cpsr; // CPSR
+ };
+
+ struct QReg {
+ uint8_t bytes[16];
+ };
+
+ struct FPU {
+ union {
+ uint32_t s[32];
+ uint64_t d[32];
+ QReg q[16]; // the 128-bit NEON registers
+ } floats;
+ uint32_t fpscr;
+ };
+ struct EXC {
+ uint32_t exception;
+ uint32_t fsr; /* Fault status */
+ uint32_t far; /* Virtual Fault Address */
+ };
+
+ struct TLS {
+ uint32_t tpidruro;
+ };
+
+ struct DBG {
+ uint32_t bvr[16];
+ uint32_t bcr[16];
+ uint32_t wvr[16];
+ uint32_t wcr[16];
+ };
+
+ RegisterInfoCommon_arm(const lldb_private::ArchSpec &target_arch,
+ bool has_tls_reg = false);
+
+ size_t GetGPRSize() const override;
+
+ size_t GetFPRSize() const override;
+
+ const lldb_private::RegisterInfo *GetRegisterInfo() const override;
+
+ uint32_t GetRegisterCount() const override;
+
+ const lldb_private::RegisterSet *
+ GetRegisterSet(size_t reg_set) const override;
+
+ size_t GetRegisterSetCount() const override;
+
+ size_t GetRegisterSetFromRegisterIndex(uint32_t reg_index) const override;
+
+private:
+ const lldb_private::RegisterInfo *m_register_info_p;
+ uint32_t m_register_info_count;
+ // Only provide information about the TLS register to users of this class that
+ // can handle it. Currently, only `NativeRegisterContextLinux_arm` reads it.
+ bool m_has_tls_reg;
+};
+
+#endif // LLDB_SOURCE_REGISTER_COMMON_REGISTERINFOCOMMON_ARM_H
diff --git a/lldb/source/Register/Common/RegisterInfoCommon_arm64.cpp b/lldb/source/Register/Common/RegisterInfoCommon_arm64.cpp
new file mode 100644
index 00000000000000..7a99329654594a
--- /dev/null
+++ b/lldb/source/Register/Common/RegisterInfoCommon_arm64.cpp
@@ -0,0 +1,681 @@
+//===-- RegisterInfoCommon_arm64.cpp ---------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===---------------------------------------------------------------------===//
+
+#include <cassert>
+#include <cstddef>
+#include <vector>
+
+#include "lldb/lldb-defines.h"
+#include "llvm/Support/Compiler.h"
+
+#include "Register/Common/RegisterInfoCommon_arm64.h"
+
+// Based on RegisterContextDarwin_arm64.cpp
+#define GPR_OFFSET(idx) ((idx)*8)
+#define GPR_OFFSET_NAME(reg) \
+ (LLVM_EXTENSION offsetof(RegisterInfoCommon_arm64::GPR, reg))
+
+#define FPU_OFFSET(idx) ((idx)*16 + sizeof(RegisterInfoCommon_arm64::GPR))
+#define FPU_OFFSET_NAME(reg) \
+ (LLVM_EXTENSION offsetof(RegisterInfoCommon_arm64::FPU, reg) + \
+ sizeof(RegisterInfoCommon_arm64::GPR))
+
+// This information is based on AArch64 with SVE architecture reference manual.
+// AArch64 with SVE has 32 Z and 16 P vector registers. There is also an FFR
+// (First Fault) register and a VG (Vector Granule) pseudo register.
+
+// SVE 16-byte quad word is the basic unit of expansion in vector length.
+#define SVE_QUAD_WORD_BYTES 16
+
+// Vector length is the multiplier which decides the no of quad words,
+// (multiples of 128-bits or 16-bytes) present in a Z register. Vector length
+// is decided during execution and can change at runtime. SVE AArch64 register
+// infos have modes one for each valid value of vector length. A change in
+// vector length requires register context to update sizes of SVE Z, P and FFR.
+// Also register context needs to update byte offsets of all registers affected
+// by the change in vector length.
+#define SVE_REGS_DEFAULT_OFFSET_LINUX sizeof(RegisterInfoCommon_arm64::GPR)
+
+#define SVE_OFFSET_VG SVE_REGS_DEFAULT_OFFSET_LINUX
+
+#define EXC_OFFSET_NAME(reg) \
+ (LLVM_EXTENSION offsetof(RegisterInfoCommon_arm64::EXC, reg) + \
+ sizeof(RegisterInfoCommon_arm64::GPR) + \
+ sizeof(RegisterInfoCommon_arm64::FPU))
+#define DBG_OFFSET_NAME(reg) \
+ (LLVM_EXTENSION offsetof(RegisterInfoCommon_arm64::DBG, reg) + \
+ sizeof(RegisterInfoCommon_arm64::GPR) + \
+ sizeof(RegisterInfoCommon_arm64::FPU) + \
+ sizeof(RegisterInfoCommon_arm64::EXC))
+
+#define DEFINE_DBG(reg, i) \
+ #reg, NULL, \
+ sizeof(((RegisterInfoCommon_arm64::DBG *) NULL)->reg[i]), \
+ DBG_OFFSET_NAME(reg[i]), lldb::eEncodingUint, lldb::eFormatHex, \
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \
+ LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \
+ dbg_##reg##i }, \
+ NULL, NULL, NULL,
+#define REG_CONTEXT_SIZE \
+ (sizeof(RegisterInfoCommon_arm64::GPR) + \
+ sizeof(RegisterInfoCommon_arm64::FPU) + \
+ sizeof(RegisterInfoCommon_arm64::EXC))
+
+// Include RegisterInfos_arm64 to declare our g_register_infos_arm64 structure.
+#define DECLARE_REGISTER_INFOS_ARM64_STRUCT
+#include "Register/Arch/RegisterInfos_arm64.h"
+#include "Register/Arch/RegisterInfos_arm64_sve.h"
+#undef DECLARE_REGISTER_INFOS_ARM64_STRUCT
+
+static lldb_private::RegisterInfo g_register_infos_pauth[] = {
+ DEFINE_EXTENSION_REG(data_mask), DEFINE_EXTENSION_REG(code_mask)};
+
+static lldb_private::RegisterInfo g_register_infos_mte[] = {
+ DEFINE_EXTENSION_REG(mte_ctrl)};
+
+static lldb_private::RegisterInfo g_register_infos_tls[] = {
+ DEFINE_EXTENSION_REG_GENERIC(tpidr, LLDB_REGNUM_GENERIC_TP),
+ // Only present when SME is present
+ DEFINE_EXTENSION_REG(tpidr2)};
+
+static lldb_private::RegisterInfo g_register_infos_sme[] = {
+ DEFINE_EXTENSION_REG(svcr),
+ DEFINE_EXTENSION_REG(svg),
+ // 16 is a default size we will change later.
+ {"za", nullptr, 16, 0, lldb::eEncodingVector, lldb::eFormatVectorOfUInt8,
+ KIND_ALL_INVALID, nullptr, nullptr, nullptr}};
+
+static lldb_private::RegisterInfo g_register_infos_sme2[] = {
+ {"zt0", nullptr, 64, 0, lldb::eEncodingVector, lldb::eFormatVectorOfUInt8,
+ KIND_ALL_INVALID, nullptr, nullptr, nullptr}};
+
+static lldb_private::RegisterInfo g_register_infos_fpmr[] = {
+ DEFINE_EXTENSION_REG(fpmr)};
+
+static lldb_private::RegisterInfo g_register_infos_gcs[] = {
+ DEFINE_EXTENSION_REG(gcs_features_enabled),
+ DEFINE_EXTENSION_REG(gcs_features_locked), DEFINE_EXTENSION_REG(gcspr_el0)};
+
+static lldb_private::RegisterInfo g_register_infos_poe[] = {
+ DEFINE_EXTENSION_REG(por_el0)};
+
+// Number of register sets provided by this context.
+enum {
+ k_num_gpr_registers = gpr_w28 - gpr_x0 + 1,
+ k_num_fpr_registers = fpu_fpcr - fpu_v0 + 1,
+ k_num_sve_registers = sve_ffr - sve_vg + 1,
+ k_num_mte_register = 1,
+ // Number of TLS registers is dynamic so it is not listed here.
+ k_num_pauth_register = 2,
+ // SME2's ZT0 will also be added to this set if present. So this number is
+ // only for SME1 registers.
+ k_num_sme_register = 3,
+ k_num_fpmr_register = 1,
+ k_num_gcs_register = 3,
+ k_num_poe_register = 1,
+ k_num_register_sets_default = 2,
+ k_num_register_sets = 3
+};
+
+// ARM64 general purpose registers.
+static const uint32_t g_gpr_regnums_arm64[] = {
+ gpr_x0, gpr_x1, gpr_x2, gpr_x3,
+ gpr_x4, gpr_x5, gpr_x6, gpr_x7,
+ gpr_x8, gpr_x9, gpr_x10, gpr_x11,
+ gpr_x12, gpr_x13, gpr_x14, gpr_x15,
+ gpr_x16, gpr_x17, gpr_x18, gpr_x19,
+ gpr_x20, gpr_x21, gpr_x22, gpr_x23,
+ gpr_x24, gpr_x25, gpr_x26, gpr_x27,
+ gpr_x28, gpr_fp, gpr_lr, gpr_sp,
+ gpr_pc, gpr_cpsr, gpr_w0, gpr_w1,
+ gpr_w2, gpr_w3, gpr_w4, gpr_w5,
+ gpr_w6, gpr_w7, gpr_w8, gpr_w9,
+ gpr_w10, gpr_w11, gpr_w12, gpr_w13,
+ gpr_w14, gpr_w15, gpr_w16, gpr_w17,
+ gpr_w18, gpr_w19, gpr_w20, gpr_w21,
+ gpr_w22, gpr_w23, gpr_w24, gpr_w25,
+ gpr_w26, gpr_w27, gpr_w28, LLDB_INVALID_REGNUM};
+
+static_assert(((sizeof g_gpr_regnums_arm64 / sizeof g_gpr_regnums_arm64[0]) -
+ 1) == k_num_gpr_registers,
+ "g_gpr_regnums_arm64 has wrong number of register infos");
+
+// ARM64 floating point registers.
+static const uint32_t g_fpu_regnums_arm64[] = {
+ fpu_v0, fpu_v1, fpu_v2,
+ fpu_v3, fpu_v4, fpu_v5,
+ fpu_v6, fpu_v7, fpu_v8,
+ fpu_v9, fpu_v10, fpu_v11,
+ fpu_v12, fpu_v13, fpu_v14,
+ fpu_v15, fpu_v16, fpu_v17,
+ fpu_v18, fpu_v19, fpu_v20,
+ fpu_v21, fpu_v22, fpu_v23,
+ fpu_v24, fpu_v25, fpu_v26,
+ fpu_v27, fpu_v28, fpu_v29,
+ fpu_v30, fpu_v31, fpu_s0,
+ fpu_s1, fpu_s2, fpu_s3,
+ fpu_s4, fpu_s5, fpu_s6,
+ fpu_s7, fpu_s8, fpu_s9,
+ fpu_s10, fpu_s11, fpu_s12,
+ fpu_s13, fpu_s14, fpu_s15,
+ fpu_s16, fpu_s17, fpu_s18,
+ fpu_s19, fpu_s20, fpu_s21,
+ fpu_s22, fpu_s23, fpu_s24,
+ fpu_s25, fpu_s26, fpu_s27,
+ fpu_s28, fpu_s29, fpu_s30,
+ fpu_s31, fpu_d0, fpu_d1,
+ fpu_d2, fpu_d3, fpu_d4,
+ fpu_d5, fpu_d6, fpu_d7,
+ fpu_d8, fpu_d9, fpu_d10,
+ fpu_d11, fpu_d12, fpu_d13,
+ fpu_d14, fpu_d15, fpu_d16,
+ fpu_d17, fpu_d18, fpu_d19,
+ fpu_d20, fpu_d21, fpu_d22,
+ fpu_d23, fpu_d24, fpu_d25,
+ fpu_d26, fpu_d27, fpu_d28,
+ fpu_d29, fpu_d30, fpu_d31,
+ fpu_fpsr, fpu_fpcr, LLDB_INVALID_REGNUM};
+static_assert(((sizeof g_fpu_regnums_arm64 / sizeof g_fpu_regnums_arm64[0]) -
+ 1) == k_num_fpr_registers,
+ "g_fpu_regnums_arm64 has wrong number of register infos");
+
+// ARM64 SVE registers.
+static const uint32_t g_sve_regnums_arm64[] = {
+ sve_vg, sve_z0, sve_z1,
+ sve_z2, sve_z3, sve_z4,
+ sve_z5, sve_z6, sve_z7,
+ sve_z8, sve_z9, sve_z10,
+ sve_z11, sve_z12, sve_z13,
+ sve_z14, sve_z15, sve_z16,
+ sve_z17, sve_z18, sve_z19,
+ sve_z20, sve_z21, sve_z22,
+ sve_z23, sve_z24, sve_z25,
+ sve_z26, sve_z27, sve_z28,
+ sve_z29, sve_z30, sve_z31,
+ sve_p0, sve_p1, sve_p2,
+ sve_p3, sve_p4, sve_p5,
+ sve_p6, sve_p7, sve_p8,
+ sve_p9, sve_p10, sve_p11,
+ sve_p12, sve_p13, sve_p14,
+ sve_p15, sve_ffr, LLDB_INVALID_REGNUM};
+static_assert(((sizeof g_sve_regnums_arm64 / sizeof g_sve_regnums_arm64[0]) -
+ 1) == k_num_sve_registers,
+ "g_sve_regnums_arm64 has wrong number of register infos");
+
+// Register sets for ARM64.
+static const lldb_private::RegisterSet g_reg_sets_arm64[k_num_register_sets] = {
+ {"General Purpose Registers", "gpr", k_num_gpr_registers,
+ g_gpr_regnums_arm64},
+ {"Floating Point Registers", "fpu", k_num_fpr_registers,
+ g_fpu_regnums_arm64},
+ {"Scalable Vector Extension Registers", "sve", k_num_sve_registers,
+ g_sve_regnums_arm64}};
+
+static const lldb_private::RegisterSet g_reg_set_pauth_arm64 = {
+ "Pointer Authentication Registers", "pauth", k_num_pauth_register, nullptr};
+
+static const lldb_private::RegisterSet g_reg_set_mte_arm64 = {
+ "MTE Control Register", "mte", k_num_mte_register, nullptr};
+
+// The size of the TLS set is dynamic, so not listed here.
+
+static const lldb_private::RegisterSet g_reg_set_sme_arm64 = {
+ "Scalable Matrix Extension Registers", "sme", k_num_sme_register, nullptr};
+
+static const lldb_private::RegisterSet g_reg_set_fpmr_arm64 = {
+ "Floating Point Mode Register", "fpmr", k_num_fpmr_register, nullptr};
+
+static const lldb_private::RegisterSet g_reg_set_gcs_arm64 = {
+ "Guarded Control Stack Registers", "gcs", k_num_gcs_register, nullptr};
+
+static const lldb_private::RegisterSet g_reg_set_poe_arm64 = {
+ "Permission Overlay Registers", "poe", k_num_poe_register, nullptr};
+
+RegisterInfoCommon_arm64::RegisterInfoCommon_arm64(
+ const lldb_private::ArchSpec &target_arch, lldb_private::Flags opt_regsets)
+ : lldb_private::RegisterInfoAndSetInterface(target_arch),
+ m_opt_regsets(opt_regsets) {
+ switch (target_arch.GetMachine()) {
+ case llvm::Triple::aarch64:
+ case llvm::Triple::aarch64_32: {
+ m_register_set_p = g_reg_sets_arm64;
+ m_register_set_count = k_num_register_sets_default;
+ m_per_regset_regnum_range[GPRegSet] = std::make_pair(gpr_x0, gpr_w28 + 1);
+ m_per_regset_regnum_range[FPRegSet] = std::make_pair(fpu_v0, fpu_fpcr + 1);
+
+ // Now configure register sets supported by current target. If we have a
+ // dynamic register set like MTE, Pointer Authentication regset then we need
+ // to create dynamic register infos and regset array. Push back all optional
+ // register infos and regset and calculate register offsets accordingly.
+ if (m_opt_regsets.AnySet(eRegsetMaskSVE | eRegsetMaskSSVE)) {
+ m_register_info_p = g_register_infos_arm64_sve_le;
+ m_register_info_count = sve_ffr + 1;
+ m_per_regset_regnum_range[m_register_set_count++] =
+ std::make_pair(sve_vg, sve_ffr + 1);
+ } else {
+ m_register_info_p = g_register_infos_arm64_le;
+ m_register_info_count = fpu_fpcr + 1;
+ }
+
+ if (m_opt_regsets.AnySet(eRegsetMaskDynamic)) {
+ llvm::ArrayRef<lldb_private::RegisterInfo> reg_infos_ref =
+ llvm::ArrayRef(m_register_info_p, m_register_info_count);
+ llvm::ArrayRef<lldb_private::RegisterSet> reg_sets_ref =
+ llvm::ArrayRef(m_register_set_p, m_register_set_count);
+ llvm::copy(reg_infos_ref, std::back_inserter(m_dynamic_reg_infos));
+ llvm::copy(reg_sets_ref, std::back_inserter(m_dynamic_reg_sets));
+
+ if (m_opt_regsets.AllSet(eRegsetMaskPAuth))
+ AddRegSetPAuth();
+
+ if (m_opt_regsets.AllSet(eRegsetMaskMTE))
+ AddRegSetMTE();
+
+ if (m_opt_regsets.AllSet(eRegsetMaskTLS)) {
+ // The TLS set always contains tpidr but only has tpidr2 when SME is
+ // present.
+ AddRegSetTLS(m_opt_regsets.AllSet(eRegsetMaskSSVE));
+ }
+
+ if (m_opt_regsets.AnySet(eRegsetMaskSSVE))
+ AddRegSetSME(m_opt_regsets.AnySet(eRegsetMaskZT));
+
+ if (m_opt_regsets.AllSet(eRegsetMaskFPMR))
+ AddRegSetFPMR();
+
+ if (m_opt_regsets.AllSet(eRegsetMaskGCS))
+ AddRegSetGCS();
+
+ if (m_opt_regsets.AllSet(eRegsetMaskPOE))
+ AddRegSetPOE();
+
+ m_register_info_count = m_dynamic_reg_infos.size();
+ m_register_info_p = m_dynamic_reg_infos.data();
+ m_register_set_p = m_dynamic_reg_sets.data();
+ m_register_set_count = m_dynamic_reg_sets.size();
+ }
+ break;
+ }
+ default:
+ assert(false && "Unhandled target architecture.");
+ }
+}
+
+uint32_t RegisterInfoCommon_arm64::GetRegisterCount() const {
+ return m_register_info_count;
+}
+
+size_t RegisterInfoCommon_arm64::GetGPRSizeStatic() {
+ return sizeof(struct RegisterInfoCommon_arm64::GPR);
+}
+
+size_t RegisterInfoCommon_arm64::GetFPRSize() const {
+ return sizeof(struct RegisterInfoCommon_arm64::FPU);
+}
+
+const lldb_private::RegisterInfo *
+RegisterInfoCommon_arm64::GetRegisterInfo() const {
+ return m_register_info_p;
+}
+
+size_t RegisterInfoCommon_arm64::GetRegisterSetCount() const {
+ return m_register_set_count;
+}
+
+size_t RegisterInfoCommon_arm64::GetRegisterSetFromRegisterIndex(
+ uint32_t reg_index) const {
+ for (const auto ®set_range : m_per_regset_regnum_range) {
+ if (reg_index >= regset_range.second.first &&
+ reg_index < regset_range.second.second)
+ return regset_range.first;
+ }
+ return LLDB_INVALID_REGNUM;
+}
+
+const lldb_private::RegisterSet *
+RegisterInfoCommon_arm64::GetRegisterSet(size_t set_index) const {
+ if (set_index < GetRegisterSetCount())
+ return &m_register_set_p[set_index];
+ return nullptr;
+}
+
+void RegisterInfoCommon_arm64::AddRegSetPAuth() {
+ uint32_t pa_regnum = m_dynamic_reg_infos.size();
+ for (uint32_t i = 0; i < k_num_pauth_register; i++) {
+ pauth_regnum_collection.push_back(pa_regnum + i);
+ m_dynamic_reg_infos.push_back(g_register_infos_pauth[i]);
+ m_dynamic_reg_infos[pa_regnum + i].byte_offset =
+ m_dynamic_reg_infos[pa_regnum + i - 1].byte_offset +
+ m_dynamic_reg_infos[pa_regnum + i - 1].byte_size;
+ m_dynamic_reg_infos[pa_regnum + i].kinds[lldb::eRegisterKindLLDB] =
+ pa_regnum + i;
+ }
+
+ m_per_regset_regnum_range[m_register_set_count] =
+ std::make_pair(pa_regnum, m_dynamic_reg_infos.size());
+ m_dynamic_reg_sets.push_back(g_reg_set_pauth_arm64);
+ m_dynamic_reg_sets.back().registers = pauth_regnum_collection.data();
+}
+
+void RegisterInfoCommon_arm64::AddRegSetMTE() {
+ uint32_t mte_regnum = m_dynamic_reg_infos.size();
+ m_mte_regnum_collection.push_back(mte_regnum);
+ m_dynamic_reg_infos.push_back(g_register_infos_mte[0]);
+ m_dynamic_reg_infos[mte_regnum].byte_offset =
+ m_dynamic_reg_infos[mte_regnum - 1].byte_offset +
+ m_dynamic_reg_infos[mte_regnum - 1].byte_size;
+ m_dynamic_reg_infos[mte_regnum].kinds[lldb::eRegisterKindLLDB] = mte_regnum;
+
+ m_per_regset_regnum_range[m_register_set_count] =
+ std::make_pair(mte_regnum, mte_regnum + 1);
+ m_dynamic_reg_sets.push_back(g_reg_set_mte_arm64);
+ m_dynamic_reg_sets.back().registers = m_mte_regnum_collection.data();
+}
+
+void RegisterInfoCommon_arm64::AddRegSetTLS(bool has_tpidr2) {
+ uint32_t tls_regnum = m_dynamic_reg_infos.size();
+ uint32_t num_regs = has_tpidr2 ? 2 : 1;
+ for (uint32_t i = 0; i < num_regs; i++) {
+ m_tls_regnum_collection.push_back(tls_regnum + i);
+ m_dynamic_reg_infos.push_back(g_register_infos_tls[i]);
+ m_dynamic_reg_infos[tls_regnum + i].byte_offset =
+ m_dynamic_reg_infos[tls_regnum + i - 1].byte_offset +
+ m_dynamic_reg_infos[tls_regnum + i - 1].byte_size;
+ m_dynamic_reg_infos[tls_regnum + i].kinds[lldb::eRegisterKindLLDB] =
+ tls_regnum + i;
+ }
+
+ m_per_regset_regnum_range[m_register_set_count] =
+ std::make_pair(tls_regnum, m_dynamic_reg_infos.size());
+ m_dynamic_reg_sets.push_back(
+ {"Thread Local Storage Registers", "tls", num_regs, nullptr});
+ m_dynamic_reg_sets.back().registers = m_tls_regnum_collection.data();
+}
+
+void RegisterInfoCommon_arm64::AddRegSetSME(bool has_zt) {
+ const uint32_t first_sme_regnum = m_dynamic_reg_infos.size();
+ uint32_t sme_regnum = first_sme_regnum;
+
+ for (uint32_t i = 0; i < k_num_sme_register; ++i, ++sme_regnum) {
+ m_sme_regnum_collection.push_back(sme_regnum);
+ m_dynamic_reg_infos.push_back(g_register_infos_sme[i]);
+ m_dynamic_reg_infos[sme_regnum].byte_offset =
+ m_dynamic_reg_infos[sme_regnum - 1].byte_offset +
+ m_dynamic_reg_infos[sme_regnum - 1].byte_size;
+ m_dynamic_reg_infos[sme_regnum].kinds[lldb::eRegisterKindLLDB] = sme_regnum;
+ }
+
+ lldb_private::RegisterSet sme_regset = g_reg_set_sme_arm64;
+
+ if (has_zt) {
+ m_sme_regnum_collection.push_back(sme_regnum);
+ m_dynamic_reg_infos.push_back(g_register_infos_sme2[0]);
+ m_dynamic_reg_infos[sme_regnum].byte_offset =
+ m_dynamic_reg_infos[sme_regnum - 1].byte_offset +
+ m_dynamic_reg_infos[sme_regnum - 1].byte_size;
+ m_dynamic_reg_infos[sme_regnum].kinds[lldb::eRegisterKindLLDB] = sme_regnum;
+
+ sme_regset.num_registers += 1;
+ }
+
+ m_per_regset_regnum_range[m_register_set_count] =
+ std::make_pair(first_sme_regnum, m_dynamic_reg_infos.size());
+ m_dynamic_reg_sets.push_back(sme_regset);
+ m_dynamic_reg_sets.back().registers = m_sme_regnum_collection.data();
+
+ // When vg is written during streaming mode, svg will also change, as vg and
+ // svg in this state are both showing the streaming vector length.
+ // We model this as vg invalidating svg. In non-streaming mode this doesn't
+ // happen but to keep things simple we will invalidate svg anyway.
+ //
+ // This must be added now, rather than when vg is defined because SME is a
+ // dynamic set that may or may not be present.
+ static uint32_t vg_invalidates[] = {GetRegNumSMESVG(), LLDB_INVALID_REGNUM};
+ m_dynamic_reg_infos[GetRegNumSVEVG()].invalidate_regs = vg_invalidates;
+}
+
+void RegisterInfoCommon_arm64::AddRegSetFPMR() {
+ uint32_t fpmr_regnum = m_dynamic_reg_infos.size();
+ m_fpmr_regnum_collection.push_back(fpmr_regnum);
+ m_dynamic_reg_infos.push_back(g_register_infos_fpmr[0]);
+ m_dynamic_reg_infos[fpmr_regnum].byte_offset =
+ m_dynamic_reg_infos[fpmr_regnum - 1].byte_offset +
+ m_dynamic_reg_infos[fpmr_regnum - 1].byte_size;
+ m_dynamic_reg_infos[fpmr_regnum].kinds[lldb::eRegisterKindLLDB] = fpmr_regnum;
+
+ m_per_regset_regnum_range[m_register_set_count] =
+ std::make_pair(fpmr_regnum, fpmr_regnum + 1);
+ m_dynamic_reg_sets.push_back(g_reg_set_fpmr_arm64);
+ m_dynamic_reg_sets.back().registers = m_fpmr_regnum_collection.data();
+}
+
+void RegisterInfoCommon_arm64::AddRegSetGCS() {
+ uint32_t gcs_regnum = m_dynamic_reg_infos.size();
+ for (uint32_t i = 0; i < k_num_gcs_register; i++) {
+ m_gcs_regnum_collection.push_back(gcs_regnum + i);
+ m_dynamic_reg_infos.push_back(g_register_infos_gcs[i]);
+ m_dynamic_reg_infos[gcs_regnum + i].byte_offset =
+ m_dynamic_reg_infos[gcs_regnum + i - 1].byte_offset +
+ m_dynamic_reg_infos[gcs_regnum + i - 1].byte_size;
+ m_dynamic_reg_infos[gcs_regnum + i].kinds[lldb::eRegisterKindLLDB] =
+ gcs_regnum + i;
+ }
+
+ m_per_regset_regnum_range[m_register_set_count] =
+ std::make_pair(gcs_regnum, m_dynamic_reg_infos.size());
+ m_dynamic_reg_sets.push_back(g_reg_set_gcs_arm64);
+ m_dynamic_reg_sets.back().registers = m_gcs_regnum_collection.data();
+}
+
+void RegisterInfoCommon_arm64::AddRegSetPOE() {
+ uint32_t poe_regnum = m_dynamic_reg_infos.size();
+ m_poe_regnum_collection.push_back(poe_regnum);
+ m_dynamic_reg_infos.push_back(g_register_infos_poe[0]);
+ m_dynamic_reg_infos[poe_regnum].byte_offset =
+ m_dynamic_reg_infos[poe_regnum - 1].byte_offset +
+ m_dynamic_reg_infos[poe_regnum - 1].byte_size;
+ m_dynamic_reg_infos[poe_regnum].kinds[lldb::eRegisterKindLLDB] = poe_regnum;
+
+ m_per_regset_regnum_range[m_register_set_count] =
+ std::make_pair(poe_regnum, poe_regnum + 1);
+ m_dynamic_reg_sets.push_back(g_reg_set_poe_arm64);
+ m_dynamic_reg_sets.back().registers = m_poe_regnum_collection.data();
+}
+
+uint32_t RegisterInfoCommon_arm64::ConfigureVectorLengthSVE(uint32_t sve_vq) {
+ // sve_vq contains SVE Quad vector length in context of AArch64 SVE.
+ // SVE register infos if enabled cannot be disabled by selecting sve_vq = 0.
+ // Also if an invalid or previously set vector length is passed to this
+ // function then it will exit immediately with previously set vector length.
+ if (!VectorSizeIsValid(sve_vq) || m_vector_reg_vq == sve_vq)
+ return m_vector_reg_vq;
+
+ // We cannot enable AArch64 only mode if SVE was enabled.
+ if (sve_vq == eVectorQuadwordAArch64 &&
+ m_vector_reg_vq > eVectorQuadwordAArch64)
+ sve_vq = eVectorQuadwordAArch64SVE;
+
+ m_vector_reg_vq = sve_vq;
+
+ if (sve_vq == eVectorQuadwordAArch64)
+ return m_vector_reg_vq;
+ std::vector<lldb_private::RegisterInfo> ®_info_ref =
+ m_per_vq_reg_infos[sve_vq];
+
+ if (reg_info_ref.empty()) {
+ reg_info_ref = llvm::ArrayRef(m_register_info_p, m_register_info_count);
+
+ uint32_t offset = SVE_REGS_DEFAULT_OFFSET_LINUX;
+ reg_info_ref[fpu_fpsr].byte_offset = offset;
+ reg_info_ref[fpu_fpcr].byte_offset = offset + 4;
+ reg_info_ref[sve_vg].byte_offset = offset + 8;
+ offset += 16;
+
+ // Update Z registers size and offset
+ uint32_t s_reg_base = fpu_s0;
+ uint32_t d_reg_base = fpu_d0;
+ uint32_t v_reg_base = fpu_v0;
+ uint32_t z_reg_base = sve_z0;
+
+ for (uint32_t index = 0; index < 32; index++) {
+ reg_info_ref[s_reg_base + index].byte_offset = offset;
+ reg_info_ref[d_reg_base + index].byte_offset = offset;
+ reg_info_ref[v_reg_base + index].byte_offset = offset;
+ reg_info_ref[z_reg_base + index].byte_offset = offset;
+
+ reg_info_ref[z_reg_base + index].byte_size = sve_vq * SVE_QUAD_WORD_BYTES;
+ offset += reg_info_ref[z_reg_base + index].byte_size;
+ }
+
+ // Update P registers and FFR size and offset
+ for (uint32_t it = sve_p0; it <= sve_ffr; it++) {
+ reg_info_ref[it].byte_offset = offset;
+ reg_info_ref[it].byte_size = sve_vq * SVE_QUAD_WORD_BYTES / 8;
+ offset += reg_info_ref[it].byte_size;
+ }
+
+ for (uint32_t it = sve_ffr + 1; it < m_register_info_count; it++) {
+ reg_info_ref[it].byte_offset = offset;
+ offset += reg_info_ref[it].byte_size;
+ }
+
+ m_per_vq_reg_infos[sve_vq] = reg_info_ref;
+ }
+
+ m_register_info_p = m_per_vq_reg_infos[sve_vq].data();
+ return m_vector_reg_vq;
+}
+
+void RegisterInfoCommon_arm64::ConfigureVectorLengthZA(uint32_t za_vq) {
+ if (!VectorSizeIsValid(za_vq) || m_za_reg_vq == za_vq)
+ return;
+
+ m_za_reg_vq = za_vq;
+
+ // For SVE changes, we replace m_register_info_p completely. ZA is in a
+ // dynamic set and is just 1 register so we make an exception to const here.
+ lldb_private::RegisterInfo *non_const_reginfo =
+ const_cast<lldb_private::RegisterInfo *>(m_register_info_p);
+ non_const_reginfo[m_sme_regnum_collection[2]].byte_size =
+ (za_vq * 16) * (za_vq * 16);
+}
+
+bool RegisterInfoCommon_arm64::IsSVEReg(unsigned reg) const {
+ if (m_vector_reg_vq > eVectorQuadwordAArch64)
+ return (sve_vg <= reg && reg <= sve_ffr);
+ else
+ return false;
+}
+
+bool RegisterInfoCommon_arm64::IsSVEZReg(unsigned reg) const {
+ return (sve_z0 <= reg && reg <= sve_z31);
+}
+
+bool RegisterInfoCommon_arm64::IsSVEPReg(unsigned reg) const {
+ return (sve_p0 <= reg && reg <= sve_p15);
+}
+
+bool RegisterInfoCommon_arm64::IsSVERegVG(unsigned reg) const {
+ return sve_vg == reg;
+}
+
+bool RegisterInfoCommon_arm64::IsSVERegFFR(unsigned reg) const {
+ return sve_ffr == reg;
+}
+
+bool RegisterInfoCommon_arm64::IsSMERegZA(unsigned reg) const {
+ return reg == m_sme_regnum_collection[2];
+}
+
+bool RegisterInfoCommon_arm64::IsSMERegZT(unsigned reg) const {
+ // ZT0 is part of the SME register set only if SME2 is present.
+ return m_sme_regnum_collection.size() >= 4 &&
+ reg == m_sme_regnum_collection[3];
+}
+
+bool RegisterInfoCommon_arm64::IsGPR(unsigned reg) const {
+ return GetRegisterSetFromRegisterIndex(reg) ==
+ RegisterInfoCommon_arm64::GPRegSet;
+}
+
+bool RegisterInfoCommon_arm64::IsFPR(unsigned reg) const {
+ return GetRegisterSetFromRegisterIndex(reg) ==
+ RegisterInfoCommon_arm64::FPRegSet;
+}
+
+bool RegisterInfoCommon_arm64::IsPAuthReg(unsigned reg) const {
+ return llvm::is_contained(pauth_regnum_collection, reg);
+}
+
+bool RegisterInfoCommon_arm64::IsMTEReg(unsigned reg) const {
+ return llvm::is_contained(m_mte_regnum_collection, reg);
+}
+
+bool RegisterInfoCommon_arm64::IsTLSReg(unsigned reg) const {
+ return llvm::is_contained(m_tls_regnum_collection, reg);
+}
+
+bool RegisterInfoCommon_arm64::IsSMEReg(unsigned reg) const {
+ return llvm::is_contained(m_sme_regnum_collection, reg);
+}
+
+bool RegisterInfoCommon_arm64::IsFPMRReg(unsigned reg) const {
+ return llvm::is_contained(m_fpmr_regnum_collection, reg);
+}
+
+bool RegisterInfoCommon_arm64::IsGCSReg(unsigned reg) const {
+ return llvm::is_contained(m_gcs_regnum_collection, reg);
+}
+
+bool RegisterInfoCommon_arm64::IsPOEReg(unsigned reg) const {
+ return llvm::is_contained(m_poe_regnum_collection, reg);
+}
+
+uint32_t RegisterInfoCommon_arm64::GetRegNumSVEZ0() const { return sve_z0; }
+
+uint32_t RegisterInfoCommon_arm64::GetRegNumSVEFFR() const { return sve_ffr; }
+
+uint32_t RegisterInfoCommon_arm64::GetRegNumFPCR() const { return fpu_fpcr; }
+
+uint32_t RegisterInfoCommon_arm64::GetRegNumFPSR() const { return fpu_fpsr; }
+
+uint32_t RegisterInfoCommon_arm64::GetRegNumFPV0() const { return fpu_v0; }
+
+uint32_t RegisterInfoCommon_arm64::GetRegNumSVEVG() const { return sve_vg; }
+
+uint32_t RegisterInfoCommon_arm64::GetRegNumSMESVG() const {
+ return m_sme_regnum_collection[1];
+}
+
+uint32_t RegisterInfoCommon_arm64::GetPAuthOffset() const {
+ return m_register_info_p[pauth_regnum_collection[0]].byte_offset;
+}
+
+uint32_t RegisterInfoCommon_arm64::GetMTEOffset() const {
+ return m_register_info_p[m_mte_regnum_collection[0]].byte_offset;
+}
+
+uint32_t RegisterInfoCommon_arm64::GetTLSOffset() const {
+ return m_register_info_p[m_tls_regnum_collection[0]].byte_offset;
+}
+
+uint32_t RegisterInfoCommon_arm64::GetSMEOffset() const {
+ return m_register_info_p[m_sme_regnum_collection[0]].byte_offset;
+}
+
+uint32_t RegisterInfoCommon_arm64::GetFPMROffset() const {
+ return m_register_info_p[m_fpmr_regnum_collection[0]].byte_offset;
+}
+
+uint32_t RegisterInfoCommon_arm64::GetGCSOffset() const {
+ return m_register_info_p[m_gcs_regnum_collection[0]].byte_offset;
+}
+
+uint32_t RegisterInfoCommon_arm64::GetPOEOffset() const {
+ return m_register_info_p[m_poe_regnum_collection[0]].byte_offset;
+}
diff --git a/lldb/source/Register/Common/RegisterInfoCommon_arm64.h b/lldb/source/Register/Common/RegisterInfoCommon_arm64.h
new file mode 100644
index 00000000000000..a3b94be43c7883
--- /dev/null
+++ b/lldb/source/Register/Common/RegisterInfoCommon_arm64.h
@@ -0,0 +1,226 @@
+//===-- RegisterInfoCommon_arm64.h -------------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLDB_SOURCE_REGISTER_COMMON_REGISTERINFOCOMMON_ARM64_H
+#define LLDB_SOURCE_REGISTER_COMMON_REGISTERINFOCOMMON_ARM64_H
+
+#include "Register/RegisterInfoAndSetInterface.h"
+#include "lldb/Target/RegisterContext.h"
+#include "lldb/Utility/Flags.h"
+#include "lldb/lldb-private.h"
+#include <map>
+
+enum class SVEState : uint8_t {
+ // We have yet to look what features there are.
+ Unknown,
+ // We know that there is no SVE or streaming SVE (SME).
+ Disabled,
+ // We are in non-streaming mode but SVE is not active.
+ FPSIMD,
+ // We are in non-streaming mode and SVE is active.
+ Full,
+ // We are in streaming mode using streaming SVE.
+ Streaming,
+ // We are in non-streaming mode, and only have SVE while in streaming mode.
+ StreamingFPSIMD
+};
+
+class RegisterInfoCommon_arm64
+ : public lldb_private::RegisterInfoAndSetInterface {
+public:
+ enum { GPRegSet = 0, FPRegSet };
+
+ // AArch64 register set mask value
+ enum {
+ eRegsetMaskDefault = 0,
+ eRegsetMaskSVE = 1,
+ eRegsetMaskSSVE = 2,
+ eRegsetMaskPAuth = 4,
+ eRegsetMaskMTE = 8,
+ eRegsetMaskTLS = 16,
+ eRegsetMaskZA = 32,
+ eRegsetMaskZT = 64,
+ eRegsetMaskFPMR = 128,
+ eRegsetMaskGCS = 256,
+ eRegsetMaskPOE = 512,
+ eRegsetMaskDynamic = ~1,
+ };
+
+ // AArch64 Register set FP/SIMD feature configuration
+ enum {
+ eVectorQuadwordAArch64,
+ eVectorQuadwordAArch64SVE,
+ eVectorQuadwordAArch64SVEMax = 256
+ };
+
+ // based on RegisterContextDarwin_arm64.h
+ // Pack this so there are no extra bytes, but align its start address to at
+ // least 8 bytes to prevent alignment errors.
+ LLVM_PACKED_START
+ struct alignas(8) GPR {
+ uint64_t x[29]; // x0-x28
+ uint64_t fp; // x29
+ uint64_t lr; // x30
+ uint64_t sp; // x31
+ uint64_t pc; // pc
+ uint32_t cpsr; // cpsr
+ uint32_t pad;
+ };
+ LLVM_PACKED_END
+
+ // based on RegisterContextDarwin_arm64.h
+ struct VReg {
+ uint8_t bytes[16];
+ };
+
+ // based on RegisterContextDarwin_arm64.h
+ struct FPU {
+ VReg v[32];
+ uint32_t fpsr;
+ uint32_t fpcr;
+ };
+
+ // based on RegisterContextDarwin_arm64.h
+ struct EXC {
+ uint64_t far; // Virtual Fault Address
+ uint32_t esr; // Exception syndrome
+ uint32_t exception; // number of arm exception token
+ };
+
+ // based on RegisterContextDarwin_arm64.h
+ struct DBG {
+ uint64_t bvr[16];
+ uint64_t bcr[16];
+ uint64_t wvr[16];
+ uint64_t wcr[16];
+ uint64_t mdscr_el1;
+ };
+
+ RegisterInfoCommon_arm64(const lldb_private::ArchSpec &target_arch,
+ lldb_private::Flags opt_regsets);
+
+ static size_t GetGPRSizeStatic();
+ size_t GetGPRSize() const override { return GetGPRSizeStatic(); }
+
+ size_t GetFPRSize() const override;
+
+ const lldb_private::RegisterInfo *GetRegisterInfo() const override;
+
+ uint32_t GetRegisterCount() const override;
+
+ const lldb_private::RegisterSet *
+ GetRegisterSet(size_t reg_set) const override;
+
+ size_t GetRegisterSetCount() const override;
+
+ size_t GetRegisterSetFromRegisterIndex(uint32_t reg_index) const override;
+
+ void AddRegSetPAuth();
+
+ void AddRegSetMTE();
+
+ void AddRegSetTLS(bool has_tpidr2);
+
+ void AddRegSetSME(bool has_zt);
+
+ void AddRegSetFPMR();
+
+ void AddRegSetGCS();
+
+ void AddRegSetPOE();
+
+ uint32_t ConfigureVectorLengthSVE(uint32_t sve_vq);
+
+ void ConfigureVectorLengthZA(uint32_t za_vq);
+
+ bool VectorSizeIsValid(uint32_t vq) {
+ // coverity[unsigned_compare]
+ if (vq >= eVectorQuadwordAArch64 && vq <= eVectorQuadwordAArch64SVEMax)
+ return true;
+ return false;
+ }
+
+ bool IsSVEPresent() const { return m_opt_regsets.AnySet(eRegsetMaskSVE); }
+ bool IsSSVEPresent() const { return m_opt_regsets.AnySet(eRegsetMaskSSVE); }
+ bool IsZAPresent() const { return m_opt_regsets.AnySet(eRegsetMaskZA); }
+ bool IsZTPresent() const { return m_opt_regsets.AnySet(eRegsetMaskZT); }
+ bool IsPAuthPresent() const { return m_opt_regsets.AnySet(eRegsetMaskPAuth); }
+ bool IsMTEPresent() const { return m_opt_regsets.AnySet(eRegsetMaskMTE); }
+ bool IsTLSPresent() const { return m_opt_regsets.AnySet(eRegsetMaskTLS); }
+ bool IsFPMRPresent() const { return m_opt_regsets.AnySet(eRegsetMaskFPMR); }
+ bool IsGCSPresent() const { return m_opt_regsets.AnySet(eRegsetMaskGCS); }
+ bool IsPOEPresent() const { return m_opt_regsets.AnySet(eRegsetMaskPOE); }
+
+ bool IsGPR(unsigned reg) const;
+ bool IsFPR(unsigned reg) const;
+ bool IsSVEReg(unsigned reg) const;
+ bool IsSVEZReg(unsigned reg) const;
+ bool IsSVEPReg(unsigned reg) const;
+ bool IsSVERegVG(unsigned reg) const;
+ bool IsSVERegFFR(unsigned reg) const;
+ bool IsPAuthReg(unsigned reg) const;
+ bool IsMTEReg(unsigned reg) const;
+ bool IsTLSReg(unsigned reg) const;
+ bool IsSMEReg(unsigned reg) const;
+ bool IsSMERegZA(unsigned reg) const;
+ bool IsSMERegZT(unsigned reg) const;
+ bool IsFPMRReg(unsigned reg) const;
+ bool IsGCSReg(unsigned reg) const;
+ bool IsPOEReg(unsigned reg) const;
+
+ uint32_t GetRegNumSVEZ0() const;
+ uint32_t GetRegNumSVEFFR() const;
+ uint32_t GetRegNumFPCR() const;
+ uint32_t GetRegNumFPSR() const;
+ uint32_t GetRegNumFPV0() const;
+ uint32_t GetRegNumSVEVG() const;
+ uint32_t GetRegNumSMESVG() const;
+ uint32_t GetPAuthOffset() const;
+ uint32_t GetMTEOffset() const;
+ uint32_t GetTLSOffset() const;
+ uint32_t GetSMEOffset() const;
+ uint32_t GetFPMROffset() const;
+ uint32_t GetGCSOffset() const;
+ uint32_t GetPOEOffset() const;
+
+private:
+ typedef std::map<uint32_t, std::vector<lldb_private::RegisterInfo>>
+ per_vq_register_infos;
+
+ per_vq_register_infos m_per_vq_reg_infos;
+
+ uint32_t m_vector_reg_vq = eVectorQuadwordAArch64;
+ uint32_t m_za_reg_vq = eVectorQuadwordAArch64;
+
+ // In normal operation this is const. Only when SVE or SME registers change
+ // size is it either replaced or the content modified.
+ const lldb_private::RegisterInfo *m_register_info_p;
+ uint32_t m_register_info_count;
+
+ const lldb_private::RegisterSet *m_register_set_p;
+ uint32_t m_register_set_count;
+
+ // Contains pair of [start, end] register numbers of a register set with start
+ // and end included.
+ std::map<uint32_t, std::pair<uint32_t, uint32_t>> m_per_regset_regnum_range;
+
+ lldb_private::Flags m_opt_regsets;
+
+ std::vector<lldb_private::RegisterInfo> m_dynamic_reg_infos;
+ std::vector<lldb_private::RegisterSet> m_dynamic_reg_sets;
+
+ std::vector<uint32_t> pauth_regnum_collection;
+ std::vector<uint32_t> m_mte_regnum_collection;
+ std::vector<uint32_t> m_tls_regnum_collection;
+ std::vector<uint32_t> m_sme_regnum_collection;
+ std::vector<uint32_t> m_fpmr_regnum_collection;
+ std::vector<uint32_t> m_gcs_regnum_collection;
+ std::vector<uint32_t> m_poe_regnum_collection;
+};
+
+#endif
diff --git a/lldb/source/Register/Common/RegisterInfoCommon_loongarch64.cpp b/lldb/source/Register/Common/RegisterInfoCommon_loongarch64.cpp
new file mode 100644
index 00000000000000..e97ba7f5f11c07
--- /dev/null
+++ b/lldb/source/Register/Common/RegisterInfoCommon_loongarch64.cpp
@@ -0,0 +1,215 @@
+//===-- RegisterInfoCommon_loongarch64.cpp --------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===---------------------------------------------------------------------===//
+
+#include <cassert>
+#include <lldb/Utility/Flags.h>
+#include <stddef.h>
+
+#include "lldb/lldb-defines.h"
+#include "llvm/Support/Compiler.h"
+
+#include "Register/Common/RegisterInfoCommon_loongarch64.h"
+
+#define GPR_OFFSET(idx) ((idx)*8 + 0)
+#define FPR_OFFSET(idx) ((idx)*8 + sizeof(RegisterInfoCommon_loongarch64::GPR))
+#define FCC_OFFSET(idx) ((idx)*1 + 32 * 8 + sizeof(RegisterInfoCommon_loongarch64::GPR))
+#define FCSR_OFFSET (8 * 1 + 32 * 8 + sizeof(RegisterInfoCommon_loongarch64::GPR))
+#define LSX_OFFSET(idx) \
+ ((idx) * 16 + sizeof(RegisterInfoCommon_loongarch64::GPR) + \
+ sizeof(RegisterInfoCommon_loongarch64::FPR))
+#define LASX_OFFSET(idx) \
+ ((idx) * 32 + sizeof(RegisterInfoCommon_loongarch64::GPR) + \
+ sizeof(RegisterInfoCommon_loongarch64::FPR) + \
+ sizeof(RegisterInfoCommon_loongarch64::LSX))
+
+#define REG_CONTEXT_SIZE \
+ (sizeof(RegisterInfoCommon_loongarch64::GPR) + \
+ sizeof(RegisterInfoCommon_loongarch64::FPR) + \
+ sizeof(RegisterInfoCommon_loongarch64::LSX) + \
+ sizeof(RegisterInfoCommon_loongarch64::LASX))
+
+#define DECLARE_REGISTER_INFOS_LOONGARCH64_STRUCT
+#include "Register/Arch/RegisterInfos_loongarch64.h"
+#undef DECLARE_REGISTER_INFOS_LOONGARCH64_STRUCT
+
+const lldb_private::RegisterInfo *
+RegisterInfoCommon_loongarch64::GetRegisterInfoPtr(
+ const lldb_private::ArchSpec &target_arch) {
+ switch (target_arch.GetMachine()) {
+ case llvm::Triple::loongarch64:
+ return g_register_infos_loongarch64;
+ default:
+ assert(false && "Unhandled target architecture.");
+ return nullptr;
+ }
+}
+
+uint32_t RegisterInfoCommon_loongarch64::GetRegisterInfoCount(
+ const lldb_private::ArchSpec &target_arch) {
+ switch (target_arch.GetMachine()) {
+ case llvm::Triple::loongarch64:
+ return static_cast<uint32_t>(sizeof(g_register_infos_loongarch64) /
+ sizeof(g_register_infos_loongarch64[0]));
+ default:
+ assert(false && "Unhandled target architecture.");
+ return 0;
+ }
+}
+
+// Number of register sets provided by this context.
+enum {
+ k_num_gpr_registers = gpr_last_loongarch - gpr_first_loongarch + 1,
+ k_num_fpr_registers = fpr_last_loongarch - fpr_first_loongarch + 1,
+ k_num_lsx_registers = lsx_last_loongarch - lsx_first_loongarch + 1,
+ k_num_lasx_registers = lasx_last_loongarch - lasx_first_loongarch + 1,
+ k_num_register_sets = 4
+};
+
+// LoongArch64 general purpose registers.
+static const uint32_t g_gpr_regnums_loongarch64[] = {
+ gpr_r0_loongarch, gpr_r1_loongarch, gpr_r2_loongarch,
+ gpr_r3_loongarch, gpr_r4_loongarch, gpr_r5_loongarch,
+ gpr_r6_loongarch, gpr_r7_loongarch, gpr_r8_loongarch,
+ gpr_r9_loongarch, gpr_r10_loongarch, gpr_r11_loongarch,
+ gpr_r12_loongarch, gpr_r13_loongarch, gpr_r14_loongarch,
+ gpr_r15_loongarch, gpr_r16_loongarch, gpr_r17_loongarch,
+ gpr_r18_loongarch, gpr_r19_loongarch, gpr_r20_loongarch,
+ gpr_r21_loongarch, gpr_r22_loongarch, gpr_r23_loongarch,
+ gpr_r24_loongarch, gpr_r25_loongarch, gpr_r26_loongarch,
+ gpr_r27_loongarch, gpr_r28_loongarch, gpr_r29_loongarch,
+ gpr_r30_loongarch, gpr_r31_loongarch, gpr_orig_a0_loongarch,
+ gpr_pc_loongarch, gpr_badv_loongarch, gpr_reserved0_loongarch,
+ gpr_reserved1_loongarch, gpr_reserved2_loongarch, gpr_reserved3_loongarch,
+ gpr_reserved4_loongarch, gpr_reserved5_loongarch, gpr_reserved6_loongarch,
+ gpr_reserved7_loongarch, gpr_reserved8_loongarch, gpr_reserved9_loongarch,
+ LLDB_INVALID_REGNUM};
+
+static_assert(((sizeof g_gpr_regnums_loongarch64 /
+ sizeof g_gpr_regnums_loongarch64[0]) -
+ 1) == k_num_gpr_registers,
+ "g_gpr_regnums_loongarch64 has wrong number of register infos");
+
+// LoongArch64 floating point registers.
+static const uint32_t g_fpr_regnums_loongarch64[] = {
+ fpr_f0_loongarch, fpr_f1_loongarch, fpr_f2_loongarch,
+ fpr_f3_loongarch, fpr_f4_loongarch, fpr_f5_loongarch,
+ fpr_f6_loongarch, fpr_f7_loongarch, fpr_f8_loongarch,
+ fpr_f9_loongarch, fpr_f10_loongarch, fpr_f11_loongarch,
+ fpr_f12_loongarch, fpr_f13_loongarch, fpr_f14_loongarch,
+ fpr_f15_loongarch, fpr_f16_loongarch, fpr_f17_loongarch,
+ fpr_f18_loongarch, fpr_f19_loongarch, fpr_f20_loongarch,
+ fpr_f21_loongarch, fpr_f22_loongarch, fpr_f23_loongarch,
+ fpr_f24_loongarch, fpr_f25_loongarch, fpr_f26_loongarch,
+ fpr_f27_loongarch, fpr_f28_loongarch, fpr_f29_loongarch,
+ fpr_f30_loongarch, fpr_f31_loongarch, fpr_fcc0_loongarch,
+ fpr_fcc1_loongarch, fpr_fcc2_loongarch, fpr_fcc3_loongarch,
+ fpr_fcc4_loongarch, fpr_fcc5_loongarch, fpr_fcc6_loongarch,
+ fpr_fcc7_loongarch, fpr_fcsr_loongarch, LLDB_INVALID_REGNUM};
+
+static_assert(((sizeof g_fpr_regnums_loongarch64 /
+ sizeof g_fpr_regnums_loongarch64[0]) -
+ 1) == k_num_fpr_registers,
+ "g_fpr_regnums_loongarch64 has wrong number of register infos");
+
+// LoongArch64 lsx vector registers.
+static const uint32_t g_lsx_regnums_loongarch64[] = {
+ lsx_vr0_loongarch, lsx_vr1_loongarch, lsx_vr2_loongarch,
+ lsx_vr3_loongarch, lsx_vr4_loongarch, lsx_vr5_loongarch,
+ lsx_vr6_loongarch, lsx_vr7_loongarch, lsx_vr8_loongarch,
+ lsx_vr9_loongarch, lsx_vr10_loongarch, lsx_vr11_loongarch,
+ lsx_vr12_loongarch, lsx_vr13_loongarch, lsx_vr14_loongarch,
+ lsx_vr15_loongarch, lsx_vr16_loongarch, lsx_vr17_loongarch,
+ lsx_vr18_loongarch, lsx_vr19_loongarch, lsx_vr20_loongarch,
+ lsx_vr21_loongarch, lsx_vr22_loongarch, lsx_vr23_loongarch,
+ lsx_vr24_loongarch, lsx_vr25_loongarch, lsx_vr26_loongarch,
+ lsx_vr27_loongarch, lsx_vr28_loongarch, lsx_vr29_loongarch,
+ lsx_vr30_loongarch, lsx_vr31_loongarch, LLDB_INVALID_REGNUM};
+
+static_assert(((sizeof g_lsx_regnums_loongarch64 /
+ sizeof g_lsx_regnums_loongarch64[0]) -
+ 1) == k_num_lsx_registers,
+ "g_lsx_regnums_loongarch64 has wrong number of register infos");
+
+// LoongArch64 lasx vector registers.
+static const uint32_t g_lasx_regnums_loongarch64[] = {
+ lasx_xr0_loongarch, lasx_xr1_loongarch, lasx_xr2_loongarch,
+ lasx_xr3_loongarch, lasx_xr4_loongarch, lasx_xr5_loongarch,
+ lasx_xr6_loongarch, lasx_xr7_loongarch, lasx_xr8_loongarch,
+ lasx_xr9_loongarch, lasx_xr10_loongarch, lasx_xr11_loongarch,
+ lasx_xr12_loongarch, lasx_xr13_loongarch, lasx_xr14_loongarch,
+ lasx_xr15_loongarch, lasx_xr16_loongarch, lasx_xr17_loongarch,
+ lasx_xr18_loongarch, lasx_xr19_loongarch, lasx_xr20_loongarch,
+ lasx_xr21_loongarch, lasx_xr22_loongarch, lasx_xr23_loongarch,
+ lasx_xr24_loongarch, lasx_xr25_loongarch, lasx_xr26_loongarch,
+ lasx_xr27_loongarch, lasx_xr28_loongarch, lasx_xr29_loongarch,
+ lasx_xr30_loongarch, lasx_xr31_loongarch, LLDB_INVALID_REGNUM};
+
+static_assert(((sizeof g_lasx_regnums_loongarch64 /
+ sizeof g_lasx_regnums_loongarch64[0]) -
+ 1) == k_num_lasx_registers,
+ "g_lasx_regnums_loongarch64 has wrong number of register infos");
+
+// Register sets for LoongArch64.
+static const lldb_private::RegisterSet
+ g_reg_sets_loongarch64[k_num_register_sets] = {
+ {"General Purpose Registers", "gpr", k_num_gpr_registers,
+ g_gpr_regnums_loongarch64},
+ {"Floating Point Registers", "fpr", k_num_fpr_registers,
+ g_fpr_regnums_loongarch64},
+ {"LSX Vector Registers", "lsx", k_num_lsx_registers,
+ g_lsx_regnums_loongarch64},
+ {"LASX Vector Registers", "lasx", k_num_lasx_registers,
+ g_lasx_regnums_loongarch64}};
+
+RegisterInfoCommon_loongarch64::RegisterInfoCommon_loongarch64(
+ const lldb_private::ArchSpec &target_arch, lldb_private::Flags flags)
+ : lldb_private::RegisterInfoAndSetInterface(target_arch),
+ m_register_info_p(GetRegisterInfoPtr(target_arch)),
+ m_register_info_count(GetRegisterInfoCount(target_arch)) {}
+
+uint32_t RegisterInfoCommon_loongarch64::GetRegisterCount() const {
+ return m_register_info_count;
+}
+
+size_t RegisterInfoCommon_loongarch64::GetGPRSize() const {
+ return sizeof(struct RegisterInfoCommon_loongarch64::GPR);
+}
+
+size_t RegisterInfoCommon_loongarch64::GetFPRSize() const {
+ return sizeof(struct RegisterInfoCommon_loongarch64::FPR);
+}
+
+const lldb_private::RegisterInfo *
+RegisterInfoCommon_loongarch64::GetRegisterInfo() const {
+ return m_register_info_p;
+}
+
+size_t RegisterInfoCommon_loongarch64::GetRegisterSetCount() const {
+ return k_num_register_sets;
+}
+
+size_t RegisterInfoCommon_loongarch64::GetRegisterSetFromRegisterIndex(
+ uint32_t reg_index) const {
+ // coverity[unsigned_compare]
+ if (reg_index >= gpr_first_loongarch && reg_index <= gpr_last_loongarch)
+ return GPRegSet;
+ if (reg_index >= fpr_first_loongarch && reg_index <= fpr_last_loongarch)
+ return FPRegSet;
+ if (reg_index >= lsx_first_loongarch && reg_index <= lsx_last_loongarch)
+ return LSXRegSet;
+ if (reg_index >= lasx_first_loongarch && reg_index <= lasx_last_loongarch)
+ return LASXRegSet;
+ return LLDB_INVALID_REGNUM;
+}
+
+const lldb_private::RegisterSet *
+RegisterInfoCommon_loongarch64::GetRegisterSet(size_t set_index) const {
+ if (set_index < GetRegisterSetCount())
+ return &g_reg_sets_loongarch64[set_index];
+ return nullptr;
+}
diff --git a/lldb/source/Register/Common/RegisterInfoCommon_loongarch64.h b/lldb/source/Register/Common/RegisterInfoCommon_loongarch64.h
new file mode 100644
index 00000000000000..8438a57c8b33f8
--- /dev/null
+++ b/lldb/source/Register/Common/RegisterInfoCommon_loongarch64.h
@@ -0,0 +1,81 @@
+//===-- RegisterInfoCommon_loongarch64.h -------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLDB_SOURCE_REGISTER_COMMON_REGISTERINFOCOMMON_LOONGARCH64_H
+#define LLDB_SOURCE_REGISTER_COMMON_REGISTERINFOCOMMON_LOONGARCH64_H
+
+#include "Register/RegisterInfoAndSetInterface.h"
+#include "lldb/Target/RegisterContext.h"
+#include "lldb/lldb-private.h"
+#include <map>
+
+class RegisterInfoCommon_loongarch64
+ : public lldb_private::RegisterInfoAndSetInterface {
+public:
+ static const lldb_private::RegisterInfo *
+ GetRegisterInfoPtr(const lldb_private::ArchSpec &target_arch);
+ static uint32_t
+ GetRegisterInfoCount(const lldb_private::ArchSpec &target_arch);
+
+public:
+ enum RegSetKind {
+ GPRegSet,
+ FPRegSet,
+ LSXRegSet,
+ LASXRegSet,
+ };
+
+ struct GPR {
+ uint64_t gpr[32];
+
+ uint64_t orig_a0;
+ uint64_t csr_era;
+ uint64_t csr_badv;
+ uint64_t reserved[10];
+ };
+
+ struct FPR {
+ uint64_t fpr[32];
+ uint64_t fcc;
+ uint32_t fcsr;
+ };
+
+ /* 32 registers, 128 bits width per register. */
+ struct LSX {
+ uint64_t vr[32 * 2];
+ };
+
+ /* 32 registers, 256 bits width per register. */
+ struct LASX {
+ uint64_t xr[32 * 4];
+ };
+
+ RegisterInfoCommon_loongarch64(const lldb_private::ArchSpec &target_arch,
+ lldb_private::Flags flags);
+
+ size_t GetGPRSize() const override;
+
+ size_t GetFPRSize() const override;
+
+ const lldb_private::RegisterInfo *GetRegisterInfo() const override;
+
+ uint32_t GetRegisterCount() const override;
+
+ const lldb_private::RegisterSet *
+ GetRegisterSet(size_t reg_set) const override;
+
+ size_t GetRegisterSetCount() const override;
+
+ size_t GetRegisterSetFromRegisterIndex(uint32_t reg_index) const override;
+
+private:
+ const lldb_private::RegisterInfo *m_register_info_p;
+ uint32_t m_register_info_count;
+};
+
+#endif
diff --git a/lldb/source/Register/Common/RegisterInfoCommon_ppc64.cpp b/lldb/source/Register/Common/RegisterInfoCommon_ppc64.cpp
new file mode 100644
index 00000000000000..feb6e5d577f661
--- /dev/null
+++ b/lldb/source/Register/Common/RegisterInfoCommon_ppc64.cpp
@@ -0,0 +1,78 @@
+//===-- RegisterInfoCommon_ppc64.cpp ---------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include <cassert>
+#include <cstddef>
+#include <vector>
+
+#include "lldb/lldb-defines.h"
+#include "llvm/Support/Compiler.h"
+
+#include "Register/Common/RegisterInfoCommon_ppc64.h"
+
+// Include RegisterInfoCommon_ppc64 to declare our g_register_infos_ppc64
+#define DECLARE_REGISTER_INFOS_PPC64_STRUCT
+#include "Register/Arch/RegisterInfos_ppc64.h"
+#undef DECLARE_REGISTER_INFOS_PPC64_STRUCT
+
+static const lldb_private::RegisterInfo *
+GetRegisterInfoPtr(const lldb_private::ArchSpec &target_arch) {
+ switch (target_arch.GetMachine()) {
+ case llvm::Triple::ppc:
+ return g_register_infos_ppc;
+ case llvm::Triple::ppc64:
+ return g_register_infos_ppc64;
+ default:
+ assert(false && "Unhandled target architecture.");
+ return nullptr;
+ }
+}
+
+static uint32_t
+GetRegisterInfoCount(const lldb_private::ArchSpec &target_arch) {
+ switch (target_arch.GetMachine()) {
+ case llvm::Triple::ppc:
+ return static_cast<uint32_t>(sizeof(g_register_infos_ppc) /
+ sizeof(g_register_infos_ppc[0]));
+ case llvm::Triple::ppc64:
+ return static_cast<uint32_t>(sizeof(g_register_infos_ppc64) /
+ sizeof(g_register_infos_ppc64[0]));
+ default:
+ assert(false && "Unhandled target architecture.");
+ return 0;
+ }
+}
+
+RegisterInfoCommon_ppc64::RegisterInfoCommon_ppc64(
+ const lldb_private::ArchSpec &target_arch)
+ : lldb_private::RegisterInfoInterface(target_arch),
+ m_register_info_p(GetRegisterInfoPtr(target_arch)),
+ m_register_info_count(GetRegisterInfoCount(target_arch)), m_gpr_size(0) {
+ switch (target_arch.GetMachine()) {
+ case llvm::Triple::ppc:
+ m_gpr_size = sizeof(GPR_PPC);
+ break;
+ case llvm::Triple::ppc64:
+ m_gpr_size = sizeof(GPR_PPC64);
+ break;
+ default:
+ assert(false && "Unhandled target architecture.");
+ break;
+ }
+}
+
+size_t RegisterInfoCommon_ppc64::GetGPRSize() const { return m_gpr_size; }
+
+const lldb_private::RegisterInfo *
+RegisterInfoCommon_ppc64::GetRegisterInfo() const {
+ return m_register_info_p;
+}
+
+uint32_t RegisterInfoCommon_ppc64::GetRegisterCount() const {
+ return m_register_info_count;
+}
diff --git a/lldb/source/Register/Common/RegisterInfoCommon_ppc64.h b/lldb/source/Register/Common/RegisterInfoCommon_ppc64.h
new file mode 100644
index 00000000000000..51a3cac7188e7a
--- /dev/null
+++ b/lldb/source/Register/Common/RegisterInfoCommon_ppc64.h
@@ -0,0 +1,32 @@
+//===-- RegisterInfoCommon_ppc64.h -------------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLDB_SOURCE_REGISTER_COMMON_REGISTERINFOCOMMON_PPC64_H
+#define LLDB_SOURCE_REGISTER_COMMON_REGISTERINFOCOMMON_PPC64_H
+
+#include "Register/RegisterInfoInterface.h"
+#include "lldb/Target/RegisterContext.h"
+#include "lldb/lldb-private.h"
+
+class RegisterInfoCommon_ppc64 : public lldb_private::RegisterInfoInterface {
+public:
+ RegisterInfoCommon_ppc64(const lldb_private::ArchSpec &target_arch);
+
+ size_t GetGPRSize() const override;
+
+ const lldb_private::RegisterInfo *GetRegisterInfo() const override;
+
+ uint32_t GetRegisterCount() const override;
+
+private:
+ const lldb_private::RegisterInfo *m_register_info_p;
+ uint32_t m_register_info_count;
+ size_t m_gpr_size;
+};
+
+#endif // LLDB_SOURCE_REGISTER_COMMON_REGISTERINFOCOMMON_PPC64_H
diff --git a/lldb/source/Register/Common/RegisterInfoCommon_ppc64le.cpp b/lldb/source/Register/Common/RegisterInfoCommon_ppc64le.cpp
new file mode 100644
index 00000000000000..09a28d7bb5a168
--- /dev/null
+++ b/lldb/source/Register/Common/RegisterInfoCommon_ppc64le.cpp
@@ -0,0 +1,63 @@
+//===-- RegisterInfoCommon_ppc64le.cpp -------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===---------------------------------------------------------------------===//
+
+#include <cassert>
+#include <cstddef>
+#include <vector>
+
+#include "lldb/lldb-defines.h"
+#include "llvm/Support/Compiler.h"
+
+#include "Register/Common/RegisterInfoCommon_ppc64le.h"
+
+// Include RegisterInfoCommon_ppc64le to declare our g_register_infos_ppc64le
+#define DECLARE_REGISTER_INFOS_PPC64LE_STRUCT
+#include "Register/Arch/RegisterInfos_ppc64le.h"
+#undef DECLARE_REGISTER_INFOS_PPC64LE_STRUCT
+
+static const lldb_private::RegisterInfo *
+GetRegisterInfoPtr(const lldb_private::ArchSpec &target_arch) {
+ switch (target_arch.GetMachine()) {
+ case llvm::Triple::ppc64le:
+ return g_register_infos_ppc64le;
+ default:
+ assert(false && "Unhandled target architecture.");
+ return nullptr;
+ }
+}
+
+static uint32_t
+GetRegisterInfoCount(const lldb_private::ArchSpec &target_arch) {
+ switch (target_arch.GetMachine()) {
+ case llvm::Triple::ppc64le:
+ return static_cast<uint32_t>(sizeof(g_register_infos_ppc64le) /
+ sizeof(g_register_infos_ppc64le[0]));
+ default:
+ assert(false && "Unhandled target architecture.");
+ return 0;
+ }
+}
+
+RegisterInfoCommon_ppc64le::RegisterInfoCommon_ppc64le(
+ const lldb_private::ArchSpec &target_arch)
+ : lldb_private::RegisterInfoInterface(target_arch),
+ m_register_info_p(GetRegisterInfoPtr(target_arch)),
+ m_register_info_count(GetRegisterInfoCount(target_arch)) {}
+
+size_t RegisterInfoCommon_ppc64le::GetGPRSize() const {
+ return sizeof(GPR);
+}
+
+const lldb_private::RegisterInfo *
+RegisterInfoCommon_ppc64le::GetRegisterInfo() const {
+ return m_register_info_p;
+}
+
+uint32_t RegisterInfoCommon_ppc64le::GetRegisterCount() const {
+ return m_register_info_count;
+}
diff --git a/lldb/source/Register/Common/RegisterInfoCommon_ppc64le.h b/lldb/source/Register/Common/RegisterInfoCommon_ppc64le.h
new file mode 100644
index 00000000000000..62a020c16e7c39
--- /dev/null
+++ b/lldb/source/Register/Common/RegisterInfoCommon_ppc64le.h
@@ -0,0 +1,31 @@
+//===-- RegisterInfoCommon_ppc64le.h -----------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLDB_SOURCE_REGISTER_COMMON_REGISTERINFOCOMMON_PPC64LE_H
+#define LLDB_SOURCE_REGISTER_COMMON_REGISTERINFOCOMMON_PPC64LE_H
+
+#include "Register/RegisterInfoInterface.h"
+#include "lldb/Target/RegisterContext.h"
+#include "lldb/lldb-private.h"
+
+class RegisterInfoCommon_ppc64le : public lldb_private::RegisterInfoInterface {
+public:
+ RegisterInfoCommon_ppc64le(const lldb_private::ArchSpec &target_arch);
+
+ size_t GetGPRSize() const override;
+
+ const lldb_private::RegisterInfo *GetRegisterInfo() const override;
+
+ uint32_t GetRegisterCount() const override;
+
+private:
+ const lldb_private::RegisterInfo *m_register_info_p;
+ uint32_t m_register_info_count;
+};
+
+#endif
diff --git a/lldb/source/Register/Common/RegisterInfoCommon_riscv32.cpp b/lldb/source/Register/Common/RegisterInfoCommon_riscv32.cpp
new file mode 100644
index 00000000000000..558acff325af8e
--- /dev/null
+++ b/lldb/source/Register/Common/RegisterInfoCommon_riscv32.cpp
@@ -0,0 +1,142 @@
+//===-- RegisterInfoCommon_riscv32.cpp -------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===---------------------------------------------------------------------===//
+
+#include "Register/Common/RegisterInfoCommon_riscv32.h"
+#include "lldb/Utility/Flags.h"
+#include "lldb/lldb-defines.h"
+#include "llvm/Support/Compiler.h"
+
+#include <cassert>
+#include <stddef.h>
+
+#define GPR_OFFSET(idx) ((idx) * 4 + 0)
+#define FPR_OFFSET(idx) ((idx) * 4 + sizeof(RegisterInfoCommon_riscv32::GPR))
+
+#define REG_CONTEXT_SIZE \
+ (sizeof(RegisterInfoCommon_riscv32::GPR) + \
+ sizeof(RegisterInfoCommon_riscv32::FPR))
+
+#define DECLARE_REGISTER_INFOS_RISCV32_STRUCT
+#include "Register/Arch/RegisterInfos_riscv32.h"
+#undef DECLARE_REGISTER_INFOS_RISCV32_STRUCT
+
+const lldb_private::RegisterInfo *RegisterInfoCommon_riscv32::GetRegisterInfoPtr(
+ const lldb_private::ArchSpec &target_arch) {
+ switch (target_arch.GetMachine()) {
+ case llvm::Triple::riscv32:
+ return g_register_infos_riscv32_le;
+ default:
+ assert(false && "Unhandled target architecture.");
+ return nullptr;
+ }
+}
+
+uint32_t RegisterInfoCommon_riscv32::GetRegisterInfoCount(
+ const lldb_private::ArchSpec &target_arch) {
+ switch (target_arch.GetMachine()) {
+ case llvm::Triple::riscv32:
+ return static_cast<uint32_t>(sizeof(g_register_infos_riscv32_le) /
+ sizeof(g_register_infos_riscv32_le[0]));
+ default:
+ assert(false && "Unhandled target architecture.");
+ return 0;
+ }
+}
+
+// Number of register sets provided by this context.
+enum {
+ k_num_gpr_registers = gpr_last_riscv - gpr_first_riscv + 1,
+ k_num_fpr_registers = fpr_last_riscv - fpr_first_riscv + 1,
+ k_num_register_sets = 2
+};
+
+// RISC-V32 general purpose registers.
+static const uint32_t g_gpr_regnums_riscv32[] = {
+ gpr_pc_riscv, gpr_ra_riscv, gpr_sp_riscv, gpr_x3_riscv,
+ gpr_x4_riscv, gpr_x5_riscv, gpr_x6_riscv, gpr_x7_riscv,
+ gpr_fp_riscv, gpr_x9_riscv, gpr_x10_riscv, gpr_x11_riscv,
+ gpr_x12_riscv, gpr_x13_riscv, gpr_x14_riscv, gpr_x15_riscv,
+ gpr_x16_riscv, gpr_x17_riscv, gpr_x18_riscv, gpr_x19_riscv,
+ gpr_x20_riscv, gpr_x21_riscv, gpr_x22_riscv, gpr_x23_riscv,
+ gpr_x24_riscv, gpr_x25_riscv, gpr_x26_riscv, gpr_x27_riscv,
+ gpr_x28_riscv, gpr_x29_riscv, gpr_x30_riscv, gpr_x31_riscv,
+ gpr_x0_riscv, LLDB_INVALID_REGNUM};
+
+static_assert(((sizeof g_gpr_regnums_riscv32 /
+ sizeof g_gpr_regnums_riscv32[0]) -
+ 1) == k_num_gpr_registers,
+ "g_gpr_regnums_riscv32 has wrong number of register infos");
+
+// RISC-V32 floating point registers.
+static const uint32_t g_fpr_regnums_riscv32[] = {
+ fpr_f0_riscv, fpr_f1_riscv, fpr_f2_riscv, fpr_f3_riscv,
+ fpr_f4_riscv, fpr_f5_riscv, fpr_f6_riscv, fpr_f7_riscv,
+ fpr_f8_riscv, fpr_f9_riscv, fpr_f10_riscv, fpr_f11_riscv,
+ fpr_f12_riscv, fpr_f13_riscv, fpr_f14_riscv, fpr_f15_riscv,
+ fpr_f16_riscv, fpr_f17_riscv, fpr_f18_riscv, fpr_f19_riscv,
+ fpr_f20_riscv, fpr_f21_riscv, fpr_f22_riscv, fpr_f23_riscv,
+ fpr_f24_riscv, fpr_f25_riscv, fpr_f26_riscv, fpr_f27_riscv,
+ fpr_f28_riscv, fpr_f29_riscv, fpr_f30_riscv, fpr_f31_riscv,
+ fpr_fcsr_riscv, LLDB_INVALID_REGNUM};
+
+static_assert(((sizeof g_fpr_regnums_riscv32 /
+ sizeof g_fpr_regnums_riscv32[0]) -
+ 1) == k_num_fpr_registers,
+ "g_fpr_regnums_riscv32 has wrong number of register infos");
+
+// Register sets for RISC-V32.
+static const lldb_private::RegisterSet g_reg_sets_riscv32[k_num_register_sets] =
+ {{"General Purpose Registers", "gpr", k_num_gpr_registers,
+ g_gpr_regnums_riscv32},
+ {"Floating Point Registers", "fpr", k_num_fpr_registers,
+ g_fpr_regnums_riscv32}};
+
+RegisterInfoCommon_riscv32::RegisterInfoCommon_riscv32(
+ const lldb_private::ArchSpec &target_arch, lldb_private::Flags opt_regsets)
+ : lldb_private::RegisterInfoAndSetInterface(target_arch),
+ m_register_info_p(GetRegisterInfoPtr(target_arch)),
+ m_register_info_count(GetRegisterInfoCount(target_arch)),
+ m_opt_regsets(opt_regsets) {}
+
+uint32_t RegisterInfoCommon_riscv32::GetRegisterCount() const {
+ return m_register_info_count;
+}
+
+size_t RegisterInfoCommon_riscv32::GetGPRSize() const {
+ return sizeof(struct RegisterInfoCommon_riscv32::GPR);
+}
+
+size_t RegisterInfoCommon_riscv32::GetFPRSize() const {
+ return sizeof(struct RegisterInfoCommon_riscv32::FPR);
+}
+
+const lldb_private::RegisterInfo *
+RegisterInfoCommon_riscv32::GetRegisterInfo() const {
+ return m_register_info_p;
+}
+
+size_t RegisterInfoCommon_riscv32::GetRegisterSetCount() const {
+ return k_num_register_sets;
+}
+
+size_t RegisterInfoCommon_riscv32::GetRegisterSetFromRegisterIndex(
+ uint32_t reg_index) const {
+ // coverity[unsigned_compare]
+ if (reg_index >= gpr_first_riscv && reg_index <= gpr_last_riscv)
+ return eRegsetMaskDefault;
+ if (reg_index >= fpr_first_riscv && reg_index <= fpr_last_riscv)
+ return eRegsetMaskFP;
+ return LLDB_INVALID_REGNUM;
+}
+
+const lldb_private::RegisterSet *
+RegisterInfoCommon_riscv32::GetRegisterSet(size_t set_index) const {
+ if (set_index < GetRegisterSetCount())
+ return &g_reg_sets_riscv32[set_index];
+ return nullptr;
+}
diff --git a/lldb/source/Register/Common/RegisterInfoCommon_riscv32.h b/lldb/source/Register/Common/RegisterInfoCommon_riscv32.h
new file mode 100644
index 00000000000000..74363b169a34f0
--- /dev/null
+++ b/lldb/source/Register/Common/RegisterInfoCommon_riscv32.h
@@ -0,0 +1,71 @@
+//===-- RegisterInfoCommon_riscv32.h -----------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLDB_SOURCE_REGISTER_COMMON_REGISTERINFOCOMMON_RISCV32_H
+#define LLDB_SOURCE_REGISTER_COMMON_REGISTERINFOCOMMON_RISCV32_H
+
+#include "Register/RegisterInfoAndSetInterface.h"
+#include "lldb/Target/RegisterContext.h"
+#include "lldb/Utility/Flags.h"
+#include "lldb/lldb-private.h"
+
+#include <map>
+
+class RegisterInfoCommon_riscv32
+ : public lldb_private::RegisterInfoAndSetInterface {
+public:
+ static const lldb_private::RegisterInfo *
+ GetRegisterInfoPtr(const lldb_private::ArchSpec &target_arch);
+ static uint32_t
+ GetRegisterInfoCount(const lldb_private::ArchSpec &target_arch);
+
+public:
+ // RISC-V32 register set mask value
+ enum {
+ eRegsetMaskDefault = 0,
+ eRegsetMaskFP = 1,
+ eRegsetMaskAll = -1,
+ };
+
+ struct GPR {
+ // gpr[0] is pc, not x0, which is the zero register.
+ uint32_t gpr[32];
+ };
+
+ struct FPR {
+ uint32_t fpr[32];
+ uint32_t fcsr;
+ };
+
+ RegisterInfoCommon_riscv32(const lldb_private::ArchSpec &target_arch,
+ lldb_private::Flags flags);
+
+ size_t GetGPRSize() const override;
+
+ size_t GetFPRSize() const override;
+
+ const lldb_private::RegisterInfo *GetRegisterInfo() const override;
+
+ uint32_t GetRegisterCount() const override;
+
+ const lldb_private::RegisterSet *
+ GetRegisterSet(size_t reg_set) const override;
+
+ size_t GetRegisterSetCount() const override;
+
+ size_t GetRegisterSetFromRegisterIndex(uint32_t reg_index) const override;
+
+ bool IsFPPresent() const { return m_opt_regsets.AnySet(eRegsetMaskFP); }
+
+private:
+ const lldb_private::RegisterInfo *m_register_info_p;
+ uint32_t m_register_info_count;
+ lldb_private::Flags m_opt_regsets;
+};
+
+#endif
diff --git a/lldb/source/Register/Common/RegisterInfoCommon_riscv64.cpp b/lldb/source/Register/Common/RegisterInfoCommon_riscv64.cpp
new file mode 100644
index 00000000000000..8f7e50b93e23ed
--- /dev/null
+++ b/lldb/source/Register/Common/RegisterInfoCommon_riscv64.cpp
@@ -0,0 +1,149 @@
+//===-- RegisterInfoCommon_riscv64.cpp -------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===---------------------------------------------------------------------===//
+
+#include "Register/Common/RegisterInfoCommon_riscv64.h"
+#include "lldb/Utility/Flags.h"
+#include "lldb/lldb-defines.h"
+#include "llvm/Support/Compiler.h"
+
+#include <cassert>
+#include <stddef.h>
+
+#define GPR_OFFSET(idx) ((idx)*8 + 0)
+#define FPR_OFFSET(idx) ((idx)*8 + sizeof(RegisterInfoCommon_riscv64::GPR))
+
+#define DECLARE_REGISTER_INFOS_RISCV64_STRUCT
+#include "Register/Arch/RegisterInfos_riscv64.h"
+#undef DECLARE_REGISTER_INFOS_RISCV64_STRUCT
+
+// Number of register sets provided by this context.
+enum {
+ k_num_gpr_registers = gpr_last_riscv - gpr_first_riscv + 1,
+ k_num_fpr_registers = fpr_last_riscv - fpr_first_riscv + 1,
+ k_num_register_sets_default = 1
+};
+
+// RISC-V64 general purpose registers.
+static const uint32_t g_gpr_regnums_riscv64[] = {
+ gpr_pc_riscv, gpr_ra_riscv, gpr_sp_riscv, gpr_x3_riscv,
+ gpr_x4_riscv, gpr_x5_riscv, gpr_x6_riscv, gpr_x7_riscv,
+ gpr_fp_riscv, gpr_x9_riscv, gpr_x10_riscv, gpr_x11_riscv,
+ gpr_x12_riscv, gpr_x13_riscv, gpr_x14_riscv, gpr_x15_riscv,
+ gpr_x16_riscv, gpr_x17_riscv, gpr_x18_riscv, gpr_x19_riscv,
+ gpr_x20_riscv, gpr_x21_riscv, gpr_x22_riscv, gpr_x23_riscv,
+ gpr_x24_riscv, gpr_x25_riscv, gpr_x26_riscv, gpr_x27_riscv,
+ gpr_x28_riscv, gpr_x29_riscv, gpr_x30_riscv, gpr_x31_riscv,
+ gpr_x0_riscv, LLDB_INVALID_REGNUM};
+
+static_assert(((sizeof g_gpr_regnums_riscv64 /
+ sizeof g_gpr_regnums_riscv64[0]) -
+ 1) == k_num_gpr_registers,
+ "g_gpr_regnums_riscv64 has wrong number of register infos");
+
+// Register sets for RISC-V64.
+static const lldb_private::RegisterSet g_reg_set_gpr_riscv64 = {
+ "General Purpose Registers", "gpr", k_num_gpr_registers,
+ g_gpr_regnums_riscv64};
+static const lldb_private::RegisterSet g_reg_set_fpr_riscv64 = {
+ "Floating Point Registers", "fpr", k_num_fpr_registers, nullptr};
+
+RegisterInfoCommon_riscv64::RegisterInfoCommon_riscv64(
+ const lldb_private::ArchSpec &target_arch, lldb_private::Flags opt_regsets)
+ : lldb_private::RegisterInfoAndSetInterface(target_arch),
+ m_opt_regsets(opt_regsets) {
+ switch (target_arch.GetMachine()) {
+ case llvm::Triple::riscv64: {
+ // By-default considering RISC-V has only GPR.
+ // Other register sets could be enabled optionally by opt_regsets.
+ AddRegSetGP();
+
+ if (m_opt_regsets.AnySet(eRegsetMaskFP))
+ AddRegSetFP();
+
+ break;
+ }
+ default:
+ assert(false && "Unhandled target architecture.");
+ }
+}
+
+void RegisterInfoCommon_riscv64::AddRegSetGP() {
+ m_register_infos.resize(k_num_gpr_registers);
+ memcpy(&m_register_infos[0], g_register_infos_riscv64_gpr,
+ sizeof(g_register_infos_riscv64_gpr));
+ m_register_sets.push_back(g_reg_set_gpr_riscv64);
+
+ m_per_regset_regnum_range[GPRegSet] =
+ std::make_pair(gpr_first_riscv, m_register_infos.size());
+}
+
+void RegisterInfoCommon_riscv64::AddRegSetFP() {
+ const uint32_t register_info_count = m_register_infos.size();
+ const uint32_t register_set_count = m_register_sets.size();
+
+ // Filling m_register_infos.
+ // For FPR case we do not need to correct register offsets and kinds
+ // while for other further cases (like VPR), register offset/kind
+ // should be started counting from the last one in previously added
+ // regset. This is needed for the case e.g. when architecture has GPR + VPR
+ // sets only.
+ m_register_infos.resize(register_info_count + k_num_fpr_registers);
+ memcpy(&m_register_infos[register_info_count], g_register_infos_riscv64_fpr,
+ sizeof(g_register_infos_riscv64_fpr));
+
+ // Filling m_register_sets with enabled register set
+ for (uint32_t i = 0; i < k_num_fpr_registers; i++)
+ m_fp_regnum_collection.push_back(register_info_count + i);
+ m_register_sets.push_back(g_reg_set_fpr_riscv64);
+ m_register_sets.back().registers = m_fp_regnum_collection.data();
+
+ m_per_regset_regnum_range[register_set_count] =
+ std::make_pair(register_info_count, m_register_infos.size());
+}
+
+uint32_t RegisterInfoCommon_riscv64::GetRegisterCount() const {
+ return m_register_infos.size();
+}
+
+size_t RegisterInfoCommon_riscv64::GetGPRSize() const {
+ return sizeof(struct RegisterInfoCommon_riscv64::GPR);
+}
+
+size_t RegisterInfoCommon_riscv64::GetFPRSize() const {
+ return sizeof(struct RegisterInfoCommon_riscv64::FPR);
+}
+
+const lldb_private::RegisterInfo *
+RegisterInfoCommon_riscv64::GetRegisterInfo() const {
+ return m_register_infos.data();
+}
+
+size_t RegisterInfoCommon_riscv64::GetRegisterSetCount() const {
+ return m_register_sets.size();
+}
+
+size_t RegisterInfoCommon_riscv64::GetRegisterSetFromRegisterIndex(
+ uint32_t reg_index) const {
+ for (const auto ®set_range : m_per_regset_regnum_range) {
+ if (reg_index >= regset_range.second.first &&
+ reg_index < regset_range.second.second)
+ return regset_range.first;
+ }
+ return LLDB_INVALID_REGNUM;
+}
+
+bool RegisterInfoCommon_riscv64::IsFPReg(unsigned reg) const {
+ return llvm::is_contained(m_fp_regnum_collection, reg);
+}
+
+const lldb_private::RegisterSet *
+RegisterInfoCommon_riscv64::GetRegisterSet(size_t set_index) const {
+ if (set_index < GetRegisterSetCount())
+ return &m_register_sets[set_index];
+ return nullptr;
+}
diff --git a/lldb/source/Register/Common/RegisterInfoCommon_riscv64.h b/lldb/source/Register/Common/RegisterInfoCommon_riscv64.h
new file mode 100644
index 00000000000000..a46874fa7f42d2
--- /dev/null
+++ b/lldb/source/Register/Common/RegisterInfoCommon_riscv64.h
@@ -0,0 +1,86 @@
+//===-- RegisterInfoCommon_riscv64.h -----------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLDB_SOURCE_REGISTER_COMMON_REGISTERINFOCOMMON_RISCV64_H
+#define LLDB_SOURCE_REGISTER_COMMON_REGISTERINFOCOMMON_RISCV64_H
+
+#include "Register/RegisterInfoAndSetInterface.h"
+#include "lldb/Target/RegisterContext.h"
+#include "lldb/Utility/Flags.h"
+#include "lldb/lldb-private.h"
+#include <map>
+
+class RegisterInfoCommon_riscv64
+ : public lldb_private::RegisterInfoAndSetInterface {
+public:
+ enum { GPRegSet = 0 };
+
+ // RISC-V64 register set mask value
+ enum {
+ eRegsetMaskDefault = 0,
+ eRegsetMaskFP = 1,
+ eRegsetMaskAll = -1,
+ };
+
+ struct GPR {
+ // note: gpr[0] is pc, not x0
+ uint64_t gpr[32];
+ };
+
+ struct FPR {
+ uint64_t fpr[32];
+ uint32_t fcsr;
+ };
+
+ struct VPR {
+ // The size should be VLEN*32 in bits, but we don't have VLEN here.
+ void *vpr;
+ };
+
+ RegisterInfoCommon_riscv64(const lldb_private::ArchSpec &target_arch,
+ lldb_private::Flags opt_regsets);
+
+ void AddRegSetGP();
+
+ void AddRegSetFP();
+
+ size_t GetGPRSize() const override;
+
+ size_t GetFPRSize() const override;
+
+ const lldb_private::RegisterInfo *GetRegisterInfo() const override;
+
+ uint32_t GetRegisterCount() const override;
+
+ const lldb_private::RegisterSet *
+ GetRegisterSet(size_t reg_set) const override;
+
+ size_t GetRegisterSetCount() const override;
+
+ size_t GetRegisterSetFromRegisterIndex(uint32_t reg_index) const override;
+
+ bool IsFPPresent() const { return m_opt_regsets.AnySet(eRegsetMaskFP); }
+
+ bool IsFPReg(unsigned reg) const;
+
+private:
+ std::vector<lldb_private::RegisterInfo> m_register_infos;
+
+ std::vector<lldb_private::RegisterSet> m_register_sets;
+
+ // Contains pair of [start, end] register numbers of a register set with start
+ // and end included.
+ std::map<uint32_t, std::pair<uint32_t, uint32_t>> m_per_regset_regnum_range;
+
+ // Register collections to be stored as reference for m_register_sets items
+ std::vector<uint32_t> m_fp_regnum_collection;
+
+ lldb_private::Flags m_opt_regsets;
+};
+
+#endif
diff --git a/lldb/source/Plugins/Process/Utility/RegisterTypeDetector_arm64.cpp b/lldb/source/Register/Common/RegisterTypeDetector_arm64.cpp
similarity index 99%
rename from lldb/source/Plugins/Process/Utility/RegisterTypeDetector_arm64.cpp
rename to lldb/source/Register/Common/RegisterTypeDetector_arm64.cpp
index ffeb6e99aabf88..7496ab48e08912 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterTypeDetector_arm64.cpp
+++ b/lldb/source/Register/Common/RegisterTypeDetector_arm64.cpp
@@ -6,7 +6,7 @@
//
//===----------------------------------------------------------------------===//
-#include "RegisterTypeDetector_arm64.h"
+#include "Register/Common/RegisterTypeDetector_arm64.h"
#include "lldb/Utility/RegisterTypeFlags.h"
#include <functional>
diff --git a/lldb/source/Plugins/Process/Utility/RegisterTypeDetector_arm64.h b/lldb/source/Register/Common/RegisterTypeDetector_arm64.h
similarity index 96%
rename from lldb/source/Plugins/Process/Utility/RegisterTypeDetector_arm64.h
rename to lldb/source/Register/Common/RegisterTypeDetector_arm64.h
index a5b39a78b92f39..3d2dd502b94c32 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterTypeDetector_arm64.h
+++ b/lldb/source/Register/Common/RegisterTypeDetector_arm64.h
@@ -6,8 +6,8 @@
//
//===----------------------------------------------------------------------===//
-#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERTYPEDETECTOR_ARM64_H
-#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERTYPEDETECTOR_ARM64_H
+#ifndef LLDB_SOURCE_REGISTER_COMMON_REGISTERTYPEDETECTOR_ARM64_H
+#define LLDB_SOURCE_REGISTER_COMMON_REGISTERTYPEDETECTOR_ARM64_H
#include "lldb/Utility/RegisterInfo.h"
#include "lldb/Utility/RegisterType.h"
@@ -127,4 +127,4 @@ class Arm64RegisterTypeDetector {
} // namespace lldb_private
-#endif // LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERTYPEDETECTOR_ARM64_H
+#endif // LLDB_SOURCE_REGISTER_COMMON_REGISTERTYPEDETECTOR_ARM64_H
diff --git a/lldb/source/Register/FreeBSD/RegisterInfoFreeBSD_i386.cpp b/lldb/source/Register/FreeBSD/RegisterInfoFreeBSD_i386.cpp
new file mode 100644
index 00000000000000..1410a98160c7f3
--- /dev/null
+++ b/lldb/source/Register/FreeBSD/RegisterInfoFreeBSD_i386.cpp
@@ -0,0 +1,85 @@
+//===-- RegisterInfoFreeBSD_i386.cpp -----------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===---------------------------------------------------------------------===//
+
+#include "Register/FreeBSD/RegisterInfoFreeBSD_i386.h"
+#include "Register/Arch/RegisterContext_x86.h"
+#include "Register/Arch/lldb-x86-register-enums.h"
+#include "lldb/lldb-defines.h"
+
+using namespace lldb_private;
+using namespace lldb;
+
+// https://cgit.freebsd.org/src/tree/sys/x86/include/reg.h?h=stable/14
+struct GPR {
+ uint32_t fs;
+ uint32_t es;
+ uint32_t ds;
+ uint32_t edi;
+ uint32_t esi;
+ uint32_t ebp;
+ uint32_t isp;
+ uint32_t ebx;
+ uint32_t edx;
+ uint32_t ecx;
+ uint32_t eax;
+ uint32_t trapno;
+ uint32_t err;
+ uint32_t eip;
+ uint32_t cs;
+ uint32_t eflags;
+ uint32_t esp;
+ uint32_t ss;
+ uint32_t gs;
+};
+
+struct DBG {
+ uint32_t dr[8]; /* debug registers */
+ /* Index 0-3: debug address registers */
+ /* Index 4-5: reserved */
+ /* Index 6: debug status */
+ /* Index 7: debug control */
+};
+
+using FPR_i386 = FXSAVE;
+
+struct UserArea {
+ GPR gpr;
+ FPR_i386 i387;
+ DBG dbg;
+};
+
+#define DR_SIZE sizeof(uint32_t)
+#define DR_OFFSET(reg_index) \
+ (LLVM_EXTENSION offsetof(UserArea, dbg) + \
+ LLVM_EXTENSION offsetof(DBG, dr[reg_index]))
+
+// Include RegisterInfos_i386 to declare our g_register_infos_i386 structure.
+#define DECLARE_REGISTER_INFOS_I386_STRUCT
+#include "Register/Arch/RegisterInfos_i386.h"
+#undef DECLARE_REGISTER_INFOS_I386_STRUCT
+
+RegisterInfoFreeBSD_i386::RegisterInfoFreeBSD_i386(
+ const ArchSpec &target_arch)
+ : RegisterInfoInterface(target_arch) {}
+
+size_t RegisterInfoFreeBSD_i386::GetGPRSize() const { return sizeof(GPR); }
+
+const RegisterInfo *RegisterInfoFreeBSD_i386::GetRegisterInfo() const {
+ switch (GetTargetArchitecture().GetMachine()) {
+ case llvm::Triple::x86:
+ return g_register_infos_i386;
+ default:
+ assert(false && "Unhandled target architecture.");
+ return nullptr;
+ }
+}
+
+uint32_t RegisterInfoFreeBSD_i386::GetRegisterCount() const {
+ return static_cast<uint32_t>(sizeof(g_register_infos_i386) /
+ sizeof(g_register_infos_i386[0]));
+}
diff --git a/lldb/source/Register/FreeBSD/RegisterInfoFreeBSD_i386.h b/lldb/source/Register/FreeBSD/RegisterInfoFreeBSD_i386.h
new file mode 100644
index 00000000000000..8318ea2b2bce76
--- /dev/null
+++ b/lldb/source/Register/FreeBSD/RegisterInfoFreeBSD_i386.h
@@ -0,0 +1,25 @@
+//===-- RegisterInfoFreeBSD_i386.h ---------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLDB_SOURCE_REGISTER_FREEBSD_REGISTERINFOFREEBSD_I386_H
+#define LLDB_SOURCE_REGISTER_FREEBSD_REGISTERINFOFREEBSD_I386_H
+
+#include "Register/RegisterInfoInterface.h"
+
+class RegisterInfoFreeBSD_i386 : public lldb_private::RegisterInfoInterface {
+public:
+ RegisterInfoFreeBSD_i386(const lldb_private::ArchSpec &target_arch);
+
+ size_t GetGPRSize() const override;
+
+ const lldb_private::RegisterInfo *GetRegisterInfo() const override;
+
+ uint32_t GetRegisterCount() const override;
+};
+
+#endif
diff --git a/lldb/source/Register/FreeBSD/RegisterInfoFreeBSD_powerpc.cpp b/lldb/source/Register/FreeBSD/RegisterInfoFreeBSD_powerpc.cpp
new file mode 100644
index 00000000000000..7213723fdfc1c0
--- /dev/null
+++ b/lldb/source/Register/FreeBSD/RegisterInfoFreeBSD_powerpc.cpp
@@ -0,0 +1,233 @@
+//===-- RegisterInfoFreeBSD_powerpc.cpp --------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===---------------------------------------------------------------------===//
+
+#include "Register/FreeBSD/RegisterInfoFreeBSD_powerpc.h"
+#include "Plugins/Process/Utility/RegisterContextPOSIX_powerpc.h"
+#include <vector>
+
+using namespace lldb_private;
+using namespace lldb;
+
+// https://cgit.freebsd.org/src/tree/sys/powerpc/include/reg.h
+typedef struct _GPR64 {
+ uint64_t r0;
+ uint64_t r1;
+ uint64_t r2;
+ uint64_t r3;
+ uint64_t r4;
+ uint64_t r5;
+ uint64_t r6;
+ uint64_t r7;
+ uint64_t r8;
+ uint64_t r9;
+ uint64_t r10;
+ uint64_t r11;
+ uint64_t r12;
+ uint64_t r13;
+ uint64_t r14;
+ uint64_t r15;
+ uint64_t r16;
+ uint64_t r17;
+ uint64_t r18;
+ uint64_t r19;
+ uint64_t r20;
+ uint64_t r21;
+ uint64_t r22;
+ uint64_t r23;
+ uint64_t r24;
+ uint64_t r25;
+ uint64_t r26;
+ uint64_t r27;
+ uint64_t r28;
+ uint64_t r29;
+ uint64_t r30;
+ uint64_t r31;
+ uint64_t lr;
+ uint64_t cr;
+ uint64_t xer;
+ uint64_t ctr;
+ uint64_t pc;
+} GPR64;
+
+typedef struct _GPR32 {
+ uint32_t r0;
+ uint32_t r1;
+ uint32_t r2;
+ uint32_t r3;
+ uint32_t r4;
+ uint32_t r5;
+ uint32_t r6;
+ uint32_t r7;
+ uint32_t r8;
+ uint32_t r9;
+ uint32_t r10;
+ uint32_t r11;
+ uint32_t r12;
+ uint32_t r13;
+ uint32_t r14;
+ uint32_t r15;
+ uint32_t r16;
+ uint32_t r17;
+ uint32_t r18;
+ uint32_t r19;
+ uint32_t r20;
+ uint32_t r21;
+ uint32_t r22;
+ uint32_t r23;
+ uint32_t r24;
+ uint32_t r25;
+ uint32_t r26;
+ uint32_t r27;
+ uint32_t r28;
+ uint32_t r29;
+ uint32_t r30;
+ uint32_t r31;
+ uint32_t lr;
+ uint32_t cr;
+ uint32_t xer;
+ uint32_t ctr;
+ uint32_t pc;
+} GPR32;
+
+typedef struct _FPR {
+ uint64_t f0;
+ uint64_t f1;
+ uint64_t f2;
+ uint64_t f3;
+ uint64_t f4;
+ uint64_t f5;
+ uint64_t f6;
+ uint64_t f7;
+ uint64_t f8;
+ uint64_t f9;
+ uint64_t f10;
+ uint64_t f11;
+ uint64_t f12;
+ uint64_t f13;
+ uint64_t f14;
+ uint64_t f15;
+ uint64_t f16;
+ uint64_t f17;
+ uint64_t f18;
+ uint64_t f19;
+ uint64_t f20;
+ uint64_t f21;
+ uint64_t f22;
+ uint64_t f23;
+ uint64_t f24;
+ uint64_t f25;
+ uint64_t f26;
+ uint64_t f27;
+ uint64_t f28;
+ uint64_t f29;
+ uint64_t f30;
+ uint64_t f31;
+ uint64_t fpscr;
+} FPR;
+
+typedef struct _VMX {
+ uint32_t v0[4];
+ uint32_t v1[4];
+ uint32_t v2[4];
+ uint32_t v3[4];
+ uint32_t v4[4];
+ uint32_t v5[4];
+ uint32_t v6[4];
+ uint32_t v7[4];
+ uint32_t v8[4];
+ uint32_t v9[4];
+ uint32_t v10[4];
+ uint32_t v11[4];
+ uint32_t v12[4];
+ uint32_t v13[4];
+ uint32_t v14[4];
+ uint32_t v15[4];
+ uint32_t v16[4];
+ uint32_t v17[4];
+ uint32_t v18[4];
+ uint32_t v19[4];
+ uint32_t v20[4];
+ uint32_t v21[4];
+ uint32_t v22[4];
+ uint32_t v23[4];
+ uint32_t v24[4];
+ uint32_t v25[4];
+ uint32_t v26[4];
+ uint32_t v27[4];
+ uint32_t v28[4];
+ uint32_t v29[4];
+ uint32_t v30[4];
+ uint32_t v31[4];
+ uint32_t pad[2];
+ uint32_t vrsave;
+ uint32_t vscr;
+} VMX;
+
+// Include RegisterInfos_powerpc to declare our g_register_infos_powerpc
+// structure.
+#define DECLARE_REGISTER_INFOS_POWERPC_STRUCT
+#include "Register/Arch/RegisterInfos_powerpc.h"
+#undef DECLARE_REGISTER_INFOS_POWERPC_STRUCT
+
+RegisterInfoFreeBSD_powerpc::RegisterInfoFreeBSD_powerpc(
+ const ArchSpec &target_arch)
+ : RegisterInfoInterface(target_arch) {}
+
+RegisterInfoFreeBSD_powerpc::~RegisterInfoFreeBSD_powerpc() = default;
+
+size_t RegisterInfoFreeBSD_powerpc::GetGPRSize() const {
+ // This is an 'abstract' base, so no GPR struct.
+ return 0;
+}
+
+const RegisterInfo *RegisterInfoFreeBSD_powerpc::GetRegisterInfo() const {
+ llvm_unreachable("Abstract class!");
+ return nullptr;
+}
+
+uint32_t RegisterInfoFreeBSD_powerpc::GetRegisterCount() const { return 0; }
+
+RegisterInfoFreeBSD_powerpc32::RegisterInfoFreeBSD_powerpc32(
+ const ArchSpec &target_arch)
+ : RegisterInfoFreeBSD_powerpc(target_arch) {}
+
+RegisterInfoFreeBSD_powerpc32::~RegisterInfoFreeBSD_powerpc32() = default;
+
+size_t RegisterInfoFreeBSD_powerpc32::GetGPRSize() const {
+ return sizeof(GPR32);
+}
+
+const RegisterInfo *RegisterInfoFreeBSD_powerpc32::GetRegisterInfo() const {
+ return g_register_infos_powerpc32;
+}
+
+uint32_t RegisterInfoFreeBSD_powerpc32::GetRegisterCount() const {
+ return static_cast<uint32_t>(sizeof(g_register_infos_powerpc32) /
+ sizeof(g_register_infos_powerpc32[0]));
+}
+
+RegisterInfoFreeBSD_powerpc64::RegisterInfoFreeBSD_powerpc64(
+ const ArchSpec &target_arch)
+ : RegisterInfoFreeBSD_powerpc(target_arch) {}
+
+RegisterInfoFreeBSD_powerpc64::~RegisterInfoFreeBSD_powerpc64() = default;
+
+size_t RegisterInfoFreeBSD_powerpc64::GetGPRSize() const {
+ return sizeof(GPR64);
+}
+
+const RegisterInfo *RegisterInfoFreeBSD_powerpc64::GetRegisterInfo() const {
+ if (GetTargetArchitecture().GetMachine() == llvm::Triple::ppc)
+ return g_register_infos_powerpc64_32;
+ return g_register_infos_powerpc64;
+}
+
+uint32_t RegisterInfoFreeBSD_powerpc64::GetRegisterCount() const {
+ return static_cast<uint32_t>(sizeof(g_register_infos_powerpc64) /
+ sizeof(g_register_infos_powerpc64[0]));
+}
diff --git a/lldb/source/Register/FreeBSD/RegisterInfoFreeBSD_powerpc.h b/lldb/source/Register/FreeBSD/RegisterInfoFreeBSD_powerpc.h
new file mode 100644
index 00000000000000..2703b7ab88fbc7
--- /dev/null
+++ b/lldb/source/Register/FreeBSD/RegisterInfoFreeBSD_powerpc.h
@@ -0,0 +1,52 @@
+//===-- RegisterInfoFreeBSD_powerpc.h -------------------------*- C++
+//-*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLDB_SOURCE_REGISTER_FREEBSD_REGISTERINFOFREEBSD_POWERPC_H
+#define LLDB_SOURCE_REGISTER_FREEBSD_REGISTERINFOFREEBSD_POWERPC_H
+
+#include "Register/RegisterInfoInterface.h"
+
+class RegisterInfoFreeBSD_powerpc
+ : public lldb_private::RegisterInfoInterface {
+public:
+ RegisterInfoFreeBSD_powerpc(const lldb_private::ArchSpec &target_arch);
+ ~RegisterInfoFreeBSD_powerpc() override;
+
+ size_t GetGPRSize() const override;
+
+ const lldb_private::RegisterInfo *GetRegisterInfo() const override;
+
+ uint32_t GetRegisterCount() const override;
+};
+
+class RegisterInfoFreeBSD_powerpc32 : public RegisterInfoFreeBSD_powerpc {
+public:
+ RegisterInfoFreeBSD_powerpc32(const lldb_private::ArchSpec &target_arch);
+ ~RegisterInfoFreeBSD_powerpc32() override;
+
+ size_t GetGPRSize() const override;
+
+ const lldb_private::RegisterInfo *GetRegisterInfo() const override;
+
+ uint32_t GetRegisterCount() const override;
+};
+
+class RegisterInfoFreeBSD_powerpc64 : public RegisterInfoFreeBSD_powerpc {
+public:
+ RegisterInfoFreeBSD_powerpc64(const lldb_private::ArchSpec &target_arch);
+ ~RegisterInfoFreeBSD_powerpc64() override;
+
+ size_t GetGPRSize() const override;
+
+ const lldb_private::RegisterInfo *GetRegisterInfo() const override;
+
+ uint32_t GetRegisterCount() const override;
+};
+
+#endif // LLDB_SOURCE_REGISTER_FREEBSD_REGISTERINFOFREEBSD_POWERPC_H
diff --git a/lldb/source/Register/FreeBSD/RegisterInfoFreeBSD_x86_64.cpp b/lldb/source/Register/FreeBSD/RegisterInfoFreeBSD_x86_64.cpp
new file mode 100644
index 00000000000000..bf819f89da8d45
--- /dev/null
+++ b/lldb/source/Register/FreeBSD/RegisterInfoFreeBSD_x86_64.cpp
@@ -0,0 +1,143 @@
+//===-- RegisterInfoFreeBSD_x86_64.cpp ---------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===---------------------------------------------------------------------===//
+
+#include "Register/FreeBSD/RegisterInfoFreeBSD_x86_64.h"
+#include "Register/FreeBSD/RegisterInfoFreeBSD_i386.h"
+#include "Register/Arch/RegisterContext_x86.h"
+#include "Register/Arch/lldb-x86-register-enums.h"
+#include "lldb/lldb-defines.h"
+#include "llvm/Support/Threading.h"
+#include <vector>
+
+using namespace lldb_private;
+using namespace lldb;
+
+// https://cgit.freebsd.org/src/tree/sys/x86/include/reg.h
+typedef struct _GPR {
+ uint64_t r15;
+ uint64_t r14;
+ uint64_t r13;
+ uint64_t r12;
+ uint64_t r11;
+ uint64_t r10;
+ uint64_t r9;
+ uint64_t r8;
+ uint64_t rdi;
+ uint64_t rsi;
+ uint64_t rbp;
+ uint64_t rbx;
+ uint64_t rdx;
+ uint64_t rcx;
+ uint64_t rax;
+ uint32_t trapno;
+ uint16_t fs;
+ uint16_t gs;
+ uint32_t err;
+ uint16_t es;
+ uint16_t ds;
+ uint64_t rip;
+ uint64_t cs;
+ uint64_t rflags;
+ uint64_t rsp;
+ uint64_t ss;
+} GPR;
+
+struct DBG {
+ uint64_t dr[16]; /* debug registers */
+ /* Index 0-3: debug address registers */
+ /* Index 4-5: reserved */
+ /* Index 6: debug status */
+ /* Index 7: debug control */
+ /* Index 8-15: reserved */
+};
+
+struct UserArea {
+ GPR gpr;
+ FPR fpr;
+ DBG dbg;
+};
+
+#define DR_OFFSET(reg_index) \
+ (LLVM_EXTENSION offsetof(UserArea, dbg) + \
+ LLVM_EXTENSION offsetof(DBG, dr[reg_index]))
+
+// Include RegisterInfos_x86_64 to declare our g_register_infos_x86_64
+// structure.
+#define DECLARE_REGISTER_INFOS_X86_64_STRUCT
+#include "Register/Arch/RegisterInfos_x86_64.h"
+#undef DECLARE_REGISTER_INFOS_X86_64_STRUCT
+
+static std::vector<lldb_private::RegisterInfo> &
+GetSharedRegisterInfoVector_i386(const lldb_private::ArchSpec &arch) {
+ static std::vector<lldb_private::RegisterInfo> g_register_infos;
+ static llvm::once_flag g_initialized;
+ llvm::call_once(g_initialized, [&]() {
+ if (g_register_infos.empty()) {
+ // Copy the register information from base class
+ std::unique_ptr<RegisterInfoFreeBSD_i386> reg_interface(
+ new RegisterInfoFreeBSD_i386(arch));
+ const RegisterInfo *base_info = reg_interface->GetRegisterInfo();
+ g_register_infos.insert(g_register_infos.end(), &base_info[0],
+ &base_info[k_num_registers_i386]);
+
+// Include RegisterInfos_x86_64 to update the g_register_infos structure
+// with x86_64 offsets.
+#define UPDATE_REGISTER_INFOS_I386_STRUCT_WITH_X86_64_OFFSETS
+#include "Register/Arch/RegisterInfos_x86_64.h"
+#undef UPDATE_REGISTER_INFOS_I386_STRUCT_WITH_X86_64_OFFSETS
+ }
+ });
+ return g_register_infos;
+}
+
+static const RegisterInfo *
+PrivateGetRegisterInfoPtr(const lldb_private::ArchSpec &target_arch) {
+ switch (target_arch.GetMachine()) {
+ case llvm::Triple::x86:
+ return &GetSharedRegisterInfoVector_i386(target_arch)[0];
+ case llvm::Triple::x86_64:
+ return g_register_infos_x86_64;
+ default:
+ assert(false && "Unhandled target architecture.");
+ return nullptr;
+ }
+}
+
+static uint32_t
+PrivateGetRegisterCount(const lldb_private::ArchSpec &target_arch) {
+ switch (target_arch.GetMachine()) {
+ case llvm::Triple::x86:
+ // This vector should have already been filled.
+ assert(!GetSharedRegisterInfoVector_i386(target_arch).empty() &&
+ "i386 register info vector not filled.");
+ return static_cast<uint32_t>(
+ GetSharedRegisterInfoVector_i386(target_arch).size());
+ case llvm::Triple::x86_64:
+ return static_cast<uint32_t>(sizeof(g_register_infos_x86_64) /
+ sizeof(g_register_infos_x86_64[0]));
+ default:
+ assert(false && "Unhandled target architecture.");
+ return 0;
+ }
+}
+
+RegisterInfoFreeBSD_x86_64::RegisterInfoFreeBSD_x86_64(
+ const ArchSpec &target_arch)
+ : lldb_private::RegisterInfoInterface(target_arch),
+ m_register_info_p(PrivateGetRegisterInfoPtr(target_arch)),
+ m_register_count(PrivateGetRegisterCount(target_arch)) {}
+
+size_t RegisterInfoFreeBSD_x86_64::GetGPRSize() const { return sizeof(GPR); }
+
+const RegisterInfo *RegisterInfoFreeBSD_x86_64::GetRegisterInfo() const {
+ return m_register_info_p;
+}
+
+uint32_t RegisterInfoFreeBSD_x86_64::GetRegisterCount() const {
+ return m_register_count;
+}
diff --git a/lldb/source/Register/FreeBSD/RegisterInfoFreeBSD_x86_64.h b/lldb/source/Register/FreeBSD/RegisterInfoFreeBSD_x86_64.h
new file mode 100644
index 00000000000000..bef4595fe97035
--- /dev/null
+++ b/lldb/source/Register/FreeBSD/RegisterInfoFreeBSD_x86_64.h
@@ -0,0 +1,30 @@
+//===-- RegisterInfoFreeBSD_x86_64.h -------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLDB_SOURCE_REGISTER_FREEBSD_REGISTERINFOFREEBSD_X86_64_H
+#define LLDB_SOURCE_REGISTER_FREEBSD_REGISTERINFOFREEBSD_X86_64_H
+
+#include "Register/RegisterInfoInterface.h"
+
+class RegisterInfoFreeBSD_x86_64
+ : public lldb_private::RegisterInfoInterface {
+public:
+ RegisterInfoFreeBSD_x86_64(const lldb_private::ArchSpec &target_arch);
+
+ size_t GetGPRSize() const override;
+
+ const lldb_private::RegisterInfo *GetRegisterInfo() const override;
+
+ uint32_t GetRegisterCount() const override;
+
+private:
+ const lldb_private::RegisterInfo *m_register_info_p;
+ const uint32_t m_register_count;
+};
+
+#endif
diff --git a/lldb/source/Register/Linux/RegisterInfoLinux_i386.cpp b/lldb/source/Register/Linux/RegisterInfoLinux_i386.cpp
new file mode 100644
index 00000000000000..01cf2621fbb680
--- /dev/null
+++ b/lldb/source/Register/Linux/RegisterInfoLinux_i386.cpp
@@ -0,0 +1,127 @@
+//===-- RegisterInfoLinux_i386.cpp -------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===---------------------------------------------------------------------===//
+
+#include "Register/Linux/RegisterInfoLinux_i386.h"
+#include "Register/Arch/RegisterContext_x86.h"
+#include "Register/Arch/lldb-x86-register-enums.h"
+#include "lldb/lldb-defines.h"
+
+using namespace lldb_private;
+using namespace lldb;
+
+struct GPR {
+ uint32_t ebx;
+ uint32_t ecx;
+ uint32_t edx;
+ uint32_t esi;
+ uint32_t edi;
+ uint32_t ebp;
+ uint32_t eax;
+ uint32_t ds;
+ uint32_t es;
+ uint32_t fs;
+ uint32_t gs;
+ uint32_t orig_eax;
+ uint32_t eip;
+ uint32_t cs;
+ uint32_t eflags;
+ uint32_t esp;
+ uint32_t ss;
+};
+
+struct FPR_i386 {
+ uint16_t fctrl; // FPU Control Word (fcw)
+ uint16_t fstat; // FPU Status Word (fsw)
+ uint16_t ftag; // FPU Tag Word (ftw)
+ uint16_t fop; // Last Instruction Opcode (fop)
+ union {
+ struct {
+ uint64_t fip; // Instruction Pointer
+ uint64_t fdp; // Data Pointer
+ } x86_64;
+ struct {
+ uint32_t fioff; // FPU IP Offset (fip)
+ uint32_t fiseg; // FPU IP Selector (fcs)
+ uint32_t fooff; // FPU Operand Pointer Offset (foo)
+ uint32_t foseg; // FPU Operand Pointer Selector (fos)
+ } i386_; // Added _ in the end to avoid error with gcc defining i386 in some
+ // cases
+ } ptr;
+ uint32_t mxcsr; // MXCSR Register State
+ uint32_t mxcsrmask; // MXCSR Mask
+ MMSReg stmm[8]; // 8*16 bytes for each FP-reg = 128 bytes
+ XMMReg xmm[8]; // 8*16 bytes for each XMM-reg = 128 bytes
+ uint32_t padding[56];
+};
+
+struct UserArea {
+ GPR regs; // General purpose registers.
+ int32_t fpvalid; // True if FPU is being used.
+ FPR_i386 i387; // FPU registers.
+ uint32_t tsize; // Text segment size.
+ uint32_t dsize; // Data segment size.
+ uint32_t ssize; // Stack segment size.
+ uint32_t start_code; // VM address of text.
+ uint32_t start_stack; // VM address of stack bottom (top in rsp).
+ int32_t signal; // Signal causing core dump.
+ int32_t reserved; // Unused.
+ uint32_t ar0; // Location of GPR's.
+ uint32_t fpstate; // Location of FPR's. Should be a FXSTATE *, but this
+ // has to be 32-bits even on 64-bit systems.
+ uint32_t magic; // Identifier for core dumps.
+ char u_comm[32]; // Command causing core dump.
+ uint32_t u_debugreg[8]; // Debug registers (DR0 - DR7).
+};
+
+#define DR_SIZE sizeof(((UserArea *)NULL)->u_debugreg[0])
+#define DR_0_OFFSET 0xFC
+#define DR_OFFSET(reg_index) (DR_0_OFFSET + (reg_index * 4))
+#define FPR_SIZE(reg) sizeof(((FPR_i386 *)NULL)->reg)
+
+// Include RegisterInfos_i386 to declare our g_register_infos_i386 structure.
+#define DECLARE_REGISTER_INFOS_I386_STRUCT
+#include "Register/Arch/RegisterInfos_i386.h"
+#undef DECLARE_REGISTER_INFOS_I386_STRUCT
+
+RegisterInfoLinux_i386::RegisterInfoLinux_i386(
+ const ArchSpec &target_arch)
+ : RegisterInfoLinux_x86(
+ target_arch,
+ {"orig_eax",
+ nullptr,
+ sizeof(((GPR *)nullptr)->orig_eax),
+ (LLVM_EXTENSION offsetof(GPR, orig_eax)),
+ eEncodingUint,
+ eFormatHex,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM},
+ nullptr,
+ nullptr,
+ nullptr}) {}
+
+size_t RegisterInfoLinux_i386::GetGPRSizeStatic() { return sizeof(GPR); }
+
+const RegisterInfo *RegisterInfoLinux_i386::GetRegisterInfo() const {
+ switch (GetTargetArchitecture().GetMachine()) {
+ case llvm::Triple::x86:
+ case llvm::Triple::x86_64:
+ return g_register_infos_i386;
+ default:
+ assert(false && "Unhandled target architecture.");
+ return nullptr;
+ }
+}
+
+uint32_t RegisterInfoLinux_i386::GetRegisterCount() const {
+ return static_cast<uint32_t>(sizeof(g_register_infos_i386) /
+ sizeof(g_register_infos_i386[0]));
+}
+
+uint32_t RegisterInfoLinux_i386::GetUserRegisterCount() const {
+ return static_cast<uint32_t>(k_num_user_registers_i386);
+}
diff --git a/lldb/source/Register/Linux/RegisterInfoLinux_i386.h b/lldb/source/Register/Linux/RegisterInfoLinux_i386.h
new file mode 100644
index 00000000000000..a6904b48d9277a
--- /dev/null
+++ b/lldb/source/Register/Linux/RegisterInfoLinux_i386.h
@@ -0,0 +1,29 @@
+//===-- RegisterInfoLinux_i386.h -----------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLDB_SOURCE_REGISTER_LINUX_REGISTERINFOLINUX_I386_H
+#define LLDB_SOURCE_REGISTER_LINUX_REGISTERINFOLINUX_I386_H
+
+#include "Register/Linux/RegisterInfoLinux_x86.h"
+
+class RegisterInfoLinux_i386
+ : public lldb_private::RegisterInfoLinux_x86 {
+public:
+ RegisterInfoLinux_i386(const lldb_private::ArchSpec &target_arch);
+
+ static size_t GetGPRSizeStatic();
+ size_t GetGPRSize() const override { return GetGPRSizeStatic(); }
+
+ const lldb_private::RegisterInfo *GetRegisterInfo() const override;
+
+ uint32_t GetRegisterCount() const override;
+
+ uint32_t GetUserRegisterCount() const override;
+};
+
+#endif
diff --git a/lldb/source/Register/Linux/RegisterInfoLinux_s390x.cpp b/lldb/source/Register/Linux/RegisterInfoLinux_s390x.cpp
new file mode 100644
index 00000000000000..682b83f723ade2
--- /dev/null
+++ b/lldb/source/Register/Linux/RegisterInfoLinux_s390x.cpp
@@ -0,0 +1,69 @@
+//===-- RegisterInfoLinux_s390x.cpp ------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "Register/Linux/RegisterInfoLinux_s390x.h"
+#include "Plugins/Process/Utility/RegisterContextPOSIX_s390x.h"
+
+using namespace lldb_private;
+using namespace lldb;
+
+// Include RegisterInfos_s390x to declare our g_register_infos_s390x structure.
+#define DECLARE_REGISTER_INFOS_S390X_STRUCT
+#include "Register/Arch/RegisterInfos_s390x.h"
+#undef DECLARE_REGISTER_INFOS_S390X_STRUCT
+
+static const RegisterInfo *GetRegisterInfoPtr(const ArchSpec &target_arch) {
+ switch (target_arch.GetMachine()) {
+ case llvm::Triple::systemz:
+ return g_register_infos_s390x;
+ default:
+ assert(false && "Unhandled target architecture.");
+ return nullptr;
+ }
+}
+
+static uint32_t GetRegisterInfoCount(const ArchSpec &target_arch) {
+ switch (target_arch.GetMachine()) {
+ case llvm::Triple::systemz:
+ return k_num_registers_s390x;
+ default:
+ assert(false && "Unhandled target architecture.");
+ return 0;
+ }
+}
+
+static uint32_t GetUserRegisterInfoCount(const ArchSpec &target_arch) {
+ switch (target_arch.GetMachine()) {
+ case llvm::Triple::systemz:
+ return k_num_user_registers_s390x + k_num_linux_registers_s390x;
+ default:
+ assert(false && "Unhandled target architecture.");
+ return 0;
+ }
+}
+
+RegisterInfoLinux_s390x::RegisterInfoLinux_s390x(
+ const ArchSpec &target_arch)
+ : lldb_private::RegisterInfoInterface(target_arch),
+ m_register_info_p(GetRegisterInfoPtr(target_arch)),
+ m_register_info_count(GetRegisterInfoCount(target_arch)),
+ m_user_register_count(GetUserRegisterInfoCount(target_arch)) {}
+
+const RegisterInfo *RegisterInfoLinux_s390x::GetRegisterInfo() const {
+ return m_register_info_p;
+}
+
+uint32_t RegisterInfoLinux_s390x::GetRegisterCount() const {
+ return m_register_info_count;
+}
+
+uint32_t RegisterInfoLinux_s390x::GetUserRegisterCount() const {
+ return m_user_register_count;
+}
+
+size_t RegisterInfoLinux_s390x::GetGPRSize() const { return 0; }
diff --git a/lldb/source/Register/Linux/RegisterInfoLinux_s390x.h b/lldb/source/Register/Linux/RegisterInfoLinux_s390x.h
new file mode 100644
index 00000000000000..418eb69e6aa840
--- /dev/null
+++ b/lldb/source/Register/Linux/RegisterInfoLinux_s390x.h
@@ -0,0 +1,32 @@
+//===-- RegisterInfoLinux_s390x.h ----------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLDB_SOURCE_REGISTER_LINUX_REGISTERINFOLINUX_S390X_H
+#define LLDB_SOURCE_REGISTER_LINUX_REGISTERINFOLINUX_S390X_H
+
+#include "Register/RegisterInfoInterface.h"
+
+class RegisterInfoLinux_s390x : public lldb_private::RegisterInfoInterface {
+public:
+ RegisterInfoLinux_s390x(const lldb_private::ArchSpec &target_arch);
+
+ size_t GetGPRSize() const override;
+
+ const lldb_private::RegisterInfo *GetRegisterInfo() const override;
+
+ uint32_t GetRegisterCount() const override;
+
+ uint32_t GetUserRegisterCount() const override;
+
+private:
+ const lldb_private::RegisterInfo *m_register_info_p;
+ uint32_t m_register_info_count;
+ uint32_t m_user_register_count;
+};
+
+#endif
diff --git a/lldb/source/Register/Linux/RegisterInfoLinux_x86.h b/lldb/source/Register/Linux/RegisterInfoLinux_x86.h
new file mode 100644
index 00000000000000..f81605afee5e9a
--- /dev/null
+++ b/lldb/source/Register/Linux/RegisterInfoLinux_x86.h
@@ -0,0 +1,30 @@
+//===-- RegisterInfoLinux_i386.h -----------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLDB_SOURCE_REGISTER_LINUX_REGISTERINFOLINUX_X86_H
+#define LLDB_SOURCE_REGISTER_LINUX_REGISTERINFOLINUX_X86_H
+
+#include "Register/RegisterInfoInterface.h"
+
+namespace lldb_private {
+
+class RegisterInfoLinux_x86 : public RegisterInfoInterface {
+public:
+ RegisterInfoLinux_x86(const ArchSpec &target_arch,
+ RegisterInfo orig_ax_info)
+ : RegisterInfoInterface(target_arch), m_orig_ax_info(orig_ax_info) {}
+
+ const RegisterInfo &GetOrigAxInfo() const { return m_orig_ax_info; }
+
+private:
+ lldb_private::RegisterInfo m_orig_ax_info;
+};
+
+} // namespace lldb_private
+
+#endif
diff --git a/lldb/source/Register/Linux/RegisterInfoLinux_x86_64.cpp b/lldb/source/Register/Linux/RegisterInfoLinux_x86_64.cpp
new file mode 100644
index 00000000000000..4b0c14c921adb9
--- /dev/null
+++ b/lldb/source/Register/Linux/RegisterInfoLinux_x86_64.cpp
@@ -0,0 +1,186 @@
+//===-- RegisterInfoLinux_x86_64.cpp -----------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===---------------------------------------------------------------------===//
+
+#include "Register/Linux/RegisterInfoLinux_x86_64.h"
+#include "Register/Linux/RegisterInfoLinux_i386.h"
+#include "Register/Arch/RegisterContext_x86.h"
+#include "Register/Arch/lldb-x86-register-enums.h"
+#include "lldb/lldb-defines.h"
+#include <vector>
+
+using namespace lldb_private;
+using namespace lldb;
+
+typedef struct _GPR {
+ uint64_t r15;
+ uint64_t r14;
+ uint64_t r13;
+ uint64_t r12;
+ uint64_t rbp;
+ uint64_t rbx;
+ uint64_t r11;
+ uint64_t r10;
+ uint64_t r9;
+ uint64_t r8;
+ uint64_t rax;
+ uint64_t rcx;
+ uint64_t rdx;
+ uint64_t rsi;
+ uint64_t rdi;
+ uint64_t orig_rax;
+ uint64_t rip;
+ uint64_t cs;
+ uint64_t rflags;
+ uint64_t rsp;
+ uint64_t ss;
+ uint64_t fs_base;
+ uint64_t gs_base;
+ uint64_t ds;
+ uint64_t es;
+ uint64_t fs;
+ uint64_t gs;
+} GPR;
+
+struct DBG {
+ uint64_t dr[8];
+};
+
+struct UserArea {
+ GPR gpr; // General purpose registers.
+ int32_t fpvalid; // True if FPU is being used.
+ int32_t pad0;
+ FXSAVE fpr; // General purpose floating point registers (see FPR for extended
+ // register sets).
+ uint64_t tsize; // Text segment size.
+ uint64_t dsize; // Data segment size.
+ uint64_t ssize; // Stack segment size.
+ uint64_t start_code; // VM address of text.
+ uint64_t start_stack; // VM address of stack bottom (top in rsp).
+ int64_t signal; // Signal causing core dump.
+ int32_t reserved; // Unused.
+ int32_t pad1;
+ uint64_t ar0; // Location of GPR's.
+ FXSAVE *fpstate; // Location of FPR's.
+ uint64_t magic; // Identifier for core dumps.
+ char u_comm[32]; // Command causing core dump.
+ DBG dbg; // Debug registers.
+ uint64_t error_code; // CPU error code.
+ uint64_t fault_address; // Control register CR3.
+};
+
+#define DR_OFFSET(reg_index) \
+ (LLVM_EXTENSION offsetof(UserArea, dbg) + \
+ LLVM_EXTENSION offsetof(DBG, dr[reg_index]))
+
+// Include RegisterInfos_x86_64 to declare our g_register_infos_x86_64_with_base
+// structure.
+#define DECLARE_REGISTER_INFOS_X86_64_STRUCT
+#include "Register/Arch/RegisterInfos_x86_64_with_base.h"
+#undef DECLARE_REGISTER_INFOS_X86_64_STRUCT
+
+static std::vector<lldb_private::RegisterInfo> &GetPrivateRegisterInfoVector() {
+ static std::vector<lldb_private::RegisterInfo> g_register_infos;
+ return g_register_infos;
+}
+
+static const RegisterInfo *
+GetRegisterInfo_i386(const lldb_private::ArchSpec &arch) {
+ std::vector<lldb_private::RegisterInfo> &g_register_infos =
+ GetPrivateRegisterInfoVector();
+
+ // Allocate RegisterInfo only once
+ if (g_register_infos.empty()) {
+ // Copy the register information from base class
+ std::unique_ptr<RegisterInfoLinux_i386> reg_interface(
+ new RegisterInfoLinux_i386(arch));
+ const RegisterInfo *base_info = reg_interface->GetRegisterInfo();
+ g_register_infos.insert(g_register_infos.end(), &base_info[0],
+ &base_info[k_num_registers_i386]);
+
+// Include RegisterInfos_x86_64 to update the g_register_infos structure
+// with x86_64 offsets.
+#define UPDATE_REGISTER_INFOS_I386_STRUCT_WITH_X86_64_OFFSETS
+#include "Register/Arch/RegisterInfos_x86_64_with_base.h"
+#undef UPDATE_REGISTER_INFOS_I386_STRUCT_WITH_X86_64_OFFSETS
+ }
+
+ return &g_register_infos[0];
+}
+
+static const RegisterInfo *GetRegisterInfoPtr(const ArchSpec &target_arch) {
+ switch (target_arch.GetMachine()) {
+ case llvm::Triple::x86:
+ return GetRegisterInfo_i386(target_arch);
+ case llvm::Triple::x86_64:
+ return g_register_infos_x86_64_with_base;
+ default:
+ assert(false && "Unhandled target architecture.");
+ return nullptr;
+ }
+}
+
+static uint32_t GetRegisterInfoCount(const ArchSpec &target_arch) {
+ switch (target_arch.GetMachine()) {
+ case llvm::Triple::x86: {
+ assert(!GetPrivateRegisterInfoVector().empty() &&
+ "i386 register info not yet filled.");
+ return static_cast<uint32_t>(GetPrivateRegisterInfoVector().size());
+ }
+ case llvm::Triple::x86_64:
+ return static_cast<uint32_t>(sizeof(g_register_infos_x86_64_with_base) /
+ sizeof(g_register_infos_x86_64_with_base[0]));
+ default:
+ assert(false && "Unhandled target architecture.");
+ return 0;
+ }
+}
+
+static uint32_t GetUserRegisterInfoCount(const ArchSpec &target_arch) {
+ switch (target_arch.GetMachine()) {
+ case llvm::Triple::x86:
+ return static_cast<uint32_t>(k_num_user_registers_i386);
+ case llvm::Triple::x86_64:
+ return static_cast<uint32_t>(x86_64_with_base::k_num_user_registers);
+ default:
+ assert(false && "Unhandled target architecture.");
+ return 0;
+ }
+}
+
+RegisterInfoLinux_x86_64::RegisterInfoLinux_x86_64(
+ const ArchSpec &target_arch)
+ : lldb_private::RegisterInfoLinux_x86(
+ target_arch,
+ {"orig_rax",
+ nullptr,
+ sizeof(((GPR *)nullptr)->orig_rax),
+ (LLVM_EXTENSION offsetof(GPR, orig_rax)),
+ eEncodingUint,
+ eFormatHex,
+ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+ LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM},
+ nullptr,
+ nullptr,
+ nullptr}),
+ m_register_info_p(GetRegisterInfoPtr(target_arch)),
+ m_register_info_count(GetRegisterInfoCount(target_arch)),
+ m_user_register_count(GetUserRegisterInfoCount(target_arch)) {}
+
+size_t RegisterInfoLinux_x86_64::GetGPRSizeStatic() { return sizeof(GPR); }
+
+const RegisterInfo *RegisterInfoLinux_x86_64::GetRegisterInfo() const {
+ return m_register_info_p;
+}
+
+uint32_t RegisterInfoLinux_x86_64::GetRegisterCount() const {
+ return m_register_info_count;
+}
+
+uint32_t RegisterInfoLinux_x86_64::GetUserRegisterCount() const {
+ return m_user_register_count;
+}
diff --git a/lldb/source/Register/Linux/RegisterInfoLinux_x86_64.h b/lldb/source/Register/Linux/RegisterInfoLinux_x86_64.h
new file mode 100644
index 00000000000000..09ad77263b3b34
--- /dev/null
+++ b/lldb/source/Register/Linux/RegisterInfoLinux_x86_64.h
@@ -0,0 +1,34 @@
+//===-- RegisterInfoLinux_x86_64.h ---------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLDB_SOURCE_REGISTER_LINUX_REGISTERINFOLINUX_X86_64_H
+#define LLDB_SOURCE_REGISTER_LINUX_REGISTERINFOLINUX_X86_64_H
+
+#include "Register/Linux/RegisterInfoLinux_x86.h"
+
+class RegisterInfoLinux_x86_64
+ : public lldb_private::RegisterInfoLinux_x86 {
+public:
+ RegisterInfoLinux_x86_64(const lldb_private::ArchSpec &target_arch);
+
+ static size_t GetGPRSizeStatic();
+ size_t GetGPRSize() const override { return GetGPRSizeStatic(); }
+
+ const lldb_private::RegisterInfo *GetRegisterInfo() const override;
+
+ uint32_t GetRegisterCount() const override;
+
+ uint32_t GetUserRegisterCount() const override;
+
+private:
+ const lldb_private::RegisterInfo *m_register_info_p;
+ uint32_t m_register_info_count;
+ uint32_t m_user_register_count;
+};
+
+#endif
diff --git a/lldb/source/Register/NetBSD/RegisterInfoNetBSD_i386.cpp b/lldb/source/Register/NetBSD/RegisterInfoNetBSD_i386.cpp
new file mode 100644
index 00000000000000..140c46989f5d9b
--- /dev/null
+++ b/lldb/source/Register/NetBSD/RegisterInfoNetBSD_i386.cpp
@@ -0,0 +1,98 @@
+//===-- RegisterInfoNetBSD_i386.cpp --------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "Register/NetBSD/RegisterInfoNetBSD_i386.h"
+#include "Register/Arch/RegisterContext_x86.h"
+#include "Register/Arch/lldb-x86-register-enums.h"
+#include "lldb/lldb-defines.h"
+
+using namespace lldb_private;
+using namespace lldb;
+
+// this needs to match 'struct reg'
+struct GPR {
+ uint32_t eax;
+ uint32_t ecx;
+ uint32_t edx;
+ uint32_t ebx;
+ uint32_t esp;
+ uint32_t ebp;
+ uint32_t esi;
+ uint32_t edi;
+ uint32_t eip;
+ uint32_t eflags;
+ uint32_t cs;
+ uint32_t ss;
+ uint32_t ds;
+ uint32_t es;
+ uint32_t fs;
+ uint32_t gs;
+};
+
+struct FPR_i386 {
+ uint16_t fctrl; // FPU Control Word (fcw)
+ uint16_t fstat; // FPU Status Word (fsw)
+ uint16_t ftag; // FPU Tag Word (ftw)
+ uint16_t fop; // Last Instruction Opcode (fop)
+ union {
+ struct {
+ uint64_t fip; // Instruction Pointer
+ uint64_t fdp; // Data Pointer
+ } x86_64;
+ struct {
+ uint32_t fioff; // FPU IP Offset (fip)
+ uint32_t fiseg; // FPU IP Selector (fcs)
+ uint32_t fooff; // FPU Operand Pointer Offset (foo)
+ uint32_t foseg; // FPU Operand Pointer Selector (fos)
+ } i386_; // Added _ in the end to avoid error with gcc defining i386 in some
+ // cases
+ } ptr;
+ uint32_t mxcsr; // MXCSR Register State
+ uint32_t mxcsrmask; // MXCSR Mask
+ MMSReg stmm[8]; // 8*16 bytes for each FP-reg = 128 bytes
+ XMMReg xmm[8]; // 8*16 bytes for each XMM-reg = 128 bytes
+ uint32_t padding[56];
+};
+
+struct UserArea {
+ GPR gpr;
+ FPR_i386 i387;
+ uint32_t u_debugreg[8]; // Debug registers (DR0 - DR7).
+ uint32_t tlsbase;
+};
+
+#define DR_SIZE sizeof(((UserArea *)NULL)->u_debugreg[0])
+#define DR_OFFSET(reg_index) \
+ (LLVM_EXTENSION offsetof(UserArea, u_debugreg[reg_index]))
+
+// Include RegisterInfos_i386 to declare our g_register_infos_i386 structure.
+#define DECLARE_REGISTER_INFOS_I386_STRUCT
+#include "Register/Arch/RegisterInfos_i386.h"
+#undef DECLARE_REGISTER_INFOS_I386_STRUCT
+
+RegisterInfoNetBSD_i386::RegisterInfoNetBSD_i386(
+ const ArchSpec &target_arch)
+ : RegisterInfoInterface(target_arch) {}
+
+size_t RegisterInfoNetBSD_i386::GetGPRSize() const { return sizeof(GPR); }
+
+const RegisterInfo *RegisterInfoNetBSD_i386::GetRegisterInfo() const {
+ switch (GetTargetArchitecture().GetMachine()) {
+ case llvm::Triple::x86:
+ case llvm::Triple::x86_64:
+ return g_register_infos_i386;
+ default:
+ assert(false && "Unhandled target architecture.");
+ return nullptr;
+ }
+}
+
+uint32_t RegisterInfoNetBSD_i386::GetRegisterCount() const {
+ return static_cast<uint32_t>(sizeof(g_register_infos_i386) /
+ sizeof(g_register_infos_i386[0]));
+}
diff --git a/lldb/source/Register/NetBSD/RegisterInfoNetBSD_i386.h b/lldb/source/Register/NetBSD/RegisterInfoNetBSD_i386.h
new file mode 100644
index 00000000000000..47d1b83620d1f6
--- /dev/null
+++ b/lldb/source/Register/NetBSD/RegisterInfoNetBSD_i386.h
@@ -0,0 +1,25 @@
+//===-- RegisterInfoNetBSD_i386.h ----------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLDB_SOURCE_REGISTER_NETBSD_REGISTERINFONETBSD_I386_H
+#define LLDB_SOURCE_REGISTER_NETBSD_REGISTERINFONETBSD_I386_H
+
+#include "Register/RegisterInfoInterface.h"
+
+class RegisterInfoNetBSD_i386 : public lldb_private::RegisterInfoInterface {
+public:
+ RegisterInfoNetBSD_i386(const lldb_private::ArchSpec &target_arch);
+
+ size_t GetGPRSize() const override;
+
+ const lldb_private::RegisterInfo *GetRegisterInfo() const override;
+
+ uint32_t GetRegisterCount() const override;
+};
+
+#endif
diff --git a/lldb/source/Register/NetBSD/RegisterInfoNetBSD_x86_64.cpp b/lldb/source/Register/NetBSD/RegisterInfoNetBSD_x86_64.cpp
new file mode 100644
index 00000000000000..104e97934c1150
--- /dev/null
+++ b/lldb/source/Register/NetBSD/RegisterInfoNetBSD_x86_64.cpp
@@ -0,0 +1,180 @@
+//===-- RegisterInfoNetBSD_x86_64.cpp ----------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "Register/NetBSD/RegisterInfoNetBSD_x86_64.h"
+#include "Register/NetBSD/RegisterInfoNetBSD_i386.h"
+#include "Register/Arch/RegisterContext_x86.h"
+#include "Register/Arch/lldb-x86-register-enums.h"
+#include "lldb/lldb-defines.h"
+#include "llvm/Support/Compiler.h"
+#include "llvm/TargetParser/Triple.h"
+#include <cassert>
+#include <cstddef>
+
+using namespace lldb_private;
+using namespace lldb;
+
+// src/sys/arch/amd64/include/frame_regs.h
+typedef struct _GPR {
+ uint64_t rdi; /* 0 */
+ uint64_t rsi; /* 1 */
+ uint64_t rdx; /* 2 */
+ uint64_t rcx; /* 3 */
+ uint64_t r8; /* 4 */
+ uint64_t r9; /* 5 */
+ uint64_t r10; /* 6 */
+ uint64_t r11; /* 7 */
+ uint64_t r12; /* 8 */
+ uint64_t r13; /* 9 */
+ uint64_t r14; /* 10 */
+ uint64_t r15; /* 11 */
+ uint64_t rbp; /* 12 */
+ uint64_t rbx; /* 13 */
+ uint64_t rax; /* 14 */
+ uint64_t gs; /* 15 */
+ uint64_t fs; /* 16 */
+ uint64_t es; /* 17 */
+ uint64_t ds; /* 18 */
+ uint64_t trapno; /* 19 */
+ uint64_t err; /* 20 */
+ uint64_t rip; /* 21 */
+ uint64_t cs; /* 22 */
+ uint64_t rflags; /* 23 */
+ uint64_t rsp; /* 24 */
+ uint64_t ss; /* 25 */
+} GPR;
+
+struct DBG {
+ uint64_t dr[16]; /* debug registers */
+ /* Index 0-3: debug address registers */
+ /* Index 4-5: reserved */
+ /* Index 6: debug status */
+ /* Index 7: debug control */
+ /* Index 8-15: reserved */
+};
+
+/*
+ * src/sys/arch/amd64/include/mcontext.h
+ *
+ * typedef struct {
+ * __gregset_t __gregs;
+ * __greg_t _mc_tlsbase;
+ * __fpregset_t __fpregs;
+ * } mcontext_t;
+ */
+
+struct UserArea {
+ GPR gpr;
+ uint64_t mc_tlsbase;
+ FPR fpr;
+ DBG dbg;
+};
+
+#define DR_OFFSET(reg_index) \
+ (LLVM_EXTENSION offsetof(UserArea, dbg) + \
+ LLVM_EXTENSION offsetof(DBG, dr[reg_index]))
+
+
+// Include RegisterInfos_x86_64 to declare our g_register_infos_x86_64
+// structure.
+#define DECLARE_REGISTER_INFOS_X86_64_STRUCT
+#include "Register/Arch/RegisterInfos_x86_64.h"
+#undef DECLARE_REGISTER_INFOS_X86_64_STRUCT
+
+static std::vector<lldb_private::RegisterInfo> &GetPrivateRegisterInfoVector() {
+ static std::vector<lldb_private::RegisterInfo> g_register_infos;
+ return g_register_infos;
+}
+
+static const RegisterInfo *
+GetRegisterInfo_i386(const lldb_private::ArchSpec &arch) {
+ std::vector<lldb_private::RegisterInfo> &g_register_infos =
+ GetPrivateRegisterInfoVector();
+
+ // Allocate RegisterInfo only once
+ if (g_register_infos.empty()) {
+ // Copy the register information from base class
+ std::unique_ptr<RegisterInfoNetBSD_i386> reg_interface(
+ new RegisterInfoNetBSD_i386(arch));
+ const RegisterInfo *base_info = reg_interface->GetRegisterInfo();
+ g_register_infos.insert(g_register_infos.end(), &base_info[0],
+ &base_info[k_num_registers_i386]);
+
+// Include RegisterInfos_x86_64 to update the g_register_infos structure
+// with x86_64 offsets.
+#define UPDATE_REGISTER_INFOS_I386_STRUCT_WITH_X86_64_OFFSETS
+#include "Register/Arch/RegisterInfos_x86_64.h"
+#undef UPDATE_REGISTER_INFOS_I386_STRUCT_WITH_X86_64_OFFSETS
+ }
+
+ return &g_register_infos[0];
+}
+
+static const RegisterInfo *
+PrivateGetRegisterInfoPtr(const lldb_private::ArchSpec &target_arch) {
+ switch (target_arch.GetMachine()) {
+ case llvm::Triple::x86:
+ return GetRegisterInfo_i386(target_arch);
+ case llvm::Triple::x86_64:
+ return g_register_infos_x86_64;
+ default:
+ assert(false && "Unhandled target architecture.");
+ return nullptr;
+ }
+}
+
+static uint32_t
+PrivateGetRegisterCount(const lldb_private::ArchSpec &target_arch) {
+ switch (target_arch.GetMachine()) {
+ case llvm::Triple::x86: {
+ assert(!GetPrivateRegisterInfoVector().empty() &&
+ "i386 register info not yet filled.");
+ return static_cast<uint32_t>(GetPrivateRegisterInfoVector().size());
+ }
+ case llvm::Triple::x86_64:
+ return static_cast<uint32_t>(sizeof(g_register_infos_x86_64) /
+ sizeof(g_register_infos_x86_64[0]));
+ default:
+ assert(false && "Unhandled target architecture.");
+ return 0;
+ }
+}
+
+static uint32_t
+PrivateGetUserRegisterCount(const lldb_private::ArchSpec &target_arch) {
+ switch (target_arch.GetMachine()) {
+ case llvm::Triple::x86:
+ return static_cast<uint32_t>(k_num_user_registers_i386);
+ case llvm::Triple::x86_64:
+ return static_cast<uint32_t>(k_num_user_registers_x86_64);
+ default:
+ assert(false && "Unhandled target architecture.");
+ return 0;
+ }
+}
+
+RegisterInfoNetBSD_x86_64::RegisterInfoNetBSD_x86_64(
+ const ArchSpec &target_arch)
+ : lldb_private::RegisterInfoInterface(target_arch),
+ m_register_info_p(PrivateGetRegisterInfoPtr(target_arch)),
+ m_register_count(PrivateGetRegisterCount(target_arch)),
+ m_user_register_count(PrivateGetUserRegisterCount(target_arch)) {}
+
+size_t RegisterInfoNetBSD_x86_64::GetGPRSize() const { return sizeof(GPR); }
+
+const RegisterInfo *RegisterInfoNetBSD_x86_64::GetRegisterInfo() const {
+ return m_register_info_p;
+}
+
+uint32_t RegisterInfoNetBSD_x86_64::GetRegisterCount() const {
+ return m_register_count;
+}
+
+uint32_t RegisterInfoNetBSD_x86_64::GetUserRegisterCount() const {
+ return m_user_register_count;
+}
diff --git a/lldb/source/Register/NetBSD/RegisterInfoNetBSD_x86_64.h b/lldb/source/Register/NetBSD/RegisterInfoNetBSD_x86_64.h
new file mode 100644
index 00000000000000..1c0323d98a929e
--- /dev/null
+++ b/lldb/source/Register/NetBSD/RegisterInfoNetBSD_x86_64.h
@@ -0,0 +1,33 @@
+//===-- RegisterInfoNetBSD_x86_64.h --------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLDB_SOURCE_REGISTER_NETBSD_REGISTERINFONETBSD_X86_64_H
+#define LLDB_SOURCE_REGISTER_NETBSD_REGISTERINFONETBSD_X86_64_H
+
+#include "Register/RegisterInfoInterface.h"
+
+class RegisterInfoNetBSD_x86_64
+ : public lldb_private::RegisterInfoInterface {
+public:
+ RegisterInfoNetBSD_x86_64(const lldb_private::ArchSpec &target_arch);
+
+ size_t GetGPRSize() const override;
+
+ const lldb_private::RegisterInfo *GetRegisterInfo() const override;
+
+ uint32_t GetRegisterCount() const override;
+
+ uint32_t GetUserRegisterCount() const override;
+
+private:
+ const lldb_private::RegisterInfo *m_register_info_p;
+ const uint32_t m_register_count;
+ const uint32_t m_user_register_count;
+};
+
+#endif
diff --git a/lldb/source/Register/OpenBSD/RegisterInfoOpenBSD_i386.cpp b/lldb/source/Register/OpenBSD/RegisterInfoOpenBSD_i386.cpp
new file mode 100644
index 00000000000000..338f6aa6d47adb
--- /dev/null
+++ b/lldb/source/Register/OpenBSD/RegisterInfoOpenBSD_i386.cpp
@@ -0,0 +1,79 @@
+//===-- RegisterInfoOpenBSD_i386.cpp -----------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===---------------------------------------------------------------------===//
+
+#include "Register/OpenBSD/RegisterInfoOpenBSD_i386.h"
+#include "Register/Arch/RegisterContext_x86.h"
+#include "Register/Arch/lldb-x86-register-enums.h"
+#include "lldb/lldb-defines.h"
+
+using namespace lldb_private;
+using namespace lldb;
+
+// /usr/include/machine/reg.h
+struct GPR {
+ uint32_t eax;
+ uint32_t ecx;
+ uint32_t edx;
+ uint32_t ebx;
+ uint32_t esp;
+ uint32_t ebp;
+ uint32_t esi;
+ uint32_t edi;
+ uint32_t eip;
+ uint32_t eflags;
+ uint32_t cs;
+ uint32_t ss;
+ uint32_t ds;
+ uint32_t es;
+ uint32_t fs;
+ uint32_t gs;
+};
+
+struct dbreg {
+ uint32_t dr[8]; /* debug registers */
+ /* Index 0-3: debug address registers */
+ /* Index 4-5: reserved */
+ /* Index 6: debug status */
+ /* Index 7: debug control */
+};
+
+using FPR_i386 = FXSAVE;
+
+struct UserArea {
+ GPR gpr;
+ FPR_i386 i387;
+};
+
+#define DR_SIZE sizeof(uint32_t)
+#define DR_OFFSET(reg_index) (LLVM_EXTENSION offsetof(dbreg, dr[reg_index]))
+
+// Include RegisterInfos_i386 to declare our g_register_infos_i386 structure.
+#define DECLARE_REGISTER_INFOS_I386_STRUCT
+#include "Register/Arch/RegisterInfos_i386.h"
+#undef DECLARE_REGISTER_INFOS_I386_STRUCT
+
+RegisterInfoOpenBSD_i386::RegisterInfoOpenBSD_i386(
+ const ArchSpec &target_arch)
+ : RegisterInfoInterface(target_arch) {}
+
+size_t RegisterInfoOpenBSD_i386::GetGPRSize() const { return sizeof(GPR); }
+
+const RegisterInfo *RegisterInfoOpenBSD_i386::GetRegisterInfo() const {
+ switch (GetTargetArchitecture().GetMachine()) {
+ case llvm::Triple::x86:
+ return g_register_infos_i386;
+ default:
+ assert(false && "Unhandled target architecture.");
+ return nullptr;
+ }
+}
+
+uint32_t RegisterInfoOpenBSD_i386::GetRegisterCount() const {
+ return static_cast<uint32_t>(sizeof(g_register_infos_i386) /
+ sizeof(g_register_infos_i386[0]));
+}
diff --git a/lldb/source/Register/OpenBSD/RegisterInfoOpenBSD_i386.h b/lldb/source/Register/OpenBSD/RegisterInfoOpenBSD_i386.h
new file mode 100644
index 00000000000000..9e0ba4c9a926fd
--- /dev/null
+++ b/lldb/source/Register/OpenBSD/RegisterInfoOpenBSD_i386.h
@@ -0,0 +1,25 @@
+//===-- RegisterInfoOpenBSD_i386.h ---------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLDB_SOURCE_REGISTER_OPENBSD_REGISTERINFOOPENBSD_I386_H
+#define LLDB_SOURCE_REGISTER_OPENBSD_REGISTERINFOOPENBSD_I386_H
+
+#include "Register/RegisterInfoInterface.h"
+
+class RegisterInfoOpenBSD_i386 : public lldb_private::RegisterInfoInterface {
+public:
+ RegisterInfoOpenBSD_i386(const lldb_private::ArchSpec &target_arch);
+
+ size_t GetGPRSize() const override;
+
+ const lldb_private::RegisterInfo *GetRegisterInfo() const override;
+
+ uint32_t GetRegisterCount() const override;
+};
+
+#endif
diff --git a/lldb/source/Register/OpenBSD/RegisterInfoOpenBSD_x86_64.cpp b/lldb/source/Register/OpenBSD/RegisterInfoOpenBSD_x86_64.cpp
new file mode 100644
index 00000000000000..5173990eefdd9c
--- /dev/null
+++ b/lldb/source/Register/OpenBSD/RegisterInfoOpenBSD_x86_64.cpp
@@ -0,0 +1,106 @@
+//===-- RegisterInfoOpenBSD_x86_64.cpp ---------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===---------------------------------------------------------------------===//
+
+#include "Register/OpenBSD/RegisterInfoOpenBSD_x86_64.h"
+#include "Register/Arch/RegisterContext_x86.h"
+#include "Register/Arch/lldb-x86-register-enums.h"
+#include "lldb/lldb-defines.h"
+#include <vector>
+
+using namespace lldb_private;
+using namespace lldb;
+
+// /usr/include/machine/reg.h
+typedef struct _GPR {
+ uint64_t rdi;
+ uint64_t rsi;
+ uint64_t rdx;
+ uint64_t rcx;
+ uint64_t r8;
+ uint64_t r9;
+ uint64_t r10;
+ uint64_t r11;
+ uint64_t r12;
+ uint64_t r13;
+ uint64_t r14;
+ uint64_t r15;
+ uint64_t rbp;
+ uint64_t rbx;
+ uint64_t rax;
+ uint64_t rsp;
+ uint64_t rip;
+ uint64_t rflags;
+ uint64_t cs;
+ uint64_t ss;
+ uint64_t ds;
+ uint64_t es;
+ uint64_t fs;
+ uint64_t gs;
+} GPR;
+
+struct DBG {
+ uint64_t dr[16]; /* debug registers */
+ /* Index 0-3: debug address registers */
+ /* Index 4-5: reserved */
+ /* Index 6: debug status */
+ /* Index 7: debug control */
+ /* Index 8-15: reserved */
+};
+
+struct UserArea {
+ GPR gpr;
+ FPR fpr;
+ DBG dbg;
+};
+
+#define DR_OFFSET(reg_index) (LLVM_EXTENSION offsetof(DBG, dr[reg_index]))
+
+// Include RegisterInfos_x86_64 to declare our g_register_infos_x86_64
+// structure.
+#define DECLARE_REGISTER_INFOS_X86_64_STRUCT
+#include "Register/Arch/RegisterInfos_x86_64.h"
+#undef DECLARE_REGISTER_INFOS_X86_64_STRUCT
+
+static const RegisterInfo *
+PrivateGetRegisterInfoPtr(const lldb_private::ArchSpec &target_arch) {
+ switch (target_arch.GetMachine()) {
+ case llvm::Triple::x86_64:
+ return g_register_infos_x86_64;
+ default:
+ assert(false && "Unhandled target architecture.");
+ return nullptr;
+ }
+}
+
+static uint32_t
+PrivateGetRegisterCount(const lldb_private::ArchSpec &target_arch) {
+ switch (target_arch.GetMachine()) {
+ case llvm::Triple::x86_64:
+ return static_cast<uint32_t>(sizeof(g_register_infos_x86_64) /
+ sizeof(g_register_infos_x86_64[0]));
+ default:
+ assert(false && "Unhandled target architecture.");
+ return 0;
+ }
+}
+
+RegisterInfoOpenBSD_x86_64::RegisterInfoOpenBSD_x86_64(
+ const ArchSpec &target_arch)
+ : lldb_private::RegisterInfoInterface(target_arch),
+ m_register_info_p(PrivateGetRegisterInfoPtr(target_arch)),
+ m_register_count(PrivateGetRegisterCount(target_arch)) {}
+
+size_t RegisterInfoOpenBSD_x86_64::GetGPRSize() const { return sizeof(GPR); }
+
+const RegisterInfo *RegisterInfoOpenBSD_x86_64::GetRegisterInfo() const {
+ return m_register_info_p;
+}
+
+uint32_t RegisterInfoOpenBSD_x86_64::GetRegisterCount() const {
+ return m_register_count;
+}
diff --git a/lldb/source/Register/OpenBSD/RegisterInfoOpenBSD_x86_64.h b/lldb/source/Register/OpenBSD/RegisterInfoOpenBSD_x86_64.h
new file mode 100644
index 00000000000000..174fee480dd36c
--- /dev/null
+++ b/lldb/source/Register/OpenBSD/RegisterInfoOpenBSD_x86_64.h
@@ -0,0 +1,30 @@
+//===-- RegisterInfoOpenBSD_x86_64.h -------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLDB_SOURCE_REGISTER_OPENBSD_REGISTERINFOOPENBSD_X86_64_H
+#define LLDB_SOURCE_REGISTER_OPENBSD_REGISTERINFOOPENBSD_X86_64_H
+
+#include "Register/RegisterInfoInterface.h"
+
+class RegisterInfoOpenBSD_x86_64
+ : public lldb_private::RegisterInfoInterface {
+public:
+ RegisterInfoOpenBSD_x86_64(const lldb_private::ArchSpec &target_arch);
+
+ size_t GetGPRSize() const override;
+
+ const lldb_private::RegisterInfo *GetRegisterInfo() const override;
+
+ uint32_t GetRegisterCount() const override;
+
+private:
+ const lldb_private::RegisterInfo *m_register_info_p;
+ const uint32_t m_register_count;
+};
+
+#endif
diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfoAndSetInterface.h b/lldb/source/Register/RegisterInfoAndSetInterface.h
similarity index 84%
rename from lldb/source/Plugins/Process/Utility/RegisterInfoAndSetInterface.h
rename to lldb/source/Register/RegisterInfoAndSetInterface.h
index 7e569dc9ba7844..9f13aa6d751f92 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterInfoAndSetInterface.h
+++ b/lldb/source/Register/RegisterInfoAndSetInterface.h
@@ -6,10 +6,10 @@
//
//===----------------------------------------------------------------------===//
-#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOANDSETINTERFACE_H
-#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOANDSETINTERFACE_H
+#ifndef LLDB_SOURCE_REGISTER_REGISTERINFOANDSETINTERFACE_H
+#define LLDB_SOURCE_REGISTER_REGISTERINFOANDSETINTERFACE_H
-#include "RegisterInfoInterface.h"
+#include "Register/RegisterInfoInterface.h"
#include "lldb/Utility/ArchSpec.h"
#include "lldb/lldb-private-types.h"
diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfoInterface.h b/lldb/source/Register/RegisterInfoInterface.h
similarity index 91%
rename from lldb/source/Plugins/Process/Utility/RegisterInfoInterface.h
rename to lldb/source/Register/RegisterInfoInterface.h
index 38d086de22bee3..d6adadc0e2051d 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterInfoInterface.h
+++ b/lldb/source/Register/RegisterInfoInterface.h
@@ -6,8 +6,8 @@
//
//===----------------------------------------------------------------------===//
-#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOINTERFACE_H
-#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOINTERFACE_H
+#ifndef LLDB_SOURCE_REGISTER_REGISTERINFOINTERFACE_H
+#define LLDB_SOURCE_REGISTER_REGISTERINFOINTERFACE_H
#include "lldb/Utility/ArchSpec.h"
#include "lldb/Utility/RegisterInfo.h"
diff --git a/lldb/source/Register/Windows/RegisterInfoWindows_i386.cpp b/lldb/source/Register/Windows/RegisterInfoWindows_i386.cpp
new file mode 100644
index 00000000000000..fde74c5f2ea4c7
--- /dev/null
+++ b/lldb/source/Register/Windows/RegisterInfoWindows_i386.cpp
@@ -0,0 +1,90 @@
+//===-- RegisterInfoWindows_i386.cpp -----------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "Register/Windows/RegisterInfoWindows_i386.h"
+#include "Register/Arch/RegisterContext_x86.h"
+#include "Register/Arch/lldb-x86-register-enums.h"
+#include "lldb/lldb-defines.h"
+
+using namespace lldb_private;
+using namespace lldb;
+
+namespace {
+// Declare our g_register_infos structure.
+typedef struct _GPR {
+ uint32_t eax;
+ uint32_t ebx;
+ uint32_t ecx;
+ uint32_t edx;
+ uint32_t edi;
+ uint32_t esi;
+ uint32_t ebp;
+ uint32_t esp;
+ uint32_t eip;
+ uint32_t eflags;
+ uint32_t cs;
+ uint32_t fs;
+ uint32_t gs;
+ uint32_t ss;
+ uint32_t ds;
+ uint32_t es;
+} GPR;
+
+#define GPR_OFFSET(regname) (LLVM_EXTENSION offsetof(GPR, regname))
+
+#define DEFINE_GPR(reg, alt, kind1, kind2, kind3, kind4) \
+ { \
+#reg, alt, sizeof(((GPR *)nullptr)->reg), GPR_OFFSET(reg), eEncodingUint, \
+ eFormatHex, \
+ {kind1, kind2, kind3, kind4, lldb_##reg##_i386 }, nullptr, nullptr, \
+ nullptr, \
+ }
+
+// clang-format off
+static RegisterInfo g_register_infos_i386[] = {
+// General purpose registers EH_Frame DWARF Generic Process Plugin
+// =========================== ================== ================ ========================= ====================
+ DEFINE_GPR(eax, nullptr, ehframe_eax_i386, dwarf_eax_i386, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+ DEFINE_GPR(ebx, nullptr, ehframe_ebx_i386, dwarf_ebx_i386, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+ DEFINE_GPR(ecx, nullptr, ehframe_ecx_i386, dwarf_ecx_i386, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+ DEFINE_GPR(edx, nullptr, ehframe_edx_i386, dwarf_edx_i386, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+ DEFINE_GPR(edi, nullptr, ehframe_edi_i386, dwarf_edi_i386, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+ DEFINE_GPR(esi, nullptr, ehframe_esi_i386, dwarf_esi_i386, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+ DEFINE_GPR(ebp, "fp", ehframe_ebp_i386, dwarf_ebp_i386, LLDB_REGNUM_GENERIC_FP, LLDB_INVALID_REGNUM),
+ DEFINE_GPR(esp, "sp", ehframe_esp_i386, dwarf_esp_i386, LLDB_REGNUM_GENERIC_SP, LLDB_INVALID_REGNUM),
+ DEFINE_GPR(eip, "pc", ehframe_eip_i386, dwarf_eip_i386, LLDB_REGNUM_GENERIC_PC, LLDB_INVALID_REGNUM),
+ DEFINE_GPR(eflags, "flags", ehframe_eflags_i386, dwarf_eflags_i386, LLDB_REGNUM_GENERIC_FLAGS, LLDB_INVALID_REGNUM),
+ DEFINE_GPR(cs, nullptr, LLDB_INVALID_REGNUM, dwarf_cs_i386, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+ DEFINE_GPR(fs, nullptr, LLDB_INVALID_REGNUM, dwarf_fs_i386, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+ DEFINE_GPR(gs, nullptr, LLDB_INVALID_REGNUM, dwarf_gs_i386, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+ DEFINE_GPR(ss, nullptr, LLDB_INVALID_REGNUM, dwarf_ss_i386, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+ DEFINE_GPR(ds, nullptr, LLDB_INVALID_REGNUM, dwarf_ds_i386, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+ DEFINE_GPR(es, nullptr, LLDB_INVALID_REGNUM, dwarf_es_i386, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+};
+// clang-format on
+} // namespace
+
+RegisterInfoWindows_i386::RegisterInfoWindows_i386(
+ const ArchSpec &target_arch)
+ : lldb_private::RegisterInfoInterface(target_arch) {
+ assert(target_arch.GetMachine() == llvm::Triple::x86);
+}
+
+const RegisterInfo *RegisterInfoWindows_i386::GetRegisterInfo() const {
+ return g_register_infos_i386;
+}
+
+uint32_t RegisterInfoWindows_i386::GetRegisterCount() const {
+ return std::size(g_register_infos_i386);
+}
+
+uint32_t RegisterInfoWindows_i386::GetUserRegisterCount() const {
+ return std::size(g_register_infos_i386);
+}
+
+size_t RegisterInfoWindows_i386::GetGPRSize() const { return sizeof(GPR); }
diff --git a/lldb/source/Register/Windows/RegisterInfoWindows_i386.h b/lldb/source/Register/Windows/RegisterInfoWindows_i386.h
new file mode 100644
index 00000000000000..cf6b1f6aceb38f
--- /dev/null
+++ b/lldb/source/Register/Windows/RegisterInfoWindows_i386.h
@@ -0,0 +1,27 @@
+//===-- RegisterInfoWindows_i386.h ---------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLDB_SOURCE_REGISTER_WINDOWS_REGISTERINFOWINDOWS_I386_H
+#define LLDB_SOURCE_REGISTER_WINDOWS_REGISTERINFOWINDOWS_I386_H
+
+#include "Register/RegisterInfoInterface.h"
+
+class RegisterInfoWindows_i386 : public lldb_private::RegisterInfoInterface {
+public:
+ RegisterInfoWindows_i386(const lldb_private::ArchSpec &target_arch);
+
+ size_t GetGPRSize() const override;
+
+ const lldb_private::RegisterInfo *GetRegisterInfo() const override;
+
+ uint32_t GetRegisterCount() const override;
+
+ uint32_t GetUserRegisterCount() const override;
+};
+
+#endif
diff --git a/lldb/source/Register/Windows/RegisterInfoWindows_x86_64.cpp b/lldb/source/Register/Windows/RegisterInfoWindows_x86_64.cpp
new file mode 100644
index 00000000000000..c8b312a77b68e2
--- /dev/null
+++ b/lldb/source/Register/Windows/RegisterInfoWindows_x86_64.cpp
@@ -0,0 +1,153 @@
+//===-- RegisterInfoWindows_x86_64.cpp ---------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "Register/Windows/RegisterInfoWindows_x86_64.h"
+#include "Register/Arch/RegisterContext_x86.h"
+#include "Register/Arch/lldb-x86-register-enums.h"
+#include "lldb/lldb-defines.h"
+
+#include <vector>
+
+using namespace lldb_private;
+using namespace lldb;
+
+namespace {
+typedef struct _GPR {
+ uint64_t rax;
+ uint64_t rcx;
+ uint64_t rdx;
+ uint64_t rbx;
+ uint64_t rsp;
+ uint64_t rbp;
+ uint64_t rsi;
+ uint64_t rdi;
+ uint64_t r8;
+ uint64_t r9;
+ uint64_t r10;
+ uint64_t r11;
+ uint64_t r12;
+ uint64_t r13;
+ uint64_t r14;
+ uint64_t r15;
+ uint64_t rip;
+ uint64_t rflags;
+ uint16_t cs;
+ uint16_t fs;
+ uint16_t gs;
+ uint16_t ss;
+ uint16_t ds;
+ uint16_t es;
+} GPR;
+
+#define GPR_OFFSET(regname) (LLVM_EXTENSION offsetof(GPR, regname))
+#define DEFINE_GPR(reg, alt, kind1, kind2, kind3, kind4) \
+ { \
+#reg, alt, sizeof(((GPR *)nullptr)->reg), GPR_OFFSET(reg), eEncodingUint, \
+ eFormatHex, \
+ {kind1, kind2, kind3, kind4, lldb_##reg##_x86_64 }, nullptr, nullptr, \
+ nullptr, \
+ }
+
+typedef struct _FPReg {
+ XMMReg xmm0;
+ XMMReg xmm1;
+ XMMReg xmm2;
+ XMMReg xmm3;
+ XMMReg xmm4;
+ XMMReg xmm5;
+ XMMReg xmm6;
+ XMMReg xmm7;
+ XMMReg xmm8;
+ XMMReg xmm9;
+ XMMReg xmm10;
+ XMMReg xmm11;
+ XMMReg xmm12;
+ XMMReg xmm13;
+ XMMReg xmm14;
+ XMMReg xmm15;
+} FPReg;
+
+#define FPR_OFFSET(regname) \
+ (sizeof(GPR) + LLVM_EXTENSION offsetof(FPReg, regname))
+
+#define DEFINE_XMM(reg) \
+ { \
+#reg, NULL, sizeof(((FPReg *)nullptr)->reg), FPR_OFFSET(reg), \
+ eEncodingUint, eFormatVectorOfUInt64, \
+ {dwarf_##reg##_x86_64, dwarf_##reg##_x86_64, LLDB_INVALID_REGNUM, \
+ LLDB_INVALID_REGNUM, lldb_##reg##_x86_64 }, \
+ nullptr, nullptr, nullptr, \
+ }
+
+// clang-format off
+static RegisterInfo g_register_infos_x86_64[] = {
+// General purpose registers EH_Frame DWARF Generic Process Plugin
+// =========================== ================== ================ ========================= ====================
+ DEFINE_GPR(rax, nullptr, dwarf_rax_x86_64, dwarf_rax_x86_64, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+ DEFINE_GPR(rbx, nullptr, dwarf_rbx_x86_64, dwarf_rbx_x86_64, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+ DEFINE_GPR(rcx, nullptr, dwarf_rcx_x86_64, dwarf_rcx_x86_64, LLDB_REGNUM_GENERIC_ARG1, LLDB_INVALID_REGNUM),
+ DEFINE_GPR(rdx, nullptr, dwarf_rdx_x86_64, dwarf_rdx_x86_64, LLDB_REGNUM_GENERIC_ARG2, LLDB_INVALID_REGNUM),
+ DEFINE_GPR(rdi, nullptr, dwarf_rdi_x86_64, dwarf_rdi_x86_64, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+ DEFINE_GPR(rsi, nullptr, dwarf_rsi_x86_64, dwarf_rsi_x86_64, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+ DEFINE_GPR(rbp, nullptr, dwarf_rbp_x86_64, dwarf_rbp_x86_64, LLDB_REGNUM_GENERIC_FP, LLDB_INVALID_REGNUM),
+ DEFINE_GPR(rsp, nullptr, dwarf_rsp_x86_64, dwarf_rsp_x86_64, LLDB_REGNUM_GENERIC_SP, LLDB_INVALID_REGNUM),
+ DEFINE_GPR(r8, nullptr, dwarf_r8_x86_64, dwarf_r8_x86_64, LLDB_REGNUM_GENERIC_ARG3, LLDB_INVALID_REGNUM),
+ DEFINE_GPR(r9, nullptr, dwarf_r9_x86_64, dwarf_r9_x86_64, LLDB_REGNUM_GENERIC_ARG4, LLDB_INVALID_REGNUM),
+ DEFINE_GPR(r10, nullptr, dwarf_r10_x86_64, dwarf_r10_x86_64, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+ DEFINE_GPR(r11, nullptr, dwarf_r11_x86_64, dwarf_r11_x86_64, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+ DEFINE_GPR(r12, nullptr, dwarf_r12_x86_64, dwarf_r12_x86_64, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+ DEFINE_GPR(r13, nullptr, dwarf_r13_x86_64, dwarf_r13_x86_64, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+ DEFINE_GPR(r14, nullptr, dwarf_r14_x86_64, dwarf_r14_x86_64, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+ DEFINE_GPR(r15, nullptr, dwarf_r15_x86_64, dwarf_r15_x86_64, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+ DEFINE_GPR(rip, nullptr, dwarf_rip_x86_64, dwarf_rip_x86_64, LLDB_REGNUM_GENERIC_PC, LLDB_INVALID_REGNUM),
+ DEFINE_GPR(rflags, nullptr, dwarf_rflags_x86_64, dwarf_rflags_x86_64, LLDB_REGNUM_GENERIC_FLAGS, LLDB_INVALID_REGNUM),
+ DEFINE_GPR(cs, nullptr, dwarf_cs_x86_64, dwarf_cs_x86_64, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+ DEFINE_GPR(fs, nullptr, dwarf_fs_x86_64, dwarf_fs_x86_64, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+ DEFINE_GPR(gs, nullptr, dwarf_gs_x86_64, dwarf_gs_x86_64, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+ DEFINE_GPR(ss, nullptr, dwarf_ss_x86_64, dwarf_ss_x86_64, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+ DEFINE_GPR(ds, nullptr, dwarf_ds_x86_64, dwarf_ds_x86_64, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+ DEFINE_GPR(es, nullptr, dwarf_es_x86_64, dwarf_es_x86_64, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM),
+ DEFINE_XMM(xmm0),
+ DEFINE_XMM(xmm1),
+ DEFINE_XMM(xmm2),
+ DEFINE_XMM(xmm3),
+ DEFINE_XMM(xmm4),
+ DEFINE_XMM(xmm5),
+ DEFINE_XMM(xmm6),
+ DEFINE_XMM(xmm7),
+ DEFINE_XMM(xmm8),
+ DEFINE_XMM(xmm9),
+ DEFINE_XMM(xmm10),
+ DEFINE_XMM(xmm11),
+ DEFINE_XMM(xmm12),
+ DEFINE_XMM(xmm13),
+ DEFINE_XMM(xmm14),
+ DEFINE_XMM(xmm15)
+};
+// clang-format on
+} // namespace
+
+RegisterInfoWindows_x86_64::RegisterInfoWindows_x86_64(
+ const ArchSpec &target_arch)
+ : lldb_private::RegisterInfoInterface(target_arch) {
+ assert(target_arch.GetMachine() == llvm::Triple::x86_64);
+}
+
+const RegisterInfo *RegisterInfoWindows_x86_64::GetRegisterInfo() const {
+ return g_register_infos_x86_64;
+}
+
+uint32_t RegisterInfoWindows_x86_64::GetRegisterCount() const {
+ return std::size(g_register_infos_x86_64);
+}
+
+uint32_t RegisterInfoWindows_x86_64::GetUserRegisterCount() const {
+ return std::size(g_register_infos_x86_64);
+}
+
+size_t RegisterInfoWindows_x86_64::GetGPRSize() const { return sizeof(GPR); }
diff --git a/lldb/source/Register/Windows/RegisterInfoWindows_x86_64.h b/lldb/source/Register/Windows/RegisterInfoWindows_x86_64.h
new file mode 100644
index 00000000000000..caf3018d823334
--- /dev/null
+++ b/lldb/source/Register/Windows/RegisterInfoWindows_x86_64.h
@@ -0,0 +1,28 @@
+//===-- RegisterInfoWindows_x86_64.h --- ---------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLDB_SOURCE_REGISTER_WINDOWS_REGISTERINFOWINDOWS_X86_64_H
+#define LLDB_SOURCE_REGISTER_WINDOWS_REGISTERINFOWINDOWS_X86_64_H
+
+#include "Register/RegisterInfoInterface.h"
+
+class RegisterInfoWindows_x86_64
+ : public lldb_private::RegisterInfoInterface {
+public:
+ RegisterInfoWindows_x86_64(const lldb_private::ArchSpec &target_arch);
+
+ size_t GetGPRSize() const override;
+
+ const lldb_private::RegisterInfo *GetRegisterInfo() const override;
+
+ uint32_t GetRegisterCount() const override;
+
+ uint32_t GetUserRegisterCount() const override;
+};
+
+#endif
diff --git a/lldb/unittests/Instruction/ARM64/TestAArch64Emulator.cpp b/lldb/unittests/Instruction/ARM64/TestAArch64Emulator.cpp
index 1ad9ec8f88f929..f66c62b38871cc 100644
--- a/lldb/unittests/Instruction/ARM64/TestAArch64Emulator.cpp
+++ b/lldb/unittests/Instruction/ARM64/TestAArch64Emulator.cpp
@@ -16,8 +16,8 @@
#include "lldb/Utility/RegisterValue.h"
#include "Plugins/Instruction/ARM64/EmulateInstructionARM64.h"
-#include "Plugins/Process/Utility/RegisterInfoCommon_arm64.h"
-#include "Plugins/Process/Utility/lldb-arm64-register-enums.h"
+#include "Register/Common/RegisterInfoCommon_arm64.h"
+#include "Register/Arch/lldb-arm64-register-enums.h"
using namespace lldb;
using namespace lldb_private;
diff --git a/lldb/unittests/Instruction/LoongArch/TestLoongArchEmulator.cpp b/lldb/unittests/Instruction/LoongArch/TestLoongArchEmulator.cpp
index c53b0bde52a090..ac6d31687b2691 100644
--- a/lldb/unittests/Instruction/LoongArch/TestLoongArchEmulator.cpp
+++ b/lldb/unittests/Instruction/LoongArch/TestLoongArchEmulator.cpp
@@ -15,8 +15,8 @@
#include "gtest/gtest.h"
#include "Plugins/Instruction/LoongArch/EmulateInstructionLoongArch.h"
-#include "Plugins/Process/Utility/RegisterInfoCommon_loongarch64.h"
-#include "Plugins/Process/Utility/lldb-loongarch-register-enums.h"
+#include "Register/Common/RegisterInfoCommon_loongarch64.h"
+#include "Register/Arch/lldb-loongarch-register-enums.h"
using namespace llvm;
using namespace lldb;
diff --git a/lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp b/lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp
index ebc80a3dd45d52..4459fe265e6bf5 100644
--- a/lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp
+++ b/lldb/unittests/Instruction/RISCV/TestRISCVEmulator.cpp
@@ -16,9 +16,9 @@
#include "lldb/Utility/RegisterValue.h"
#include "Plugins/Instruction/RISCV/EmulateInstructionRISCV.h"
-#include "Plugins/Process/Utility/RegisterInfoCommon_riscv32.h"
-#include "Plugins/Process/Utility/RegisterInfoCommon_riscv64.h"
-#include "Plugins/Process/Utility/lldb-riscv-register-enums.h"
+#include "Register/Common/RegisterInfoCommon_riscv32.h"
+#include "Register/Common/RegisterInfoCommon_riscv64.h"
+#include "Register/Arch/lldb-riscv-register-enums.h"
using namespace llvm;
using namespace lldb;
diff --git a/lldb/unittests/Instruction/RISCV/TestRiscvInstEmulation.cpp b/lldb/unittests/Instruction/RISCV/TestRiscvInstEmulation.cpp
index 009b9cdc79607a..dfa5c2ad4f851d 100644
--- a/lldb/unittests/Instruction/RISCV/TestRiscvInstEmulation.cpp
+++ b/lldb/unittests/Instruction/RISCV/TestRiscvInstEmulation.cpp
@@ -16,7 +16,7 @@
#include "Plugins/Disassembler/LLVMC/DisassemblerLLVMC.h"
#include "Plugins/Instruction/RISCV/EmulateInstructionRISCV.h"
-#include "Plugins/Process/Utility/lldb-riscv-register-enums.h"
+#include "Register/Arch/lldb-riscv-register-enums.h"
#include "llvm/Support/TargetSelect.h"
using namespace lldb;
diff --git a/lldb/unittests/ObjectFile/PECOFF/TestPECallFrameInfo.cpp b/lldb/unittests/ObjectFile/PECOFF/TestPECallFrameInfo.cpp
index 264678e4c4ed32..ab89d5f82df2a6 100644
--- a/lldb/unittests/ObjectFile/PECOFF/TestPECallFrameInfo.cpp
+++ b/lldb/unittests/ObjectFile/PECOFF/TestPECallFrameInfo.cpp
@@ -10,7 +10,7 @@
#include "gtest/gtest.h"
#include "Plugins/ObjectFile/PECOFF/ObjectFilePECOFF.h"
-#include "Plugins/Process/Utility/lldb-x86-register-enums.h"
+#include "Register/Arch/lldb-x86-register-enums.h"
#include "TestingSupport/SubsystemRAII.h"
#include "TestingSupport/TestUtilities.h"
diff --git a/lldb/unittests/ObjectFile/PECOFF/TestSectionSize.cpp b/lldb/unittests/ObjectFile/PECOFF/TestSectionSize.cpp
index 1a95a0d0fc4e97..0021169509b4da 100644
--- a/lldb/unittests/ObjectFile/PECOFF/TestSectionSize.cpp
+++ b/lldb/unittests/ObjectFile/PECOFF/TestSectionSize.cpp
@@ -10,7 +10,7 @@
#include "gtest/gtest.h"
#include "Plugins/ObjectFile/PECOFF/ObjectFilePECOFF.h"
-#include "Plugins/Process/Utility/lldb-x86-register-enums.h"
+#include "Register/Arch/lldb-x86-register-enums.h"
#include "TestingSupport/SubsystemRAII.h"
#include "TestingSupport/TestUtilities.h"
@@ -75,4 +75,3 @@ symbols: []
// without the zero padding, instead of SizeOfRawData (512).
EXPECT_EQ(section_data.GetByteSize(), (uint64_t)496);
}
-
diff --git a/lldb/unittests/Process/Utility/RegisterInfoFreeBSDTest.cpp b/lldb/unittests/Process/Utility/RegisterInfoFreeBSDTest.cpp
index f8be5f7262aa45..332100f5c9c8fd 100644
--- a/lldb/unittests/Process/Utility/RegisterInfoFreeBSDTest.cpp
+++ b/lldb/unittests/Process/Utility/RegisterInfoFreeBSDTest.cpp
@@ -17,15 +17,15 @@
#include "gmock/gmock.h"
#include "gtest/gtest.h"
-#include "Plugins/Process/Utility/RegisterInfoFreeBSD_i386.h"
-#include "Plugins/Process/Utility/RegisterInfoFreeBSD_powerpc.h"
-#include "Plugins/Process/Utility/RegisterInfoFreeBSD_x86_64.h"
+#include "Register/FreeBSD/RegisterInfoFreeBSD_i386.h"
+#include "Register/FreeBSD/RegisterInfoFreeBSD_powerpc.h"
+#include "Register/FreeBSD/RegisterInfoFreeBSD_x86_64.h"
#include "Plugins/Process/Utility/RegisterContextPOSIX_powerpc.h"
-#include "Plugins/Process/Utility/RegisterInfoCommon_arm.h"
-#include "Plugins/Process/Utility/RegisterInfoCommon_arm64.h"
-#include "Plugins/Process/Utility/lldb-arm-register-enums.h"
-#include "Plugins/Process/Utility/lldb-arm64-register-enums.h"
-#include "Plugins/Process/Utility/lldb-x86-register-enums.h"
+#include "Register/Common/RegisterInfoCommon_arm.h"
+#include "Register/Common/RegisterInfoCommon_arm64.h"
+#include "Register/Arch/lldb-arm-register-enums.h"
+#include "Register/Arch/lldb-arm64-register-enums.h"
+#include "Register/Arch/lldb-x86-register-enums.h"
using namespace lldb;
using namespace lldb_private;
diff --git a/lldb/unittests/Process/Utility/RegisterInfoNetBSDTest_i386.cpp b/lldb/unittests/Process/Utility/RegisterInfoNetBSDTest_i386.cpp
index e0947c7d05b244..784b4e75bb92a2 100644
--- a/lldb/unittests/Process/Utility/RegisterInfoNetBSDTest_i386.cpp
+++ b/lldb/unittests/Process/Utility/RegisterInfoNetBSDTest_i386.cpp
@@ -16,8 +16,8 @@
#include "gmock/gmock.h"
#include "gtest/gtest.h"
-#include "Plugins/Process/Utility/lldb-x86-register-enums.h"
-#include "Plugins/Process/Utility/RegisterInfoNetBSD_i386.h"
+#include "Register/Arch/lldb-x86-register-enums.h"
+#include "Register/NetBSD/RegisterInfoNetBSD_i386.h"
using namespace lldb;
using namespace lldb_private;
diff --git a/lldb/unittests/Process/Utility/RegisterInfoNetBSDTest_x86_64.cpp b/lldb/unittests/Process/Utility/RegisterInfoNetBSDTest_x86_64.cpp
index c0bfc01c6bf219..4c97a13434d29d 100644
--- a/lldb/unittests/Process/Utility/RegisterInfoNetBSDTest_x86_64.cpp
+++ b/lldb/unittests/Process/Utility/RegisterInfoNetBSDTest_x86_64.cpp
@@ -16,9 +16,9 @@
#include "gmock/gmock.h"
#include "gtest/gtest.h"
-#include "Plugins/Process/Utility/lldb-x86-register-enums.h"
-#include "Plugins/Process/Utility/RegisterInfoNetBSD_i386.h"
-#include "Plugins/Process/Utility/RegisterInfoNetBSD_x86_64.h"
+#include "Register/Arch/lldb-x86-register-enums.h"
+#include "Register/NetBSD/RegisterInfoNetBSD_i386.h"
+#include "Register/NetBSD/RegisterInfoNetBSD_x86_64.h"
using namespace lldb;
using namespace lldb_private;
diff --git a/lldb/unittests/Process/Utility/RegisterInfo_x86Test.cpp b/lldb/unittests/Process/Utility/RegisterInfo_x86Test.cpp
index 302fbbcbba9dec..9668e4ac6ed287 100644
--- a/lldb/unittests/Process/Utility/RegisterInfo_x86Test.cpp
+++ b/lldb/unittests/Process/Utility/RegisterInfo_x86Test.cpp
@@ -8,7 +8,7 @@
#include "gtest/gtest.h"
-#include "Plugins/Process/Utility/RegisterContext_x86.h"
+#include "Register/Arch/RegisterContext_x86.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/Support/FormatVariadic.h"
diff --git a/lldb/unittests/Process/minidump/RegisterContextMinidumpTest.cpp b/lldb/unittests/Process/minidump/RegisterContextMinidumpTest.cpp
index 18fb6ed001ff19..2a3ba654982e1e 100644
--- a/lldb/unittests/Process/minidump/RegisterContextMinidumpTest.cpp
+++ b/lldb/unittests/Process/minidump/RegisterContextMinidumpTest.cpp
@@ -6,8 +6,8 @@
//
//===----------------------------------------------------------------------===//
-#include "Plugins/Process/Utility/RegisterInfoLinux_i386.h"
-#include "Plugins/Process/Utility/RegisterInfoLinux_x86_64.h"
+#include "Register/Linux/RegisterInfoLinux_i386.h"
+#include "Register/Linux/RegisterInfoLinux_x86_64.h"
#include "Plugins/Process/minidump/RegisterContextMinidump_x86_32.h"
#include "Plugins/Process/minidump/RegisterContextMinidump_x86_64.h"
#include "Plugins/Process/minidump/RegisterContextMinidump_ARM.h"
diff --git a/lldb/unittests/Symbol/TestDWARFCallFrameInfo.cpp b/lldb/unittests/Symbol/TestDWARFCallFrameInfo.cpp
index c52e9a7387e14d..d2c258712c1efc 100644
--- a/lldb/unittests/Symbol/TestDWARFCallFrameInfo.cpp
+++ b/lldb/unittests/Symbol/TestDWARFCallFrameInfo.cpp
@@ -11,7 +11,7 @@
#include "gtest/gtest.h"
#include "Plugins/ObjectFile/ELF/ObjectFileELF.h"
-#include "Plugins/Process/Utility/RegisterContext_x86.h"
+#include "Register/Arch/RegisterContext_x86.h"
#include "Plugins/SymbolFile/Symtab/SymbolFileSymtab.h"
#include "TestingSupport/SubsystemRAII.h"
#include "TestingSupport/TestUtilities.h"
diff --git a/lldb/unittests/UnwindAssembly/ARM64/TestArm64InstEmulation.cpp b/lldb/unittests/UnwindAssembly/ARM64/TestArm64InstEmulation.cpp
index 12a1d2d015d508..94485c91f6154b 100644
--- a/lldb/unittests/UnwindAssembly/ARM64/TestArm64InstEmulation.cpp
+++ b/lldb/unittests/UnwindAssembly/ARM64/TestArm64InstEmulation.cpp
@@ -32,6 +32,7 @@
#include "lldb/Symbol/Symbol.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/Support/FormatVariadic.h"
+#include "Register/Arch/lldb-arm64-register-enums.h"
#include "llvm/Support/TargetSelect.h"
using namespace lldb;
diff --git a/lldb/unittests/UnwindAssembly/PPC64/TestPPC64InstEmulation.cpp b/lldb/unittests/UnwindAssembly/PPC64/TestPPC64InstEmulation.cpp
index 1a528da620779c..a8295a7e2edf6c 100644
--- a/lldb/unittests/UnwindAssembly/PPC64/TestPPC64InstEmulation.cpp
+++ b/lldb/unittests/UnwindAssembly/PPC64/TestPPC64InstEmulation.cpp
@@ -20,7 +20,7 @@
#include "Plugins/Disassembler/LLVMC/DisassemblerLLVMC.h"
#include "Plugins/Instruction/PPC64/EmulateInstructionPPC64.h"
-#include "Plugins/Process/Utility/lldb-ppc64le-register-enums.h"
+#include "Register/Arch/lldb-ppc64le-register-enums.h"
#include "llvm/Support/TargetSelect.h"
using namespace lldb;
diff --git a/llvm/utils/gn/secondary/lldb/source/Plugins/Process/Utility/BUILD.gn b/llvm/utils/gn/secondary/lldb/source/Plugins/Process/Utility/BUILD.gn
index 88841256310bf6..59c70635001112 100644
--- a/llvm/utils/gn/secondary/lldb/source/Plugins/Process/Utility/BUILD.gn
+++ b/llvm/utils/gn/secondary/lldb/source/Plugins/Process/Utility/BUILD.gn
@@ -1,46 +1,8 @@
-static_library("Register") {
- output_name = "lldbRegister"
- configs += [ "//llvm/utils/gn/build:lldb_code" ]
- deps = [
- "//lldb/source/Utility",
- "//llvm/lib/Support",
- "//llvm/lib/TargetParser",
- ]
-
- # Uses source-relative includes for own headers.
- include_dirs = [ "//lldb/source" ]
- sources = [
- "RegisterInfoFreeBSD_i386.cpp",
- "RegisterInfoFreeBSD_powerpc.cpp",
- "RegisterInfoFreeBSD_x86_64.cpp",
- "RegisterInfoLinux_i386.cpp",
- "RegisterInfoLinux_s390x.cpp",
- "RegisterInfoLinux_x86_64.cpp",
- "RegisterInfoNetBSD_i386.cpp",
- "RegisterInfoNetBSD_x86_64.cpp",
- "RegisterInfoOpenBSD_i386.cpp",
- "RegisterInfoOpenBSD_x86_64.cpp",
- "RegisterInfoWindows_i386.cpp",
- "RegisterInfoWindows_x86_64.cpp",
- "RegisterContext_x86.cpp",
- "RegisterInfoCommonDynamic_riscv32.cpp",
- "RegisterInfoCommon_arm.cpp",
- "RegisterInfoCommon_arm64.cpp",
- "RegisterInfoCommon_loongarch64.cpp",
- "RegisterInfoCommon_ppc64.cpp",
- "RegisterInfoCommon_ppc64le.cpp",
- "RegisterInfoCommon_riscv32.cpp",
- "RegisterInfoCommon_riscv64.cpp",
- "RegisterInfos_x86_64_with_base_shared.cpp",
- "RegisterTypeDetector_arm64.cpp",
- ]
-}
-
static_library("Utility") {
output_name = "lldbPluginProcessUtility"
configs += [ "//llvm/utils/gn/build:lldb_code" ]
deps = [
- ":Register",
+ "//lldb/source/Register",
#"//lldb/source/Breakpoint", # 3-hop dependency cycle.
"//lldb/source/Core",
"//lldb/source/DataFormatters",
diff --git a/llvm/utils/gn/secondary/lldb/source/Register/BUILD.gn b/llvm/utils/gn/secondary/lldb/source/Register/BUILD.gn
new file mode 100644
index 00000000000000..9d7da52abdff9a
--- /dev/null
+++ b/llvm/utils/gn/secondary/lldb/source/Register/BUILD.gn
@@ -0,0 +1,37 @@
+static_library("Register") {
+ output_name = "lldbRegister"
+ configs += [ "//llvm/utils/gn/build:lldb_code" ]
+ deps = [
+ "//lldb/source/Utility",
+ "//llvm/lib/Support",
+ "//llvm/lib/TargetParser",
+ ]
+
+ # Uses source-relative includes for own headers.
+ include_dirs = [ "//lldb/source" ]
+ sources = [
+ "Arch/RegisterContext_x86.cpp",
+ "Arch/RegisterInfos_x86_64_with_base_shared.cpp",
+ "Common/RegisterInfoCommonDynamic_riscv32.cpp",
+ "Common/RegisterInfoCommon_arm.cpp",
+ "Common/RegisterInfoCommon_arm64.cpp",
+ "Common/RegisterInfoCommon_loongarch64.cpp",
+ "Common/RegisterInfoCommon_ppc64.cpp",
+ "Common/RegisterInfoCommon_ppc64le.cpp",
+ "Common/RegisterInfoCommon_riscv32.cpp",
+ "Common/RegisterInfoCommon_riscv64.cpp",
+ "Common/RegisterTypeDetector_arm64.cpp",
+ "FreeBSD/RegisterInfoFreeBSD_i386.cpp",
+ "FreeBSD/RegisterInfoFreeBSD_powerpc.cpp",
+ "FreeBSD/RegisterInfoFreeBSD_x86_64.cpp",
+ "Linux/RegisterInfoLinux_i386.cpp",
+ "Linux/RegisterInfoLinux_s390x.cpp",
+ "Linux/RegisterInfoLinux_x86_64.cpp",
+ "NetBSD/RegisterInfoNetBSD_i386.cpp",
+ "NetBSD/RegisterInfoNetBSD_x86_64.cpp",
+ "OpenBSD/RegisterInfoOpenBSD_i386.cpp",
+ "OpenBSD/RegisterInfoOpenBSD_x86_64.cpp",
+ "Windows/RegisterInfoWindows_i386.cpp",
+ "Windows/RegisterInfoWindows_x86_64.cpp",
+ ]
+}
>From 2ff0fdb608234eb139e05b7768bd8874e2b25045 Mon Sep 17 00:00:00 2001
From: Minsoo Choo <minsoo at minsoo.io>
Date: Sun, 6 Sep 2026 09:59:29 -0400
Subject: [PATCH 3/5] [lldb] Extract native process support
---
.../source/Plugins/Process/AIX/CMakeLists.txt | 1 +
.../Process/AIX/NativeRegisterContextAIX.h | 2 +-
lldb/source/Plugins/Process/CMakeLists.txt | 1 +
.../Plugins/Process/FreeBSD/CMakeLists.txt | 1 +
.../FreeBSD/NativeRegisterContextFreeBSD.h | 2 +-
.../NativeRegisterContextFreeBSD_arm64.h | 2 +-
.../NativeRegisterContextFreeBSD_x86.h | 2 +-
.../Plugins/Process/Linux/CMakeLists.txt | 1 +
.../Linux/NativeRegisterContextLinux.h | 2 +-
.../Linux/NativeRegisterContextLinux_arm.h | 2 +-
.../Linux/NativeRegisterContextLinux_arm64.h | 2 +-
.../NativeRegisterContextLinux_arm64dbreg.h | 2 +-
.../NativeRegisterContextLinux_loongarch64.h | 2 +-
.../Linux/NativeRegisterContextLinux_x86.h | 2 +-
.../Process/NativeCommon/CMakeLists.txt | 21 +
.../NativeRegisterContextDBReg.cpp | 410 ++++++++++++++++++
.../NativeRegisterContextDBReg.h | 8 +-
.../NativeRegisterContextDBReg_arm.cpp | 0
.../NativeRegisterContextDBReg_arm.h | 8 +-
.../NativeRegisterContextDBReg_arm64.cpp | 0
.../NativeRegisterContextDBReg_arm64.h | 8 +-
.../NativeRegisterContextDBReg_loongarch.cpp | 0
.../NativeRegisterContextDBReg_loongarch.h | 8 +-
.../NativeRegisterContextDBReg_x86.cpp | 0
.../NativeRegisterContextDBReg_x86.h | 8 +-
.../NativeRegisterContextRegisterInfo.cpp | 0
.../NativeRegisterContextRegisterInfo.h | 6 +-
.../Plugins/Process/NetBSD/CMakeLists.txt | 1 +
.../NetBSD/NativeRegisterContextNetBSD.h | 2 +-
.../NetBSD/NativeRegisterContextNetBSD_x86.h | 2 +-
.../Plugins/Process/Utility/CMakeLists.txt | 6 -
.../Process/Windows/Common/CMakeLists.txt | 1 +
.../Common/NativeRegisterContextWindows.h | 2 +-
.../NativeRegisterContextWindows_arm64.h | 2 +-
.../RegisterInfos_x86_64_with_base_shared.h | 3 +-
.../source/Plugins/Process/Linux/BUILD.gn | 1 +
.../Plugins/Process/NativeCommon/BUILD.gn | 22 +
.../source/Plugins/Process/Utility/BUILD.gn | 6 -
.../Plugins/Process/Windows/Common/BUILD.gn | 1 +
39 files changed, 499 insertions(+), 51 deletions(-)
create mode 100644 lldb/source/Plugins/Process/NativeCommon/CMakeLists.txt
create mode 100644 lldb/source/Plugins/Process/NativeCommon/NativeRegisterContextDBReg.cpp
rename lldb/source/Plugins/Process/{Utility => NativeCommon}/NativeRegisterContextDBReg.h (91%)
rename lldb/source/Plugins/Process/{Utility => NativeCommon}/NativeRegisterContextDBReg_arm.cpp (100%)
rename lldb/source/Plugins/Process/{Utility => NativeCommon}/NativeRegisterContextDBReg_arm.h (78%)
rename lldb/source/Plugins/Process/{Utility => NativeCommon}/NativeRegisterContextDBReg_arm64.cpp (100%)
rename lldb/source/Plugins/Process/{Utility => NativeCommon}/NativeRegisterContextDBReg_arm64.h (73%)
rename lldb/source/Plugins/Process/{Utility => NativeCommon}/NativeRegisterContextDBReg_loongarch.cpp (100%)
rename lldb/source/Plugins/Process/{Utility => NativeCommon}/NativeRegisterContextDBReg_loongarch.h (73%)
rename lldb/source/Plugins/Process/{Utility => NativeCommon}/NativeRegisterContextDBReg_x86.cpp (100%)
rename lldb/source/Plugins/Process/{Utility => NativeCommon}/NativeRegisterContextDBReg_x86.h (81%)
rename lldb/source/Plugins/Process/{Utility => NativeCommon}/NativeRegisterContextRegisterInfo.cpp (100%)
rename lldb/source/Plugins/Process/{Utility => NativeCommon}/NativeRegisterContextRegisterInfo.h (85%)
create mode 100644 llvm/utils/gn/secondary/lldb/source/Plugins/Process/NativeCommon/BUILD.gn
diff --git a/lldb/source/Plugins/Process/AIX/CMakeLists.txt b/lldb/source/Plugins/Process/AIX/CMakeLists.txt
index f1f91218227363..3ca961eebac26c 100644
--- a/lldb/source/Plugins/Process/AIX/CMakeLists.txt
+++ b/lldb/source/Plugins/Process/AIX/CMakeLists.txt
@@ -7,6 +7,7 @@ add_lldb_library(lldbPluginProcessAIX
LINK_COMPONENTS
Support
LINK_LIBS
+ lldbNativeProcessSupport
lldbCore
lldbHost
lldbSymbol
diff --git a/lldb/source/Plugins/Process/AIX/NativeRegisterContextAIX.h b/lldb/source/Plugins/Process/AIX/NativeRegisterContextAIX.h
index 1f4f79627db413..c4af6f3d5b392a 100644
--- a/lldb/source/Plugins/Process/AIX/NativeRegisterContextAIX.h
+++ b/lldb/source/Plugins/Process/AIX/NativeRegisterContextAIX.h
@@ -9,7 +9,7 @@
#ifndef LLDB_SOURCE_PLUGINS_PROCESS_AIX_NATIVEREGISTERCONTEXTAIX_H
#define LLDB_SOURCE_PLUGINS_PROCESS_AIX_NATIVEREGISTERCONTEXTAIX_H
-#include "Plugins/Process/Utility/NativeRegisterContextRegisterInfo.h"
+#include "Plugins/Process/NativeCommon/NativeRegisterContextRegisterInfo.h"
namespace lldb_private::process_aix {
diff --git a/lldb/source/Plugins/Process/CMakeLists.txt b/lldb/source/Plugins/Process/CMakeLists.txt
index 84cc65e45157e4..1599da896aca08 100644
--- a/lldb/source/Plugins/Process/CMakeLists.txt
+++ b/lldb/source/Plugins/Process/CMakeLists.txt
@@ -23,6 +23,7 @@ endif()
add_subdirectory(FreeBSD-Kernel-Core)
add_subdirectory(MacOSX-Kernel)
+add_subdirectory(NativeCommon)
add_subdirectory(scripted)
add_subdirectory(gdb-remote)
add_subdirectory(Utility)
diff --git a/lldb/source/Plugins/Process/FreeBSD/CMakeLists.txt b/lldb/source/Plugins/Process/FreeBSD/CMakeLists.txt
index 559e6ff0dd570d..0599191d408581 100644
--- a/lldb/source/Plugins/Process/FreeBSD/CMakeLists.txt
+++ b/lldb/source/Plugins/Process/FreeBSD/CMakeLists.txt
@@ -10,6 +10,7 @@ add_lldb_library(lldbPluginProcessFreeBSD
LINK_COMPONENTS
Support
LINK_LIBS
+ lldbNativeProcessSupport
lldbHost
lldbSymbol
lldbTarget
diff --git a/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD.h b/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD.h
index b7f659ef24de2c..8bec2bc1f447e5 100644
--- a/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD.h
+++ b/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD.h
@@ -9,7 +9,7 @@
#ifndef lldb_NativeRegisterContextFreeBSD_h
#define lldb_NativeRegisterContextFreeBSD_h
-#include "Plugins/Process/Utility/NativeRegisterContextRegisterInfo.h"
+#include "Plugins/Process/NativeCommon/NativeRegisterContextRegisterInfo.h"
namespace lldb_private {
namespace process_freebsd {
diff --git a/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_arm64.h b/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_arm64.h
index b40507add17f3f..044e90c6a5eb48 100644
--- a/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_arm64.h
+++ b/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_arm64.h
@@ -18,7 +18,7 @@
// clang-format on
#include "Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD.h"
-#include "Plugins/Process/Utility/NativeRegisterContextDBReg_arm64.h"
+#include "Plugins/Process/NativeCommon/NativeRegisterContextDBReg_arm64.h"
#include "Register/Common/RegisterInfoCommon_arm64.h"
#include <array>
diff --git a/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_x86.h b/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_x86.h
index 9d86935d13c32a..ef628c2009eb33 100644
--- a/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_x86.h
+++ b/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_x86.h
@@ -22,7 +22,7 @@
#include <optional>
#include "Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD.h"
-#include "Plugins/Process/Utility/NativeRegisterContextDBReg_x86.h"
+#include "Plugins/Process/NativeCommon/NativeRegisterContextDBReg_x86.h"
#include "Register/Arch/RegisterContext_x86.h"
#include "Register/Arch/lldb-x86-register-enums.h"
diff --git a/lldb/source/Plugins/Process/Linux/CMakeLists.txt b/lldb/source/Plugins/Process/Linux/CMakeLists.txt
index ce624a5211b056..b77b203fb295c8 100644
--- a/lldb/source/Plugins/Process/Linux/CMakeLists.txt
+++ b/lldb/source/Plugins/Process/Linux/CMakeLists.txt
@@ -23,6 +23,7 @@ add_lldb_library(lldbPluginProcessLinux
Support
TargetParser
LINK_LIBS
+ lldbNativeProcessSupport
lldbCore
lldbHost
lldbSymbol
diff --git a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux.h b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux.h
index 797eacc3bdd0f0..b18e308ad0b345 100644
--- a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux.h
+++ b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux.h
@@ -9,7 +9,7 @@
#ifndef lldb_NativeRegisterContextLinux_h
#define lldb_NativeRegisterContextLinux_h
-#include "Plugins/Process/Utility/NativeRegisterContextRegisterInfo.h"
+#include "Plugins/Process/NativeCommon/NativeRegisterContextRegisterInfo.h"
#include "lldb/Host/common/NativeThreadProtocol.h"
#include "lldb/Target/MemoryTagManager.h"
#include "llvm/Support/Error.h"
diff --git a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm.h b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm.h
index 949a27fc5c139e..d813809a9afb4f 100644
--- a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm.h
+++ b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm.h
@@ -12,7 +12,7 @@
#define lldb_NativeRegisterContextLinux_arm_h
#include "Plugins/Process/Linux/NativeRegisterContextLinux.h"
-#include "Plugins/Process/Utility/NativeRegisterContextDBReg_arm.h"
+#include "Plugins/Process/NativeCommon/NativeRegisterContextDBReg_arm.h"
#include "Register/Common/RegisterInfoCommon_arm.h"
#include "Register/Arch/lldb-arm-register-enums.h"
diff --git a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
index 44d3b191d509a5..117666eea20636 100644
--- a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
+++ b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64.h
@@ -13,7 +13,7 @@
#include "Plugins/Process/Linux/NativeRegisterContextLinux.h"
#include "Plugins/Process/Utility/LinuxPTraceDefines_arm64sve.h"
-#include "Plugins/Process/Utility/NativeRegisterContextDBReg_arm64.h"
+#include "Plugins/Process/NativeCommon/NativeRegisterContextDBReg_arm64.h"
#include "Register/Common/RegisterInfoCommon_arm64.h"
#include "llvm/ADT/BitmaskEnum.h"
diff --git a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64dbreg.h b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64dbreg.h
index bca217851858de..2026d6e19eca9f 100644
--- a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64dbreg.h
+++ b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm64dbreg.h
@@ -12,7 +12,7 @@
// context for 64-bit server.
#include "Plugins/Process/Linux/NativeProcessLinux.h"
-#include "Plugins/Process/Utility/NativeRegisterContextDBReg.h"
+#include "Plugins/Process/NativeCommon/NativeRegisterContextDBReg.h"
#include "lldb/Utility/Status.h"
namespace lldb_private {
diff --git a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_loongarch64.h b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_loongarch64.h
index 1ee8ffa8681f23..5e081dbbdaae0c 100644
--- a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_loongarch64.h
+++ b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_loongarch64.h
@@ -12,7 +12,7 @@
#define lldb_NativeRegisterContextLinux_loongarch64_h
#include "Plugins/Process/Linux/NativeRegisterContextLinux.h"
-#include "Plugins/Process/Utility/NativeRegisterContextDBReg_loongarch.h"
+#include "Plugins/Process/NativeCommon/NativeRegisterContextDBReg_loongarch.h"
#include "Register/Common/RegisterInfoCommon_loongarch64.h"
#include <asm/ptrace.h>
diff --git a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86.h b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86.h
index b58ae5bebe95fa..60a471fd5d5e7c 100644
--- a/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86.h
+++ b/lldb/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86.h
@@ -12,7 +12,7 @@
#define lldb_NativeRegisterContextLinux_x86_h
#include "Plugins/Process/Linux/NativeRegisterContextLinux.h"
-#include "Plugins/Process/Utility/NativeRegisterContextDBReg_x86.h"
+#include "Plugins/Process/NativeCommon/NativeRegisterContextDBReg_x86.h"
#include "Register/Linux/RegisterInfoLinux_x86.h"
#include "Register/Arch/RegisterContext_x86.h"
#include "Register/Arch/lldb-x86-register-enums.h"
diff --git a/lldb/source/Plugins/Process/NativeCommon/CMakeLists.txt b/lldb/source/Plugins/Process/NativeCommon/CMakeLists.txt
new file mode 100644
index 00000000000000..fecf53fad414f5
--- /dev/null
+++ b/lldb/source/Plugins/Process/NativeCommon/CMakeLists.txt
@@ -0,0 +1,21 @@
+add_lldb_library(lldbNativeProcessSupport NO_PLUGIN_DEPENDENCIES
+ NativeRegisterContextDBReg.cpp
+ NativeRegisterContextDBReg_arm.cpp
+ NativeRegisterContextDBReg_arm64.cpp
+ NativeRegisterContextDBReg_loongarch.cpp
+ NativeRegisterContextDBReg_x86.cpp
+ NativeRegisterContextRegisterInfo.cpp
+
+ LINK_COMPONENTS
+ Support
+ LINK_LIBS
+ lldbCore
+ lldbHost
+ lldbRegister
+ lldbUtility
+ ALLOWED_INTERNAL_DEPENDENCIES
+ lldbCore
+ lldbHost
+ lldbRegister
+ lldbUtility
+ )
diff --git a/lldb/source/Plugins/Process/NativeCommon/NativeRegisterContextDBReg.cpp b/lldb/source/Plugins/Process/NativeCommon/NativeRegisterContextDBReg.cpp
new file mode 100644
index 00000000000000..f35027e9351401
--- /dev/null
+++ b/lldb/source/Plugins/Process/NativeCommon/NativeRegisterContextDBReg.cpp
@@ -0,0 +1,410 @@
+//===-- NativeRegisterContextDBReg.cpp ------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "NativeRegisterContextDBReg.h"
+
+#include "lldb/Utility/LLDBLog.h"
+#include "lldb/Utility/Log.h"
+#include "lldb/Utility/RegisterValue.h"
+
+using namespace lldb_private;
+
+uint32_t NativeRegisterContextDBReg::NumSupportedHardwareBreakpoints() {
+ Log *log = GetLog(LLDBLog::Breakpoints);
+
+ // Read hardware breakpoint and watchpoint information.
+ llvm::Error error = ReadHardwareDebugInfo();
+
+ if (error) {
+ LLDB_LOG_ERROR(log, std::move(error),
+ "failed to read debug registers: {0}");
+ return 0;
+ }
+
+ LLDB_LOG(log, "{0}", m_max_hbp_supported);
+ return m_max_hbp_supported;
+}
+
+uint32_t NativeRegisterContextDBReg::SetHardwareBreakpoint(lldb::addr_t addr,
+ size_t size) {
+ Log *log = GetLog(LLDBLog::Breakpoints);
+ LLDB_LOG(log, "addr: {0:x}, size: {1:x}", addr, size);
+
+ // Read hardware breakpoint and watchpoint information.
+ llvm::Error error = ReadHardwareDebugInfo();
+ if (error) {
+ LLDB_LOG_ERROR(
+ log, std::move(error),
+ "unable to set breakpoint: failed to read debug registers: {0}");
+ return LLDB_INVALID_INDEX32;
+ }
+
+ if (!ValidateBreakpoint(size, addr))
+ return LLDB_INVALID_INDEX32;
+
+ uint32_t control_value = MakeBreakControlValue(size);
+ auto details = AdjustBreakpoint({size, addr});
+ size = details.size;
+ addr = details.addr;
+
+ // Iterate over stored breakpoints and find a free bp_index
+ uint32_t bp_index = LLDB_INVALID_INDEX32;
+ for (uint32_t i = 0; i < m_max_hbp_supported; i++) {
+ if (!BreakpointIsEnabled(i))
+ bp_index = i; // Mark last free slot
+ else if (m_hbp_regs[i].address == addr)
+ return LLDB_INVALID_INDEX32; // We do not support duplicate breakpoints.
+ }
+
+ if (bp_index == LLDB_INVALID_INDEX32)
+ return LLDB_INVALID_INDEX32;
+
+ // Update breakpoint in local cache
+ m_hbp_regs[bp_index].real_addr = addr;
+ m_hbp_regs[bp_index].address = addr;
+ m_hbp_regs[bp_index].control = control_value;
+
+ // PTRACE call to set corresponding hardware breakpoint register.
+ error = WriteHardwareDebugRegs(eDREGTypeBREAK);
+
+ if (error) {
+ m_hbp_regs[bp_index].address = 0;
+ m_hbp_regs[bp_index].control &= ~m_hw_dbg_enable_bit;
+
+ LLDB_LOG_ERROR(
+ log, std::move(error),
+ "unable to set breakpoint: failed to write debug registers: {0}");
+ return LLDB_INVALID_INDEX32;
+ }
+
+ return bp_index;
+}
+
+bool NativeRegisterContextDBReg::ClearHardwareBreakpoint(uint32_t hw_idx) {
+ Log *log = GetLog(LLDBLog::Breakpoints);
+ LLDB_LOG(log, "hw_idx: {0}", hw_idx);
+
+ // Read hardware breakpoint and watchpoint information.
+ llvm::Error error = ReadHardwareDebugInfo();
+ if (error) {
+ LLDB_LOG_ERROR(
+ log, std::move(error),
+ "unable to clear breakpoint: failed to read debug registers: {0}");
+ return false;
+ }
+
+ if (hw_idx >= m_max_hbp_supported)
+ return false;
+
+ // Create a backup we can revert to in case of failure.
+ lldb::addr_t tempAddr = m_hbp_regs[hw_idx].address;
+ uint32_t tempControl = m_hbp_regs[hw_idx].control;
+
+ m_hbp_regs[hw_idx].control &= ~m_hw_dbg_enable_bit;
+ m_hbp_regs[hw_idx].address = 0;
+
+ // PTRACE call to clear corresponding hardware breakpoint register.
+ error = WriteHardwareDebugRegs(eDREGTypeBREAK);
+
+ if (error) {
+ m_hbp_regs[hw_idx].control = tempControl;
+ m_hbp_regs[hw_idx].address = tempAddr;
+
+ LLDB_LOG_ERROR(
+ log, std::move(error),
+ "unable to clear breakpoint: failed to write debug registers: {0}");
+ return false;
+ }
+
+ return true;
+}
+
+Status
+NativeRegisterContextDBReg::GetHardwareBreakHitIndex(uint32_t &bp_index,
+ lldb::addr_t trap_addr) {
+ Log *log = GetLog(LLDBLog::Breakpoints);
+
+ LLDB_LOGF(log, "NativeRegisterContextDBReg::%s()", __FUNCTION__);
+
+ lldb::addr_t break_addr;
+
+ for (bp_index = 0; bp_index < m_max_hbp_supported; ++bp_index) {
+ break_addr = m_hbp_regs[bp_index].address;
+
+ if (BreakpointIsEnabled(bp_index) && trap_addr == break_addr) {
+ m_hbp_regs[bp_index].hit_addr = trap_addr;
+ return Status();
+ }
+ }
+
+ bp_index = LLDB_INVALID_INDEX32;
+ return Status();
+}
+
+Status NativeRegisterContextDBReg::ClearAllHardwareBreakpoints() {
+ Log *log = GetLog(LLDBLog::Breakpoints);
+
+ LLDB_LOGF(log, "NativeRegisterContextDBReg::%s()", __FUNCTION__);
+
+ // Read hardware breakpoint and watchpoint information.
+ llvm::Error error = ReadHardwareDebugInfo();
+ if (error)
+ return Status::FromError(std::move(error));
+
+ for (uint32_t i = 0; i < m_max_hbp_supported; i++) {
+ if (!BreakpointIsEnabled(i))
+ continue;
+ // Create a backup we can revert to in case of failure.
+ lldb::addr_t tempAddr = m_hbp_regs[i].address;
+ uint32_t tempControl = m_hbp_regs[i].control;
+
+ // Clear watchpoints in local cache
+ m_hbp_regs[i].control &= ~m_hw_dbg_enable_bit;
+ m_hbp_regs[i].address = 0;
+
+ // Ptrace call to update hardware debug registers
+ error = WriteHardwareDebugRegs(eDREGTypeBREAK);
+
+ if (error) {
+ m_hbp_regs[i].control = tempControl;
+ m_hbp_regs[i].address = tempAddr;
+
+ return Status::FromError(std::move(error));
+ }
+ }
+
+ return Status();
+}
+
+bool NativeRegisterContextDBReg::BreakpointIsEnabled(uint32_t bp_index) {
+ return ((m_hbp_regs[bp_index].control & m_hw_dbg_enable_bit) != 0);
+}
+
+uint32_t NativeRegisterContextDBReg::NumSupportedHardwareWatchpoints() {
+ Log *log = GetLog(LLDBLog::Watchpoints);
+ llvm::Error error = ReadHardwareDebugInfo();
+ if (error) {
+ LLDB_LOG_ERROR(log, std::move(error),
+ "failed to read debug registers: {0}");
+ return 0;
+ }
+
+ return m_max_hwp_supported;
+}
+
+uint32_t NativeRegisterContextDBReg::SetHardwareWatchpoint(
+ lldb::addr_t addr, size_t size, uint32_t watch_flags) {
+ Log *log = GetLog(LLDBLog::Watchpoints);
+ LLDB_LOG(log, "addr: {0:x}, size: {1:x} watch_flags: {2:x}", addr, size,
+ watch_flags);
+
+ // Read hardware breakpoint and watchpoint information.
+ llvm::Error error = ReadHardwareDebugInfo();
+ if (error) {
+ LLDB_LOG_ERROR(
+ log, std::move(error),
+ "unable to set watchpoint: failed to read debug registers: {0}");
+ return LLDB_INVALID_INDEX32;
+ }
+
+ uint32_t control_value = 0, wp_index = 0;
+ lldb::addr_t real_addr = addr;
+ WatchpointDetails details{size, addr};
+
+ auto adjusted = AdjustWatchpoint(details);
+ if (adjusted == std::nullopt)
+ return LLDB_INVALID_INDEX32;
+ size = adjusted->size;
+ addr = adjusted->addr;
+
+ // Check if we are setting watchpoint other than read/write/access Also
+ // update watchpoint flag to match ARM/AArch64/LoongArch write-read bit
+ // configuration.
+ switch (watch_flags) {
+ case lldb::eWatchpointKindWrite:
+ watch_flags = 2;
+ break;
+ case lldb::eWatchpointKindRead:
+ watch_flags = 1;
+ break;
+ case (lldb::eWatchpointKindRead | lldb::eWatchpointKindWrite):
+ break;
+ default:
+ return LLDB_INVALID_INDEX32;
+ }
+
+ control_value = MakeWatchControlValue(size, watch_flags);
+
+ // Iterate over stored watchpoints and find a free wp_index
+ wp_index = LLDB_INVALID_INDEX32;
+ for (uint32_t i = 0; i < m_max_hwp_supported; i++) {
+ if (!WatchpointIsEnabled(i))
+ wp_index = i; // Mark last free slot
+ else if (m_hwp_regs[i].address == addr) {
+ return LLDB_INVALID_INDEX32; // We do not support duplicate watchpoints.
+ }
+ }
+
+ if (wp_index == LLDB_INVALID_INDEX32)
+ return LLDB_INVALID_INDEX32;
+
+ // Update watchpoint in local cache
+ m_hwp_regs[wp_index].real_addr = real_addr;
+ m_hwp_regs[wp_index].address = addr;
+ m_hwp_regs[wp_index].control = control_value;
+
+ // PTRACE call to set corresponding watchpoint register.
+ error = WriteHardwareDebugRegs(eDREGTypeWATCH);
+
+ if (error) {
+ m_hwp_regs[wp_index].address = 0;
+ m_hwp_regs[wp_index].control &= ~m_hw_dbg_enable_bit;
+
+ LLDB_LOG_ERROR(
+ log, std::move(error),
+ "unable to set watchpoint: failed to write debug registers: {0}");
+ return LLDB_INVALID_INDEX32;
+ }
+
+ return wp_index;
+}
+
+bool NativeRegisterContextDBReg::ClearHardwareWatchpoint(uint32_t wp_index) {
+ Log *log = GetLog(LLDBLog::Watchpoints);
+ LLDB_LOG(log, "wp_index: {0}", wp_index);
+
+ // Read hardware breakpoint and watchpoint information.
+ llvm::Error error = ReadHardwareDebugInfo();
+ if (error) {
+ LLDB_LOG_ERROR(
+ log, std::move(error),
+ "unable to set watchpoint: failed to read debug registers: {0}");
+ return false;
+ }
+
+ if (wp_index >= m_max_hwp_supported)
+ return false;
+
+ // Create a backup we can revert to in case of failure.
+ lldb::addr_t tempAddr = m_hwp_regs[wp_index].address;
+ uint32_t tempControl = m_hwp_regs[wp_index].control;
+
+ // Update watchpoint in local cache
+ m_hwp_regs[wp_index].control &= ~m_hw_dbg_enable_bit;
+ m_hwp_regs[wp_index].address = 0;
+
+ // Ptrace call to update hardware debug registers
+ error = WriteHardwareDebugRegs(eDREGTypeWATCH);
+
+ if (error) {
+ m_hwp_regs[wp_index].control = tempControl;
+ m_hwp_regs[wp_index].address = tempAddr;
+
+ LLDB_LOG_ERROR(
+ log, std::move(error),
+ "unable to clear watchpoint: failed to read debug registers: {0}");
+ return false;
+ }
+
+ return true;
+}
+
+Status NativeRegisterContextDBReg::ClearAllHardwareWatchpoints() {
+ // Read hardware breakpoint and watchpoint information.
+ llvm::Error error = ReadHardwareDebugInfo();
+ if (error)
+ return Status::FromError(std::move(error));
+
+ for (uint32_t i = 0; i < m_max_hwp_supported; i++) {
+ if (!WatchpointIsEnabled(i))
+ continue;
+ // Create a backup we can revert to in case of failure.
+ lldb::addr_t tempAddr = m_hwp_regs[i].address;
+ uint32_t tempControl = m_hwp_regs[i].control;
+
+ // Clear watchpoints in local cache
+ m_hwp_regs[i].control = 0;
+ m_hwp_regs[i].address = 0;
+
+ // Ptrace call to update hardware debug registers
+ error = WriteHardwareDebugRegs(eDREGTypeWATCH);
+
+ if (error) {
+ m_hwp_regs[i].control = tempControl;
+ m_hwp_regs[i].address = tempAddr;
+
+ return Status::FromError(std::move(error));
+ }
+ }
+
+ return Status();
+}
+
+Status
+NativeRegisterContextDBReg::GetWatchpointHitIndex(uint32_t &wp_index,
+ lldb::addr_t trap_addr) {
+ Log *log = GetLog(LLDBLog::Watchpoints);
+ LLDB_LOG(log, "wp_index: {0}, trap_addr: {1:x}", wp_index, trap_addr);
+
+ // Read hardware breakpoint and watchpoint information.
+ llvm::Error error = ReadHardwareDebugInfo();
+ if (error)
+ return Status::FromError(std::move(error));
+
+ // AArch64 need mask off ignored bits from watchpoint trap address.
+ trap_addr = FixWatchpointHitAddress(trap_addr);
+
+ uint32_t watch_size;
+ lldb::addr_t watch_addr;
+
+ for (wp_index = 0; wp_index < m_max_hwp_supported; ++wp_index) {
+ watch_size = GetWatchpointSize(wp_index);
+ watch_addr = m_hwp_regs[wp_index].address;
+
+ if (WatchpointIsEnabled(wp_index) && trap_addr >= watch_addr &&
+ trap_addr < watch_addr + watch_size) {
+ m_hwp_regs[wp_index].hit_addr = trap_addr;
+ return Status();
+ }
+ }
+
+ wp_index = LLDB_INVALID_INDEX32;
+ return Status();
+}
+
+bool NativeRegisterContextDBReg::WatchpointIsEnabled(uint32_t wp_index) {
+ Log *log = GetLog(LLDBLog::Watchpoints);
+ LLDB_LOG(log, "wp_index: {0}", wp_index);
+ return ((m_hwp_regs[wp_index].control & m_hw_dbg_enable_bit) != 0);
+}
+
+lldb::addr_t
+NativeRegisterContextDBReg::GetWatchpointAddress(uint32_t wp_index) {
+ Log *log = GetLog(LLDBLog::Watchpoints);
+ LLDB_LOG(log, "wp_index: {0}", wp_index);
+
+ if (wp_index >= m_max_hwp_supported)
+ return LLDB_INVALID_ADDRESS;
+
+ if (WatchpointIsEnabled(wp_index))
+ return m_hwp_regs[wp_index].real_addr;
+ return LLDB_INVALID_ADDRESS;
+}
+
+lldb::addr_t
+NativeRegisterContextDBReg::GetWatchpointHitAddress(uint32_t wp_index) {
+ Log *log = GetLog(LLDBLog::Watchpoints);
+ LLDB_LOG(log, "wp_index: {0}", wp_index);
+
+ if (wp_index >= m_max_hwp_supported)
+ return LLDB_INVALID_ADDRESS;
+
+ if (WatchpointIsEnabled(wp_index))
+ return m_hwp_regs[wp_index].hit_addr;
+ return LLDB_INVALID_ADDRESS;
+}
diff --git a/lldb/source/Plugins/Process/Utility/NativeRegisterContextDBReg.h b/lldb/source/Plugins/Process/NativeCommon/NativeRegisterContextDBReg.h
similarity index 91%
rename from lldb/source/Plugins/Process/Utility/NativeRegisterContextDBReg.h
rename to lldb/source/Plugins/Process/NativeCommon/NativeRegisterContextDBReg.h
index 60d1bfa38dd016..7599ca460d1573 100644
--- a/lldb/source/Plugins/Process/Utility/NativeRegisterContextDBReg.h
+++ b/lldb/source/Plugins/Process/NativeCommon/NativeRegisterContextDBReg.h
@@ -6,10 +6,10 @@
//
//===----------------------------------------------------------------------===//
-#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_NATIVEREGISTERCONTEXTDBREG_H
-#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_NATIVEREGISTERCONTEXTDBREG_H
+#ifndef LLDB_SOURCE_PLUGINS_PROCESS_NATIVECOMMON_NATIVEREGISTERCONTEXTDBREG_H
+#define LLDB_SOURCE_PLUGINS_PROCESS_NATIVECOMMON_NATIVEREGISTERCONTEXTDBREG_H
-#include "Plugins/Process/Utility/NativeRegisterContextRegisterInfo.h"
+#include "Plugins/Process/NativeCommon/NativeRegisterContextRegisterInfo.h"
#include <array>
#include <optional>
@@ -105,4 +105,4 @@ class NativeRegisterContextDBReg
} // namespace lldb_private
-#endif // LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_NATIVEREGISTERCONTEXTDBREG_H
+#endif // LLDB_SOURCE_PLUGINS_PROCESS_NATIVECOMMON_NATIVEREGISTERCONTEXTDBREG_H
diff --git a/lldb/source/Plugins/Process/Utility/NativeRegisterContextDBReg_arm.cpp b/lldb/source/Plugins/Process/NativeCommon/NativeRegisterContextDBReg_arm.cpp
similarity index 100%
rename from lldb/source/Plugins/Process/Utility/NativeRegisterContextDBReg_arm.cpp
rename to lldb/source/Plugins/Process/NativeCommon/NativeRegisterContextDBReg_arm.cpp
diff --git a/lldb/source/Plugins/Process/Utility/NativeRegisterContextDBReg_arm.h b/lldb/source/Plugins/Process/NativeCommon/NativeRegisterContextDBReg_arm.h
similarity index 78%
rename from lldb/source/Plugins/Process/Utility/NativeRegisterContextDBReg_arm.h
rename to lldb/source/Plugins/Process/NativeCommon/NativeRegisterContextDBReg_arm.h
index 0d1de2ae2d89b8..38fcf6034e1d76 100644
--- a/lldb/source/Plugins/Process/Utility/NativeRegisterContextDBReg_arm.h
+++ b/lldb/source/Plugins/Process/NativeCommon/NativeRegisterContextDBReg_arm.h
@@ -6,10 +6,10 @@
//
//===----------------------------------------------------------------------===//
-#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_NATIVEREGISTERCONTEXTDBREG_ARM_H
-#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_NATIVEREGISTERCONTEXTDBREG_ARM_H
+#ifndef LLDB_SOURCE_PLUGINS_PROCESS_NATIVECOMMON_NATIVEREGISTERCONTEXTDBREG_ARM_H
+#define LLDB_SOURCE_PLUGINS_PROCESS_NATIVECOMMON_NATIVEREGISTERCONTEXTDBREG_ARM_H
-#include "Plugins/Process/Utility/NativeRegisterContextDBReg.h"
+#include "Plugins/Process/NativeCommon/NativeRegisterContextDBReg.h"
namespace lldb_private {
@@ -39,4 +39,4 @@ class NativeRegisterContextDBReg_arm : public NativeRegisterContextDBReg {
} // namespace lldb_private
-#endif // LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_NATIVEREGISTERCONTEXTDBREG_ARM_H
+#endif // LLDB_SOURCE_PLUGINS_PROCESS_NATIVECOMMON_NATIVEREGISTERCONTEXTDBREG_ARM_H
diff --git a/lldb/source/Plugins/Process/Utility/NativeRegisterContextDBReg_arm64.cpp b/lldb/source/Plugins/Process/NativeCommon/NativeRegisterContextDBReg_arm64.cpp
similarity index 100%
rename from lldb/source/Plugins/Process/Utility/NativeRegisterContextDBReg_arm64.cpp
rename to lldb/source/Plugins/Process/NativeCommon/NativeRegisterContextDBReg_arm64.cpp
diff --git a/lldb/source/Plugins/Process/Utility/NativeRegisterContextDBReg_arm64.h b/lldb/source/Plugins/Process/NativeCommon/NativeRegisterContextDBReg_arm64.h
similarity index 73%
rename from lldb/source/Plugins/Process/Utility/NativeRegisterContextDBReg_arm64.h
rename to lldb/source/Plugins/Process/NativeCommon/NativeRegisterContextDBReg_arm64.h
index 0dfa5e03fc27b9..8870570c15e306 100644
--- a/lldb/source/Plugins/Process/Utility/NativeRegisterContextDBReg_arm64.h
+++ b/lldb/source/Plugins/Process/NativeCommon/NativeRegisterContextDBReg_arm64.h
@@ -6,10 +6,10 @@
//
//===----------------------------------------------------------------------===//
-#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_NATIVEREGISTERCONTEXTDBREG_ARM64_H
-#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_NATIVEREGISTERCONTEXTDBREG_ARM64_H
+#ifndef LLDB_SOURCE_PLUGINS_PROCESS_NATIVECOMMON_NATIVEREGISTERCONTEXTDBREG_ARM64_H
+#define LLDB_SOURCE_PLUGINS_PROCESS_NATIVECOMMON_NATIVEREGISTERCONTEXTDBREG_ARM64_H
-#include "Plugins/Process/Utility/NativeRegisterContextDBReg.h"
+#include "Plugins/Process/NativeCommon/NativeRegisterContextDBReg.h"
namespace lldb_private {
@@ -31,4 +31,4 @@ class NativeRegisterContextDBReg_arm64 : public NativeRegisterContextDBReg {
} // namespace lldb_private
-#endif // LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_NATIVEREGISTERCONTEXTDBREG_ARM64_H
+#endif // LLDB_SOURCE_PLUGINS_PROCESS_NATIVECOMMON_NATIVEREGISTERCONTEXTDBREG_ARM64_H
diff --git a/lldb/source/Plugins/Process/Utility/NativeRegisterContextDBReg_loongarch.cpp b/lldb/source/Plugins/Process/NativeCommon/NativeRegisterContextDBReg_loongarch.cpp
similarity index 100%
rename from lldb/source/Plugins/Process/Utility/NativeRegisterContextDBReg_loongarch.cpp
rename to lldb/source/Plugins/Process/NativeCommon/NativeRegisterContextDBReg_loongarch.cpp
diff --git a/lldb/source/Plugins/Process/Utility/NativeRegisterContextDBReg_loongarch.h b/lldb/source/Plugins/Process/NativeCommon/NativeRegisterContextDBReg_loongarch.h
similarity index 73%
rename from lldb/source/Plugins/Process/Utility/NativeRegisterContextDBReg_loongarch.h
rename to lldb/source/Plugins/Process/NativeCommon/NativeRegisterContextDBReg_loongarch.h
index 703f41f3c298b0..bdedb6696e2b61 100644
--- a/lldb/source/Plugins/Process/Utility/NativeRegisterContextDBReg_loongarch.h
+++ b/lldb/source/Plugins/Process/NativeCommon/NativeRegisterContextDBReg_loongarch.h
@@ -6,10 +6,10 @@
//
//===----------------------------------------------------------------------===//
-#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_NATIVEREGISTERCONTEXTDBREG_LOONGARCH_H
-#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_NATIVEREGISTERCONTEXTDBREG_LOONGARCH_H
+#ifndef LLDB_SOURCE_PLUGINS_PROCESS_NATIVECOMMON_NATIVEREGISTERCONTEXTDBREG_LOONGARCH_H
+#define LLDB_SOURCE_PLUGINS_PROCESS_NATIVECOMMON_NATIVEREGISTERCONTEXTDBREG_LOONGARCH_H
-#include "Plugins/Process/Utility/NativeRegisterContextDBReg.h"
+#include "Plugins/Process/NativeCommon/NativeRegisterContextDBReg.h"
namespace lldb_private {
@@ -31,4 +31,4 @@ class NativeRegisterContextDBReg_loongarch : public NativeRegisterContextDBReg {
} // namespace lldb_private
-#endif // LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_NATIVEREGISTERCONTEXTDBREG_LOONGARCH_H
+#endif // LLDB_SOURCE_PLUGINS_PROCESS_NATIVECOMMON_NATIVEREGISTERCONTEXTDBREG_LOONGARCH_H
diff --git a/lldb/source/Plugins/Process/Utility/NativeRegisterContextDBReg_x86.cpp b/lldb/source/Plugins/Process/NativeCommon/NativeRegisterContextDBReg_x86.cpp
similarity index 100%
rename from lldb/source/Plugins/Process/Utility/NativeRegisterContextDBReg_x86.cpp
rename to lldb/source/Plugins/Process/NativeCommon/NativeRegisterContextDBReg_x86.cpp
diff --git a/lldb/source/Plugins/Process/Utility/NativeRegisterContextDBReg_x86.h b/lldb/source/Plugins/Process/NativeCommon/NativeRegisterContextDBReg_x86.h
similarity index 81%
rename from lldb/source/Plugins/Process/Utility/NativeRegisterContextDBReg_x86.h
rename to lldb/source/Plugins/Process/NativeCommon/NativeRegisterContextDBReg_x86.h
index 8a2c1a1dbcbe13..2f0d08513e6042 100644
--- a/lldb/source/Plugins/Process/Utility/NativeRegisterContextDBReg_x86.h
+++ b/lldb/source/Plugins/Process/NativeCommon/NativeRegisterContextDBReg_x86.h
@@ -6,10 +6,10 @@
//
//===----------------------------------------------------------------------===//
-#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_NATIVEREGISTERCONTEXTDBREG_X86_H
-#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_NATIVEREGISTERCONTEXTDBREG_X86_H
+#ifndef LLDB_SOURCE_PLUGINS_PROCESS_NATIVECOMMON_NATIVEREGISTERCONTEXTDBREG_X86_H
+#define LLDB_SOURCE_PLUGINS_PROCESS_NATIVECOMMON_NATIVEREGISTERCONTEXTDBREG_X86_H
-#include "Plugins/Process/Utility/NativeRegisterContextRegisterInfo.h"
+#include "Plugins/Process/NativeCommon/NativeRegisterContextRegisterInfo.h"
namespace lldb_private {
@@ -45,4 +45,4 @@ class NativeRegisterContextDBReg_x86
} // namespace lldb_private
-#endif // LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_NATIVEREGISTERCONTEXTDBREG_X86_H
+#endif // LLDB_SOURCE_PLUGINS_PROCESS_NATIVECOMMON_NATIVEREGISTERCONTEXTDBREG_X86_H
diff --git a/lldb/source/Plugins/Process/Utility/NativeRegisterContextRegisterInfo.cpp b/lldb/source/Plugins/Process/NativeCommon/NativeRegisterContextRegisterInfo.cpp
similarity index 100%
rename from lldb/source/Plugins/Process/Utility/NativeRegisterContextRegisterInfo.cpp
rename to lldb/source/Plugins/Process/NativeCommon/NativeRegisterContextRegisterInfo.cpp
diff --git a/lldb/source/Plugins/Process/Utility/NativeRegisterContextRegisterInfo.h b/lldb/source/Plugins/Process/NativeCommon/NativeRegisterContextRegisterInfo.h
similarity index 85%
rename from lldb/source/Plugins/Process/Utility/NativeRegisterContextRegisterInfo.h
rename to lldb/source/Plugins/Process/NativeCommon/NativeRegisterContextRegisterInfo.h
index 58a2a4843e4ec7..c66e3e1ed88676 100644
--- a/lldb/source/Plugins/Process/Utility/NativeRegisterContextRegisterInfo.h
+++ b/lldb/source/Plugins/Process/NativeCommon/NativeRegisterContextRegisterInfo.h
@@ -6,12 +6,12 @@
//
//===----------------------------------------------------------------------===//
-#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_NATIVEREGISTERCONTEXTREGISTERINFO_H
-#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_NATIVEREGISTERCONTEXTREGISTERINFO_H
+#ifndef LLDB_SOURCE_PLUGINS_PROCESS_NATIVECOMMON_NATIVEREGISTERCONTEXTREGISTERINFO_H
+#define LLDB_SOURCE_PLUGINS_PROCESS_NATIVECOMMON_NATIVEREGISTERCONTEXTREGISTERINFO_H
#include <memory>
-#include "RegisterInfoInterface.h"
+#include "Register/RegisterInfoInterface.h"
#include "lldb/Host/common/NativeRegisterContext.h"
namespace lldb_private {
diff --git a/lldb/source/Plugins/Process/NetBSD/CMakeLists.txt b/lldb/source/Plugins/Process/NetBSD/CMakeLists.txt
index 438e6b6c2a3c7c..df09a2c6e19320 100644
--- a/lldb/source/Plugins/Process/NetBSD/CMakeLists.txt
+++ b/lldb/source/Plugins/Process/NetBSD/CMakeLists.txt
@@ -7,6 +7,7 @@ add_lldb_library(lldbPluginProcessNetBSD
LINK_COMPONENTS
Support
LINK_LIBS
+ lldbNativeProcessSupport
lldbHost
lldbSymbol
lldbTarget
diff --git a/lldb/source/Plugins/Process/NetBSD/NativeRegisterContextNetBSD.h b/lldb/source/Plugins/Process/NetBSD/NativeRegisterContextNetBSD.h
index 08490aad9e0ba1..35c0e12ea77e64 100644
--- a/lldb/source/Plugins/Process/NetBSD/NativeRegisterContextNetBSD.h
+++ b/lldb/source/Plugins/Process/NetBSD/NativeRegisterContextNetBSD.h
@@ -11,7 +11,7 @@
#include "lldb/Host/common/NativeThreadProtocol.h"
-#include "Plugins/Process/Utility/NativeRegisterContextRegisterInfo.h"
+#include "Plugins/Process/NativeCommon/NativeRegisterContextRegisterInfo.h"
namespace lldb_private {
namespace process_netbsd {
diff --git a/lldb/source/Plugins/Process/NetBSD/NativeRegisterContextNetBSD_x86.h b/lldb/source/Plugins/Process/NetBSD/NativeRegisterContextNetBSD_x86.h
index dba5ac78f67d39..e4bf9ac5b691ab 100644
--- a/lldb/source/Plugins/Process/NetBSD/NativeRegisterContextNetBSD_x86.h
+++ b/lldb/source/Plugins/Process/NetBSD/NativeRegisterContextNetBSD_x86.h
@@ -23,7 +23,7 @@
#include "Plugins/Process/NetBSD/NativeRegisterContextNetBSD.h"
#include "Register/Arch/RegisterContext_x86.h"
-#include "Plugins/Process/Utility/NativeRegisterContextDBReg_x86.h"
+#include "Plugins/Process/NativeCommon/NativeRegisterContextDBReg_x86.h"
#include "Register/Arch/lldb-x86-register-enums.h"
namespace lldb_private {
diff --git a/lldb/source/Plugins/Process/Utility/CMakeLists.txt b/lldb/source/Plugins/Process/Utility/CMakeLists.txt
index 19a65bfa4fde1f..e74e17971d0356 100644
--- a/lldb/source/Plugins/Process/Utility/CMakeLists.txt
+++ b/lldb/source/Plugins/Process/Utility/CMakeLists.txt
@@ -12,12 +12,6 @@ add_lldb_library(lldbPluginProcessUtility
LinuxSignals.cpp
MemoryTagManagerAArch64MTE.cpp
NativeProcessSoftwareSingleStep.cpp
- NativeRegisterContextDBReg.cpp
- NativeRegisterContextDBReg_arm.cpp
- NativeRegisterContextDBReg_arm64.cpp
- NativeRegisterContextDBReg_loongarch.cpp
- NativeRegisterContextDBReg_x86.cpp
- NativeRegisterContextRegisterInfo.cpp
NetBSDSignals.cpp
OpenBSDSignals.cpp
RegisterContextDarwin_arm.cpp
diff --git a/lldb/source/Plugins/Process/Windows/Common/CMakeLists.txt b/lldb/source/Plugins/Process/Windows/Common/CMakeLists.txt
index c6d8713a831599..913f5dec8e4830 100644
--- a/lldb/source/Plugins/Process/Windows/Common/CMakeLists.txt
+++ b/lldb/source/Plugins/Process/Windows/Common/CMakeLists.txt
@@ -24,6 +24,7 @@ add_lldb_library(lldbPluginProcessWindowsCommon PLUGIN
LINK_COMPONENTS
Support
LINK_LIBS
+ lldbNativeProcessSupport
lldbCore
lldbHost
lldbInterpreter
diff --git a/lldb/source/Plugins/Process/Windows/Common/NativeRegisterContextWindows.h b/lldb/source/Plugins/Process/Windows/Common/NativeRegisterContextWindows.h
index 2b71f639d562e9..051e685c52c999 100644
--- a/lldb/source/Plugins/Process/Windows/Common/NativeRegisterContextWindows.h
+++ b/lldb/source/Plugins/Process/Windows/Common/NativeRegisterContextWindows.h
@@ -9,7 +9,7 @@
#ifndef liblldb_NativeRegisterContextWindows_h_
#define liblldb_NativeRegisterContextWindows_h_
-#include "Plugins/Process/Utility/NativeRegisterContextRegisterInfo.h"
+#include "Plugins/Process/NativeCommon/NativeRegisterContextRegisterInfo.h"
#include "lldb/Host/common/NativeThreadProtocol.h"
#include "lldb/Utility/DataBufferHeap.h"
diff --git a/lldb/source/Plugins/Process/Windows/Common/NativeRegisterContextWindows_arm64.h b/lldb/source/Plugins/Process/Windows/Common/NativeRegisterContextWindows_arm64.h
index 970d4ce26c61f4..091d1946111a24 100644
--- a/lldb/source/Plugins/Process/Windows/Common/NativeRegisterContextWindows_arm64.h
+++ b/lldb/source/Plugins/Process/Windows/Common/NativeRegisterContextWindows_arm64.h
@@ -12,7 +12,7 @@
#include "NativeRegisterContextWindows.h"
-#include "Plugins/Process/Utility/NativeRegisterContextDBReg_arm64.h"
+#include "Plugins/Process/NativeCommon/NativeRegisterContextDBReg_arm64.h"
#include "Register/Common/RegisterInfoCommon_arm64.h"
#include "Register/Arch/lldb-arm64-register-enums.h"
diff --git a/lldb/source/Register/Arch/RegisterInfos_x86_64_with_base_shared.h b/lldb/source/Register/Arch/RegisterInfos_x86_64_with_base_shared.h
index 8486e1fe1eb5c1..e93c90e9c880cd 100644
--- a/lldb/source/Register/Arch/RegisterInfos_x86_64_with_base_shared.h
+++ b/lldb/source/Register/Arch/RegisterInfos_x86_64_with_base_shared.h
@@ -7,13 +7,12 @@
//===----------------------------------------------------------------------===//
#include "Register/Arch/lldb-x86-register-enums.h"
+#include "llvm/TargetParser/Triple.h"
#include <stdint.h>
#ifndef lldb_RegisterInfos_x86_64_with_base_shared_h
#define lldb_RegisterInfos_x86_64_with_base_shared_h
-#include "Plugins/Process/Utility/NativeRegisterContextRegisterInfo.h"
-
namespace lldb_private {
struct RegisterInfos_x86_64_with_base_shared {
diff --git a/llvm/utils/gn/secondary/lldb/source/Plugins/Process/Linux/BUILD.gn b/llvm/utils/gn/secondary/lldb/source/Plugins/Process/Linux/BUILD.gn
index 90fd39410939b6..c0383a005d7056 100644
--- a/llvm/utils/gn/secondary/lldb/source/Plugins/Process/Linux/BUILD.gn
+++ b/llvm/utils/gn/secondary/lldb/source/Plugins/Process/Linux/BUILD.gn
@@ -4,6 +4,7 @@ static_library("Linux") {
deps = [
"//lldb/source/Core",
"//lldb/source/Host",
+ "//lldb/source/Plugins/Process/NativeCommon",
"//lldb/source/Plugins/Process/POSIX",
"//lldb/source/Plugins/Process/Utility",
"//lldb/source/Symbol",
diff --git a/llvm/utils/gn/secondary/lldb/source/Plugins/Process/NativeCommon/BUILD.gn b/llvm/utils/gn/secondary/lldb/source/Plugins/Process/NativeCommon/BUILD.gn
new file mode 100644
index 00000000000000..00e851d003b407
--- /dev/null
+++ b/llvm/utils/gn/secondary/lldb/source/Plugins/Process/NativeCommon/BUILD.gn
@@ -0,0 +1,22 @@
+static_library("NativeCommon") {
+ output_name = "lldbNativeProcessSupport"
+ configs += [ "//llvm/utils/gn/build:lldb_code" ]
+ deps = [
+ "//lldb/source/Core",
+ "//lldb/source/Host",
+ "//lldb/source/Register",
+ "//lldb/source/Utility",
+ "//llvm/lib/Support",
+ ]
+
+ # Uses source-relative includes for own headers.
+ include_dirs = [ "//lldb/source" ]
+ sources = [
+ "NativeRegisterContextDBReg.cpp",
+ "NativeRegisterContextDBReg_arm.cpp",
+ "NativeRegisterContextDBReg_arm64.cpp",
+ "NativeRegisterContextDBReg_loongarch.cpp",
+ "NativeRegisterContextDBReg_x86.cpp",
+ "NativeRegisterContextRegisterInfo.cpp",
+ ]
+}
diff --git a/llvm/utils/gn/secondary/lldb/source/Plugins/Process/Utility/BUILD.gn b/llvm/utils/gn/secondary/lldb/source/Plugins/Process/Utility/BUILD.gn
index 59c70635001112..175599f39f62ec 100644
--- a/llvm/utils/gn/secondary/lldb/source/Plugins/Process/Utility/BUILD.gn
+++ b/llvm/utils/gn/secondary/lldb/source/Plugins/Process/Utility/BUILD.gn
@@ -30,12 +30,6 @@ static_library("Utility") {
"LinuxSignals.cpp",
"MemoryTagManagerAArch64MTE.cpp",
"NativeProcessSoftwareSingleStep.cpp",
- "NativeRegisterContextDBReg.cpp",
- "NativeRegisterContextDBReg_arm.cpp",
- "NativeRegisterContextDBReg_arm64.cpp",
- "NativeRegisterContextDBReg_loongarch.cpp",
- "NativeRegisterContextDBReg_x86.cpp",
- "NativeRegisterContextRegisterInfo.cpp",
"NetBSDSignals.cpp",
"OpenBSDSignals.cpp",
"RegisterContextDarwin_arm.cpp",
diff --git a/llvm/utils/gn/secondary/lldb/source/Plugins/Process/Windows/Common/BUILD.gn b/llvm/utils/gn/secondary/lldb/source/Plugins/Process/Windows/Common/BUILD.gn
index 0fec9ee7eddd23..1b6275b27055f0 100644
--- a/llvm/utils/gn/secondary/lldb/source/Plugins/Process/Windows/Common/BUILD.gn
+++ b/llvm/utils/gn/secondary/lldb/source/Plugins/Process/Windows/Common/BUILD.gn
@@ -6,6 +6,7 @@ static_library("Common") {
"//lldb/source/Host",
"//lldb/source/Interpreter",
"//lldb/source/Plugins/DynamicLoader/Windows-DYLD",
+ "//lldb/source/Plugins/Process/NativeCommon",
"//lldb/source/Symbol",
"//lldb/source/Target",
"//llvm/lib/Support",
>From e87ea9f75437ccee7beab312fa75e398b41d459b Mon Sep 17 00:00:00 2001
From: Minsoo Choo <minsoo at minsoo.io>
Date: Sun, 6 Sep 2026 10:12:43 -0400
Subject: [PATCH 4/5] [lldb] Extract reusable POSIX register contexts
---
lldb/source/Plugins/Process/CMakeLists.txt | 1 +
.../Plugins/Process/Common/CMakeLists.txt | 22 ++
.../POSIX}/RegisterContextPOSIX_arm.cpp | 0
.../POSIX}/RegisterContextPOSIX_arm.h | 10 +-
.../POSIX}/RegisterContextPOSIX_arm64.cpp | 0
.../POSIX}/RegisterContextPOSIX_arm64.h | 10 +-
.../RegisterContextPOSIX_loongarch64.cpp | 0
.../POSIX}/RegisterContextPOSIX_loongarch64.h | 12 +-
.../POSIX}/RegisterContextPOSIX_powerpc.cpp | 0
.../POSIX/RegisterContextPOSIX_powerpc.h | 74 +++++++
.../POSIX}/RegisterContextPOSIX_ppc64le.cpp | 0
.../POSIX}/RegisterContextPOSIX_ppc64le.h | 8 +-
.../POSIX}/RegisterContextPOSIX_riscv32.cpp | 0
.../POSIX}/RegisterContextPOSIX_riscv32.h | 12 +-
.../POSIX}/RegisterContextPOSIX_riscv64.cpp | 0
.../POSIX}/RegisterContextPOSIX_riscv64.h | 12 +-
.../POSIX}/RegisterContextPOSIX_s390x.cpp | 2 +-
.../POSIX}/RegisterContextPOSIX_s390x.h | 12 +-
.../POSIX}/RegisterContextPOSIX_x86.cpp | 2 +-
.../POSIX}/RegisterContextPOSIX_x86.h | 14 +-
.../FreeBSD-Kernel-Core/CMakeLists.txt | 1 +
.../RegisterContextFreeBSDKernelCore_arm.h | 2 +-
.../RegisterContextFreeBSDKernelCore_arm64.h | 2 +-
.../RegisterContextFreeBSDKernelCore_i386.h | 2 +-
...RegisterContextFreeBSDKernelCore_ppc64le.h | 2 +-
...RegisterContextFreeBSDKernelCore_riscv64.h | 2 +-
.../RegisterContextFreeBSDKernelCore_x86_64.h | 2 +-
.../Plugins/Process/FreeBSD/CMakeLists.txt | 1 +
.../NativeRegisterContextFreeBSD_powerpc.cpp | 2 +-
.../Plugins/Process/Utility/CMakeLists.txt | 9 -
.../Utility/RegisterContextPOSIX_powerpc.h | 195 ------------------
.../Plugins/Process/elf-core/CMakeLists.txt | 1 +
.../elf-core/RegisterContextPOSIXCore_arm.h | 2 +-
.../elf-core/RegisterContextPOSIXCore_arm64.h | 2 +-
.../RegisterContextPOSIXCore_loongarch64.h | 2 +-
.../RegisterContextPOSIXCore_powerpc.h | 2 +-
.../RegisterContextPOSIXCore_ppc64le.h | 2 +-
.../RegisterContextPOSIXCore_riscv64.h | 2 +-
.../elf-core/RegisterContextPOSIXCore_s390x.h | 2 +-
.../elf-core/RegisterContextPOSIXCore_x86.h | 2 +-
.../Register/Arch/RegisterContext_powerpc.h | 121 +++++++++++
.../FreeBSD/RegisterInfoFreeBSD_powerpc.cpp | 3 +-
.../Linux/RegisterInfoLinux_s390x.cpp | 4 +-
lldb/unittests/Process/Utility/CMakeLists.txt | 3 +-
.../Utility/RegisterInfoFreeBSDTest.cpp | 2 +-
.../source/Plugins/Process/Common/BUILD.gn | 23 +++
.../source/Plugins/Process/Utility/BUILD.gn | 9 -
.../source/Plugins/Process/elf-core/BUILD.gn | 1 +
48 files changed, 315 insertions(+), 279 deletions(-)
create mode 100644 lldb/source/Plugins/Process/Common/CMakeLists.txt
rename lldb/source/Plugins/Process/{Utility => Common/RegisterContext/POSIX}/RegisterContextPOSIX_arm.cpp (100%)
rename lldb/source/Plugins/Process/{Utility => Common/RegisterContext/POSIX}/RegisterContextPOSIX_arm.h (80%)
rename lldb/source/Plugins/Process/{Utility => Common/RegisterContext/POSIX}/RegisterContextPOSIX_arm64.cpp (100%)
rename lldb/source/Plugins/Process/{Utility => Common/RegisterContext/POSIX}/RegisterContextPOSIX_arm64.h (86%)
rename lldb/source/Plugins/Process/{Utility => Common/RegisterContext/POSIX}/RegisterContextPOSIX_loongarch64.cpp (100%)
rename lldb/source/Plugins/Process/{Utility => Common/RegisterContext/POSIX}/RegisterContextPOSIX_loongarch64.h (80%)
rename lldb/source/Plugins/Process/{Utility => Common/RegisterContext/POSIX}/RegisterContextPOSIX_powerpc.cpp (100%)
create mode 100644 lldb/source/Plugins/Process/Common/RegisterContext/POSIX/RegisterContextPOSIX_powerpc.h
rename lldb/source/Plugins/Process/{Utility => Common/RegisterContext/POSIX}/RegisterContextPOSIX_ppc64le.cpp (100%)
rename lldb/source/Plugins/Process/{Utility => Common/RegisterContext/POSIX}/RegisterContextPOSIX_ppc64le.h (86%)
rename lldb/source/Plugins/Process/{Utility => Common/RegisterContext/POSIX}/RegisterContextPOSIX_riscv32.cpp (100%)
rename lldb/source/Plugins/Process/{Utility => Common/RegisterContext/POSIX}/RegisterContextPOSIX_riscv32.h (78%)
rename lldb/source/Plugins/Process/{Utility => Common/RegisterContext/POSIX}/RegisterContextPOSIX_riscv64.cpp (100%)
rename lldb/source/Plugins/Process/{Utility => Common/RegisterContext/POSIX}/RegisterContextPOSIX_riscv64.h (78%)
rename lldb/source/Plugins/Process/{Utility => Common/RegisterContext/POSIX}/RegisterContextPOSIX_s390x.cpp (99%)
rename lldb/source/Plugins/Process/{Utility => Common/RegisterContext/POSIX}/RegisterContextPOSIX_s390x.h (80%)
rename lldb/source/Plugins/Process/{Utility => Common/RegisterContext/POSIX}/RegisterContextPOSIX_x86.cpp (99%)
rename lldb/source/Plugins/Process/{Utility => Common/RegisterContext/POSIX}/RegisterContextPOSIX_x86.h (84%)
delete mode 100644 lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_powerpc.h
create mode 100644 llvm/utils/gn/secondary/lldb/source/Plugins/Process/Common/BUILD.gn
diff --git a/lldb/source/Plugins/Process/CMakeLists.txt b/lldb/source/Plugins/Process/CMakeLists.txt
index 1599da896aca08..98a82be2fc332b 100644
--- a/lldb/source/Plugins/Process/CMakeLists.txt
+++ b/lldb/source/Plugins/Process/CMakeLists.txt
@@ -23,6 +23,7 @@ endif()
add_subdirectory(FreeBSD-Kernel-Core)
add_subdirectory(MacOSX-Kernel)
+add_subdirectory(Common)
add_subdirectory(NativeCommon)
add_subdirectory(scripted)
add_subdirectory(gdb-remote)
diff --git a/lldb/source/Plugins/Process/Common/CMakeLists.txt b/lldb/source/Plugins/Process/Common/CMakeLists.txt
new file mode 100644
index 00000000000000..f9f7289f9c1276
--- /dev/null
+++ b/lldb/source/Plugins/Process/Common/CMakeLists.txt
@@ -0,0 +1,22 @@
+add_lldb_library(lldbProcessContextSupport NO_PLUGIN_DEPENDENCIES
+ RegisterContext/POSIX/RegisterContextPOSIX_arm.cpp
+ RegisterContext/POSIX/RegisterContextPOSIX_arm64.cpp
+ RegisterContext/POSIX/RegisterContextPOSIX_loongarch64.cpp
+ RegisterContext/POSIX/RegisterContextPOSIX_powerpc.cpp
+ RegisterContext/POSIX/RegisterContextPOSIX_ppc64le.cpp
+ RegisterContext/POSIX/RegisterContextPOSIX_riscv32.cpp
+ RegisterContext/POSIX/RegisterContextPOSIX_riscv64.cpp
+ RegisterContext/POSIX/RegisterContextPOSIX_s390x.cpp
+ RegisterContext/POSIX/RegisterContextPOSIX_x86.cpp
+
+ LINK_COMPONENTS
+ Support
+ LINK_LIBS
+ lldbRegister
+ lldbTarget
+ lldbUtility
+ ALLOWED_INTERNAL_DEPENDENCIES
+ lldbRegister
+ lldbTarget
+ lldbUtility
+ )
diff --git a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_arm.cpp b/lldb/source/Plugins/Process/Common/RegisterContext/POSIX/RegisterContextPOSIX_arm.cpp
similarity index 100%
rename from lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_arm.cpp
rename to lldb/source/Plugins/Process/Common/RegisterContext/POSIX/RegisterContextPOSIX_arm.cpp
diff --git a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_arm.h b/lldb/source/Plugins/Process/Common/RegisterContext/POSIX/RegisterContextPOSIX_arm.h
similarity index 80%
rename from lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_arm.h
rename to lldb/source/Plugins/Process/Common/RegisterContext/POSIX/RegisterContextPOSIX_arm.h
index 4b21cfbb93d904..35db27ea67af48 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_arm.h
+++ b/lldb/source/Plugins/Process/Common/RegisterContext/POSIX/RegisterContextPOSIX_arm.h
@@ -6,11 +6,11 @@
//
//===----------------------------------------------------------------------===//
-#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTPOSIX_ARM_H
-#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTPOSIX_ARM_H
+#ifndef LLDB_SOURCE_PLUGINS_PROCESS_COMMON_REGISTERCONTEXT_POSIX_REGISTERCONTEXTPOSIX_ARM_H
+#define LLDB_SOURCE_PLUGINS_PROCESS_COMMON_REGISTERCONTEXT_POSIX_REGISTERCONTEXTPOSIX_ARM_H
-#include "RegisterInfoInterface.h"
-#include "RegisterInfoCommon_arm.h"
+#include "Register/RegisterInfoInterface.h"
+#include "Register/Common/RegisterInfoCommon_arm.h"
#include "lldb/Target/RegisterContext.h"
#include "lldb/Utility/Log.h"
@@ -59,4 +59,4 @@ class RegisterContextPOSIX_arm : public lldb_private::RegisterContext {
virtual bool WriteFPR() = 0;
};
-#endif // LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTPOSIX_ARM_H
+#endif // LLDB_SOURCE_PLUGINS_PROCESS_COMMON_REGISTERCONTEXT_POSIX_REGISTERCONTEXTPOSIX_ARM_H
diff --git a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_arm64.cpp b/lldb/source/Plugins/Process/Common/RegisterContext/POSIX/RegisterContextPOSIX_arm64.cpp
similarity index 100%
rename from lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_arm64.cpp
rename to lldb/source/Plugins/Process/Common/RegisterContext/POSIX/RegisterContextPOSIX_arm64.cpp
diff --git a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_arm64.h b/lldb/source/Plugins/Process/Common/RegisterContext/POSIX/RegisterContextPOSIX_arm64.h
similarity index 86%
rename from lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_arm64.h
rename to lldb/source/Plugins/Process/Common/RegisterContext/POSIX/RegisterContextPOSIX_arm64.h
index 6137030a577116..6b90d63144268e 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_arm64.h
+++ b/lldb/source/Plugins/Process/Common/RegisterContext/POSIX/RegisterContextPOSIX_arm64.h
@@ -6,11 +6,11 @@
//
//===----------------------------------------------------------------------===//
-#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTPOSIX_ARM64_H
-#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTPOSIX_ARM64_H
+#ifndef LLDB_SOURCE_PLUGINS_PROCESS_COMMON_REGISTERCONTEXT_POSIX_REGISTERCONTEXTPOSIX_ARM64_H
+#define LLDB_SOURCE_PLUGINS_PROCESS_COMMON_REGISTERCONTEXT_POSIX_REGISTERCONTEXTPOSIX_ARM64_H
-#include "RegisterInfoInterface.h"
-#include "RegisterInfoCommon_arm64.h"
+#include "Register/RegisterInfoInterface.h"
+#include "Register/Common/RegisterInfoCommon_arm64.h"
#include "lldb/Target/RegisterContext.h"
#include "lldb/Utility/Log.h"
@@ -86,4 +86,4 @@ class RegisterContextPOSIX_arm64 : public lldb_private::RegisterContext {
virtual bool WriteFPR() = 0;
};
-#endif // LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTPOSIX_ARM64_H
+#endif // LLDB_SOURCE_PLUGINS_PROCESS_COMMON_REGISTERCONTEXT_POSIX_REGISTERCONTEXTPOSIX_ARM64_H
diff --git a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_loongarch64.cpp b/lldb/source/Plugins/Process/Common/RegisterContext/POSIX/RegisterContextPOSIX_loongarch64.cpp
similarity index 100%
rename from lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_loongarch64.cpp
rename to lldb/source/Plugins/Process/Common/RegisterContext/POSIX/RegisterContextPOSIX_loongarch64.cpp
diff --git a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_loongarch64.h b/lldb/source/Plugins/Process/Common/RegisterContext/POSIX/RegisterContextPOSIX_loongarch64.h
similarity index 80%
rename from lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_loongarch64.h
rename to lldb/source/Plugins/Process/Common/RegisterContext/POSIX/RegisterContextPOSIX_loongarch64.h
index 7f63a6e95d9ab4..ff1fb1fd0d20ed 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_loongarch64.h
+++ b/lldb/source/Plugins/Process/Common/RegisterContext/POSIX/RegisterContextPOSIX_loongarch64.h
@@ -6,12 +6,12 @@
//
//===----------------------------------------------------------------------===//
-#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTPOSIX_LOONGARCH64_H
-#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTPOSIX_LOONGARCH64_H
+#ifndef LLDB_SOURCE_PLUGINS_PROCESS_COMMON_REGISTERCONTEXT_POSIX_REGISTERCONTEXTPOSIX_LOONGARCH64_H
+#define LLDB_SOURCE_PLUGINS_PROCESS_COMMON_REGISTERCONTEXT_POSIX_REGISTERCONTEXTPOSIX_LOONGARCH64_H
-#include "RegisterInfoInterface.h"
-#include "RegisterInfoCommon_loongarch64.h"
-#include "lldb-loongarch-register-enums.h"
+#include "Register/RegisterInfoInterface.h"
+#include "Register/Common/RegisterInfoCommon_loongarch64.h"
+#include "Register/Arch/lldb-loongarch-register-enums.h"
#include "lldb/Target/RegisterContext.h"
#include "lldb/Utility/Log.h"
@@ -68,4 +68,4 @@ class RegisterContextPOSIX_loongarch64 : public lldb_private::RegisterContext {
virtual bool WriteLASX() { return false; }
};
-#endif // LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTPOSIX_LOONGARCH64_H
+#endif // LLDB_SOURCE_PLUGINS_PROCESS_COMMON_REGISTERCONTEXT_POSIX_REGISTERCONTEXTPOSIX_LOONGARCH64_H
diff --git a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_powerpc.cpp b/lldb/source/Plugins/Process/Common/RegisterContext/POSIX/RegisterContextPOSIX_powerpc.cpp
similarity index 100%
rename from lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_powerpc.cpp
rename to lldb/source/Plugins/Process/Common/RegisterContext/POSIX/RegisterContextPOSIX_powerpc.cpp
diff --git a/lldb/source/Plugins/Process/Common/RegisterContext/POSIX/RegisterContextPOSIX_powerpc.h b/lldb/source/Plugins/Process/Common/RegisterContext/POSIX/RegisterContextPOSIX_powerpc.h
new file mode 100644
index 00000000000000..301360c1e902eb
--- /dev/null
+++ b/lldb/source/Plugins/Process/Common/RegisterContext/POSIX/RegisterContextPOSIX_powerpc.h
@@ -0,0 +1,74 @@
+//===-- RegisterContextPOSIX_powerpc.h --------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLDB_SOURCE_PLUGINS_PROCESS_COMMON_REGISTERCONTEXT_POSIX_REGISTERCONTEXTPOSIX_POWERPC_H
+#define LLDB_SOURCE_PLUGINS_PROCESS_COMMON_REGISTERCONTEXT_POSIX_REGISTERCONTEXTPOSIX_POWERPC_H
+
+#include "Register/RegisterInfoInterface.h"
+#include "Register/Arch/RegisterContext_powerpc.h"
+#include "lldb/Target/RegisterContext.h"
+#include "lldb/Utility/Log.h"
+
+class RegisterContextPOSIX_powerpc : public lldb_private::RegisterContext {
+public:
+ RegisterContextPOSIX_powerpc(
+ lldb_private::Thread &thread, uint32_t concrete_frame_idx,
+ lldb_private::RegisterInfoInterface *register_info);
+
+ ~RegisterContextPOSIX_powerpc() override;
+
+ void Invalidate();
+
+ void InvalidateAllRegisters() override;
+
+ size_t GetRegisterCount() override;
+
+ virtual size_t GetGPRSize();
+
+ virtual unsigned GetRegisterSize(unsigned reg);
+
+ virtual unsigned GetRegisterOffset(unsigned reg);
+
+ const lldb_private::RegisterInfo *GetRegisterInfoAtIndex(size_t reg) override;
+
+ size_t GetRegisterSetCount() override;
+
+ const lldb_private::RegisterSet *GetRegisterSet(size_t set) override;
+
+ const char *GetRegisterName(unsigned reg);
+
+protected:
+ uint64_t
+ m_gpr_powerpc[k_num_gpr_registers_powerpc]; // general purpose registers.
+ uint64_t
+ m_fpr_powerpc[k_num_fpr_registers_powerpc]; // floating point registers.
+ uint32_t m_vmx_powerpc[k_num_vmx_registers_powerpc][4];
+ std::unique_ptr<lldb_private::RegisterInfoInterface>
+ m_register_info_up; // Register Info Interface (FreeBSD or Linux)
+
+ // Determines if an extended register set is supported on the processor
+ // running the inferior process.
+ virtual bool IsRegisterSetAvailable(size_t set_index);
+
+ virtual const lldb_private::RegisterInfo *GetRegisterInfo();
+
+ bool IsGPR(unsigned reg);
+
+ bool IsFPR(unsigned reg);
+
+ bool IsVMX(unsigned reg);
+
+ virtual bool ReadGPR() = 0;
+ virtual bool ReadFPR() = 0;
+ virtual bool ReadVMX() = 0;
+ virtual bool WriteGPR() = 0;
+ virtual bool WriteFPR() = 0;
+ virtual bool WriteVMX() = 0;
+};
+
+#endif // LLDB_SOURCE_PLUGINS_PROCESS_COMMON_REGISTERCONTEXT_POSIX_REGISTERCONTEXTPOSIX_POWERPC_H
diff --git a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_ppc64le.cpp b/lldb/source/Plugins/Process/Common/RegisterContext/POSIX/RegisterContextPOSIX_ppc64le.cpp
similarity index 100%
rename from lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_ppc64le.cpp
rename to lldb/source/Plugins/Process/Common/RegisterContext/POSIX/RegisterContextPOSIX_ppc64le.cpp
diff --git a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_ppc64le.h b/lldb/source/Plugins/Process/Common/RegisterContext/POSIX/RegisterContextPOSIX_ppc64le.h
similarity index 86%
rename from lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_ppc64le.h
rename to lldb/source/Plugins/Process/Common/RegisterContext/POSIX/RegisterContextPOSIX_ppc64le.h
index 65209179596295..3689527b12d041 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_ppc64le.h
+++ b/lldb/source/Plugins/Process/Common/RegisterContext/POSIX/RegisterContextPOSIX_ppc64le.h
@@ -6,11 +6,11 @@
//
//===----------------------------------------------------------------------===//
-#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTPOSIX_PPC64LE_H
-#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTPOSIX_PPC64LE_H
+#ifndef LLDB_SOURCE_PLUGINS_PROCESS_COMMON_REGISTERCONTEXT_POSIX_REGISTERCONTEXTPOSIX_PPC64LE_H
+#define LLDB_SOURCE_PLUGINS_PROCESS_COMMON_REGISTERCONTEXT_POSIX_REGISTERCONTEXTPOSIX_PPC64LE_H
#include "Register/Arch/lldb-ppc64le-register-enums.h"
-#include "RegisterInfoInterface.h"
+#include "Register/RegisterInfoInterface.h"
#include "Utility/PPC64LE_DWARF_Registers.h"
#include "lldb/Target/RegisterContext.h"
#include "lldb/Utility/Log.h"
@@ -70,4 +70,4 @@ class RegisterContextPOSIX_ppc64le : public lldb_private::RegisterContext {
};
-#endif // LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTPOSIX_PPC64LE_H
+#endif // LLDB_SOURCE_PLUGINS_PROCESS_COMMON_REGISTERCONTEXT_POSIX_REGISTERCONTEXTPOSIX_PPC64LE_H
diff --git a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_riscv32.cpp b/lldb/source/Plugins/Process/Common/RegisterContext/POSIX/RegisterContextPOSIX_riscv32.cpp
similarity index 100%
rename from lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_riscv32.cpp
rename to lldb/source/Plugins/Process/Common/RegisterContext/POSIX/RegisterContextPOSIX_riscv32.cpp
diff --git a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_riscv32.h b/lldb/source/Plugins/Process/Common/RegisterContext/POSIX/RegisterContextPOSIX_riscv32.h
similarity index 78%
rename from lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_riscv32.h
rename to lldb/source/Plugins/Process/Common/RegisterContext/POSIX/RegisterContextPOSIX_riscv32.h
index 3fa948f0f82212..fd5310ec69c263 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_riscv32.h
+++ b/lldb/source/Plugins/Process/Common/RegisterContext/POSIX/RegisterContextPOSIX_riscv32.h
@@ -6,12 +6,12 @@
//
//===----------------------------------------------------------------------===//
-#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTPOSIX_RISCV32_H
-#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTPOSIX_RISCV32_H
+#ifndef LLDB_SOURCE_PLUGINS_PROCESS_COMMON_REGISTERCONTEXT_POSIX_REGISTERCONTEXTPOSIX_RISCV32_H
+#define LLDB_SOURCE_PLUGINS_PROCESS_COMMON_REGISTERCONTEXT_POSIX_REGISTERCONTEXTPOSIX_RISCV32_H
-#include "RegisterInfoInterface.h"
-#include "RegisterInfoCommon_riscv32.h"
-#include "lldb-riscv-register-enums.h"
+#include "Register/RegisterInfoInterface.h"
+#include "Register/Common/RegisterInfoCommon_riscv32.h"
+#include "Register/Arch/lldb-riscv-register-enums.h"
#include "lldb/Target/RegisterContext.h"
#include "lldb/Utility/Log.h"
@@ -60,4 +60,4 @@ class RegisterContextPOSIX_riscv32 : public lldb_private::RegisterContext {
virtual bool WriteFPR() = 0;
};
-#endif // LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTPOSIX_RISCV32_H
+#endif // LLDB_SOURCE_PLUGINS_PROCESS_COMMON_REGISTERCONTEXT_POSIX_REGISTERCONTEXTPOSIX_RISCV32_H
diff --git a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_riscv64.cpp b/lldb/source/Plugins/Process/Common/RegisterContext/POSIX/RegisterContextPOSIX_riscv64.cpp
similarity index 100%
rename from lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_riscv64.cpp
rename to lldb/source/Plugins/Process/Common/RegisterContext/POSIX/RegisterContextPOSIX_riscv64.cpp
diff --git a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_riscv64.h b/lldb/source/Plugins/Process/Common/RegisterContext/POSIX/RegisterContextPOSIX_riscv64.h
similarity index 78%
rename from lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_riscv64.h
rename to lldb/source/Plugins/Process/Common/RegisterContext/POSIX/RegisterContextPOSIX_riscv64.h
index 417bb4f808f035..f954dd9199ff66 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_riscv64.h
+++ b/lldb/source/Plugins/Process/Common/RegisterContext/POSIX/RegisterContextPOSIX_riscv64.h
@@ -6,12 +6,12 @@
//
//===----------------------------------------------------------------------===//
-#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTPOSIX_RISCV64_H
-#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTPOSIX_RISCV64_H
+#ifndef LLDB_SOURCE_PLUGINS_PROCESS_COMMON_REGISTERCONTEXT_POSIX_REGISTERCONTEXTPOSIX_RISCV64_H
+#define LLDB_SOURCE_PLUGINS_PROCESS_COMMON_REGISTERCONTEXT_POSIX_REGISTERCONTEXTPOSIX_RISCV64_H
-#include "RegisterInfoInterface.h"
-#include "RegisterInfoCommon_riscv64.h"
-#include "lldb-riscv-register-enums.h"
+#include "Register/RegisterInfoInterface.h"
+#include "Register/Common/RegisterInfoCommon_riscv64.h"
+#include "Register/Arch/lldb-riscv-register-enums.h"
#include "lldb/Target/RegisterContext.h"
#include "lldb/Utility/Log.h"
@@ -60,4 +60,4 @@ class RegisterContextPOSIX_riscv64 : public lldb_private::RegisterContext {
virtual bool WriteFPR() = 0;
};
-#endif // LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTPOSIX_RISCV64_H
+#endif // LLDB_SOURCE_PLUGINS_PROCESS_COMMON_REGISTERCONTEXT_POSIX_REGISTERCONTEXTPOSIX_RISCV64_H
diff --git a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_s390x.cpp b/lldb/source/Plugins/Process/Common/RegisterContext/POSIX/RegisterContextPOSIX_s390x.cpp
similarity index 99%
rename from lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_s390x.cpp
rename to lldb/source/Plugins/Process/Common/RegisterContext/POSIX/RegisterContextPOSIX_s390x.cpp
index b85da39b4c45c7..c3cbea2b5be647 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_s390x.cpp
+++ b/lldb/source/Plugins/Process/Common/RegisterContext/POSIX/RegisterContextPOSIX_s390x.cpp
@@ -21,7 +21,7 @@
#include "llvm/Support/Compiler.h"
#include "RegisterContextPOSIX_s390x.h"
-#include "RegisterContext_s390x.h"
+#include "Register/Arch/RegisterContext_s390x.h"
using namespace lldb_private;
using namespace lldb;
diff --git a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_s390x.h b/lldb/source/Plugins/Process/Common/RegisterContext/POSIX/RegisterContextPOSIX_s390x.h
similarity index 80%
rename from lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_s390x.h
rename to lldb/source/Plugins/Process/Common/RegisterContext/POSIX/RegisterContextPOSIX_s390x.h
index 7027af04f0bb2d..54a18cca066067 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_s390x.h
+++ b/lldb/source/Plugins/Process/Common/RegisterContext/POSIX/RegisterContextPOSIX_s390x.h
@@ -6,12 +6,12 @@
//
//===----------------------------------------------------------------------===//
-#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTPOSIX_S390X_H
-#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTPOSIX_S390X_H
+#ifndef LLDB_SOURCE_PLUGINS_PROCESS_COMMON_REGISTERCONTEXT_POSIX_REGISTERCONTEXTPOSIX_S390X_H
+#define LLDB_SOURCE_PLUGINS_PROCESS_COMMON_REGISTERCONTEXT_POSIX_REGISTERCONTEXTPOSIX_S390X_H
-#include "RegisterContext_s390x.h"
-#include "RegisterInfoInterface.h"
-#include "lldb-s390x-register-enums.h"
+#include "Register/Arch/RegisterContext_s390x.h"
+#include "Register/RegisterInfoInterface.h"
+#include "Register/Arch/lldb-s390x-register-enums.h"
#include "lldb/Target/RegisterContext.h"
#include "lldb/Utility/Log.h"
@@ -69,4 +69,4 @@ class RegisterContextPOSIX_s390x : public lldb_private::RegisterContext {
virtual bool WriteFPR() = 0;
};
-#endif // LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTPOSIX_S390X_H
+#endif // LLDB_SOURCE_PLUGINS_PROCESS_COMMON_REGISTERCONTEXT_POSIX_REGISTERCONTEXTPOSIX_S390X_H
diff --git a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_x86.cpp b/lldb/source/Plugins/Process/Common/RegisterContext/POSIX/RegisterContextPOSIX_x86.cpp
similarity index 99%
rename from lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_x86.cpp
rename to lldb/source/Plugins/Process/Common/RegisterContext/POSIX/RegisterContextPOSIX_x86.cpp
index 96640bceaea622..96abe5cc0eb72a 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_x86.cpp
+++ b/lldb/source/Plugins/Process/Common/RegisterContext/POSIX/RegisterContextPOSIX_x86.cpp
@@ -21,7 +21,7 @@
#include "llvm/Support/Compiler.h"
#include "RegisterContextPOSIX_x86.h"
-#include "RegisterContext_x86.h"
+#include "Register/Arch/RegisterContext_x86.h"
using namespace lldb_private;
using namespace lldb;
diff --git a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_x86.h b/lldb/source/Plugins/Process/Common/RegisterContext/POSIX/RegisterContextPOSIX_x86.h
similarity index 84%
rename from lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_x86.h
rename to lldb/source/Plugins/Process/Common/RegisterContext/POSIX/RegisterContextPOSIX_x86.h
index 2bee8f638c2daf..5fdde75f866dd2 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_x86.h
+++ b/lldb/source/Plugins/Process/Common/RegisterContext/POSIX/RegisterContextPOSIX_x86.h
@@ -6,13 +6,13 @@
//
//===----------------------------------------------------------------------===//
-#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTPOSIX_X86_H
-#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTPOSIX_X86_H
+#ifndef LLDB_SOURCE_PLUGINS_PROCESS_COMMON_REGISTERCONTEXT_POSIX_REGISTERCONTEXTPOSIX_X86_H
+#define LLDB_SOURCE_PLUGINS_PROCESS_COMMON_REGISTERCONTEXT_POSIX_REGISTERCONTEXTPOSIX_X86_H
-#include "RegisterContext_x86.h"
-#include "RegisterInfoInterface.h"
-#include "RegisterInfos_x86_64_with_base_shared.h"
-#include "lldb-x86-register-enums.h"
+#include "Register/Arch/RegisterContext_x86.h"
+#include "Register/RegisterInfoInterface.h"
+#include "Register/Arch/RegisterInfos_x86_64_with_base_shared.h"
+#include "Register/Arch/lldb-x86-register-enums.h"
#include "lldb/Target/RegisterContext.h"
#include "lldb/Utility/Log.h"
@@ -88,4 +88,4 @@ class RegisterContextPOSIX_x86 : public lldb_private::RegisterContext {
virtual lldb_private::RegInfo &GetRegInfo();
};
-#endif // LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTPOSIX_X86_H
+#endif // LLDB_SOURCE_PLUGINS_PROCESS_COMMON_REGISTERCONTEXT_POSIX_REGISTERCONTEXTPOSIX_X86_H
diff --git a/lldb/source/Plugins/Process/FreeBSD-Kernel-Core/CMakeLists.txt b/lldb/source/Plugins/Process/FreeBSD-Kernel-Core/CMakeLists.txt
index b9487abe105e0e..b7f27d1d97a919 100644
--- a/lldb/source/Plugins/Process/FreeBSD-Kernel-Core/CMakeLists.txt
+++ b/lldb/source/Plugins/Process/FreeBSD-Kernel-Core/CMakeLists.txt
@@ -24,6 +24,7 @@ if (CMAKE_SYSTEM_NAME MATCHES "FreeBSD")
LINK_COMPONENTS
Support
LINK_LIBS
+ lldbProcessContextSupport
lldbCore
lldbHost
lldbTarget
diff --git a/lldb/source/Plugins/Process/FreeBSD-Kernel-Core/RegisterContextFreeBSDKernelCore_arm.h b/lldb/source/Plugins/Process/FreeBSD-Kernel-Core/RegisterContextFreeBSDKernelCore_arm.h
index 8af593e9cbe5de..93c18082833e9b 100644
--- a/lldb/source/Plugins/Process/FreeBSD-Kernel-Core/RegisterContextFreeBSDKernelCore_arm.h
+++ b/lldb/source/Plugins/Process/FreeBSD-Kernel-Core/RegisterContextFreeBSDKernelCore_arm.h
@@ -9,7 +9,7 @@
#ifndef LLDB_SOURCE_PLUGINS_PROCESS_FREEBSDKERNEL_REGISTERCONTEXTFREEBSDKERNELCORE_ARM_H
#define LLDB_SOURCE_PLUGINS_PROCESS_FREEBSDKERNEL_REGISTERCONTEXTFREEBSDKERNELCORE_ARM_H
-#include "Plugins/Process/Utility/RegisterContextPOSIX_arm.h"
+#include "Plugins/Process/Common/RegisterContext/POSIX/RegisterContextPOSIX_arm.h"
#include "Plugins/Process/elf-core/RegisterUtilities.h"
class RegisterContextFreeBSDKernelCore_arm : public RegisterContextPOSIX_arm {
diff --git a/lldb/source/Plugins/Process/FreeBSD-Kernel-Core/RegisterContextFreeBSDKernelCore_arm64.h b/lldb/source/Plugins/Process/FreeBSD-Kernel-Core/RegisterContextFreeBSDKernelCore_arm64.h
index 3ad5ae7b88bae6..a008980161f6fa 100644
--- a/lldb/source/Plugins/Process/FreeBSD-Kernel-Core/RegisterContextFreeBSDKernelCore_arm64.h
+++ b/lldb/source/Plugins/Process/FreeBSD-Kernel-Core/RegisterContextFreeBSDKernelCore_arm64.h
@@ -9,7 +9,7 @@
#ifndef LLDB_SOURCE_PLUGINS_PROCESS_FREEBSDKERNEL_REGISTERCONTEXTFREEBSDKERNELCORE_ARM64_H
#define LLDB_SOURCE_PLUGINS_PROCESS_FREEBSDKERNEL_REGISTERCONTEXTFREEBSDKERNELCORE_ARM64_H
-#include "Plugins/Process/Utility/RegisterContextPOSIX_arm64.h"
+#include "Plugins/Process/Common/RegisterContext/POSIX/RegisterContextPOSIX_arm64.h"
#include "Plugins/Process/elf-core/RegisterUtilities.h"
#include <optional>
diff --git a/lldb/source/Plugins/Process/FreeBSD-Kernel-Core/RegisterContextFreeBSDKernelCore_i386.h b/lldb/source/Plugins/Process/FreeBSD-Kernel-Core/RegisterContextFreeBSDKernelCore_i386.h
index 26576734040f2a..74428bf6024566 100644
--- a/lldb/source/Plugins/Process/FreeBSD-Kernel-Core/RegisterContextFreeBSDKernelCore_i386.h
+++ b/lldb/source/Plugins/Process/FreeBSD-Kernel-Core/RegisterContextFreeBSDKernelCore_i386.h
@@ -9,7 +9,7 @@
#ifndef LLDB_SOURCE_PLUGINS_PROCESS_FREEBSDKERNEL_REGISTERCONTEXTFREEBSDKERNELCORE_I386_H
#define LLDB_SOURCE_PLUGINS_PROCESS_FREEBSDKERNEL_REGISTERCONTEXTFREEBSDKERNELCORE_I386_H
-#include "Plugins/Process/Utility/RegisterContextPOSIX_x86.h"
+#include "Plugins/Process/Common/RegisterContext/POSIX/RegisterContextPOSIX_x86.h"
#include "Plugins/Process/elf-core/RegisterUtilities.h"
class RegisterContextFreeBSDKernelCore_i386 : public RegisterContextPOSIX_x86 {
diff --git a/lldb/source/Plugins/Process/FreeBSD-Kernel-Core/RegisterContextFreeBSDKernelCore_ppc64le.h b/lldb/source/Plugins/Process/FreeBSD-Kernel-Core/RegisterContextFreeBSDKernelCore_ppc64le.h
index 5895744e6fa3dc..86169965b37a72 100644
--- a/lldb/source/Plugins/Process/FreeBSD-Kernel-Core/RegisterContextFreeBSDKernelCore_ppc64le.h
+++ b/lldb/source/Plugins/Process/FreeBSD-Kernel-Core/RegisterContextFreeBSDKernelCore_ppc64le.h
@@ -9,7 +9,7 @@
#ifndef LLDB_SOURCE_PLUGINS_PROCESS_FREEBSDKERNEL_REGISTERCONTEXTFREEBSDKERNELCORE_PPC64LE_H
#define LLDB_SOURCE_PLUGINS_PROCESS_FREEBSDKERNEL_REGISTERCONTEXTFREEBSDKERNELCORE_PPC64LE_H
-#include "Plugins/Process/Utility/RegisterContextPOSIX_ppc64le.h"
+#include "Plugins/Process/Common/RegisterContext/POSIX/RegisterContextPOSIX_ppc64le.h"
#include "Plugins/Process/elf-core/RegisterUtilities.h"
class RegisterContextFreeBSDKernelCore_ppc64le
diff --git a/lldb/source/Plugins/Process/FreeBSD-Kernel-Core/RegisterContextFreeBSDKernelCore_riscv64.h b/lldb/source/Plugins/Process/FreeBSD-Kernel-Core/RegisterContextFreeBSDKernelCore_riscv64.h
index cb96c5c989f2c1..ff641ecc88cf82 100644
--- a/lldb/source/Plugins/Process/FreeBSD-Kernel-Core/RegisterContextFreeBSDKernelCore_riscv64.h
+++ b/lldb/source/Plugins/Process/FreeBSD-Kernel-Core/RegisterContextFreeBSDKernelCore_riscv64.h
@@ -9,7 +9,7 @@
#ifndef LLDB_SOURCE_PLUGINS_PROCESS_FREEBSDKERNEL_REGISTERCONTEXTFREEBSDKERNELCORE_RISCV64_H
#define LLDB_SOURCE_PLUGINS_PROCESS_FREEBSDKERNEL_REGISTERCONTEXTFREEBSDKERNELCORE_RISCV64_H
-#include "Plugins/Process/Utility/RegisterContextPOSIX_riscv64.h"
+#include "Plugins/Process/Common/RegisterContext/POSIX/RegisterContextPOSIX_riscv64.h"
#include "Plugins/Process/elf-core/RegisterUtilities.h"
class RegisterContextFreeBSDKernelCore_riscv64
diff --git a/lldb/source/Plugins/Process/FreeBSD-Kernel-Core/RegisterContextFreeBSDKernelCore_x86_64.h b/lldb/source/Plugins/Process/FreeBSD-Kernel-Core/RegisterContextFreeBSDKernelCore_x86_64.h
index 5e2877ca55b9db..56170f7d5ca73e 100644
--- a/lldb/source/Plugins/Process/FreeBSD-Kernel-Core/RegisterContextFreeBSDKernelCore_x86_64.h
+++ b/lldb/source/Plugins/Process/FreeBSD-Kernel-Core/RegisterContextFreeBSDKernelCore_x86_64.h
@@ -9,7 +9,7 @@
#ifndef LLDB_SOURCE_PLUGINS_PROCESS_FREEBSDKERNEL_REGISTERCONTEXTFREEBSDKERNELCORE_X86_64_H
#define LLDB_SOURCE_PLUGINS_PROCESS_FREEBSDKERNEL_REGISTERCONTEXTFREEBSDKERNELCORE_X86_64_H
-#include "Plugins/Process/Utility/RegisterContextPOSIX_x86.h"
+#include "Plugins/Process/Common/RegisterContext/POSIX/RegisterContextPOSIX_x86.h"
#include "Plugins/Process/elf-core/RegisterUtilities.h"
class RegisterContextFreeBSDKernelCore_x86_64
diff --git a/lldb/source/Plugins/Process/FreeBSD/CMakeLists.txt b/lldb/source/Plugins/Process/FreeBSD/CMakeLists.txt
index 0599191d408581..4c763044e364b4 100644
--- a/lldb/source/Plugins/Process/FreeBSD/CMakeLists.txt
+++ b/lldb/source/Plugins/Process/FreeBSD/CMakeLists.txt
@@ -11,6 +11,7 @@ add_lldb_library(lldbPluginProcessFreeBSD
Support
LINK_LIBS
lldbNativeProcessSupport
+ lldbProcessContextSupport
lldbHost
lldbSymbol
lldbTarget
diff --git a/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_powerpc.cpp b/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_powerpc.cpp
index 560c3e567702c8..eee4cabc1e7b2e 100644
--- a/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_powerpc.cpp
+++ b/lldb/source/Plugins/Process/FreeBSD/NativeRegisterContextFreeBSD_powerpc.cpp
@@ -17,7 +17,7 @@
#include "Plugins/Process/FreeBSD/NativeProcessFreeBSD.h"
// for register enum definitions
-#include "Plugins/Process/Utility/RegisterContextPOSIX_powerpc.h"
+#include "Plugins/Process/Common/RegisterContext/POSIX/RegisterContextPOSIX_powerpc.h"
// clang-format off
#include <sys/param.h>
diff --git a/lldb/source/Plugins/Process/Utility/CMakeLists.txt b/lldb/source/Plugins/Process/Utility/CMakeLists.txt
index e74e17971d0356..6dbd6a5279e9cc 100644
--- a/lldb/source/Plugins/Process/Utility/CMakeLists.txt
+++ b/lldb/source/Plugins/Process/Utility/CMakeLists.txt
@@ -23,15 +23,6 @@ add_lldb_library(lldbPluginProcessUtility
RegisterContextMach_arm.cpp
RegisterContextMach_x86_64.cpp
RegisterContextMemory.cpp
- RegisterContextPOSIX_arm.cpp
- RegisterContextPOSIX_arm64.cpp
- RegisterContextPOSIX_loongarch64.cpp
- RegisterContextPOSIX_riscv32.cpp
- RegisterContextPOSIX_powerpc.cpp
- RegisterContextPOSIX_ppc64le.cpp
- RegisterContextPOSIX_riscv64.cpp
- RegisterContextPOSIX_s390x.cpp
- RegisterContextPOSIX_x86.cpp
RegisterContextThreadMemory.cpp
StopInfoMachException.cpp
ThreadMemory.cpp
diff --git a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_powerpc.h b/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_powerpc.h
deleted file mode 100644
index 5dd8c890da6ede..00000000000000
--- a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_powerpc.h
+++ /dev/null
@@ -1,195 +0,0 @@
-//===-- RegisterContextPOSIX_powerpc.h --------------------------*- C++ -*-===//
-//
-// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
-// See https://llvm.org/LICENSE.txt for license information.
-// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTPOSIX_POWERPC_H
-#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTPOSIX_POWERPC_H
-
-#include "RegisterContext_powerpc.h"
-#include "RegisterInfoInterface.h"
-#include "lldb/Target/RegisterContext.h"
-#include "lldb/Utility/Log.h"
-
-// Internal codes for all powerpc registers.
-enum {
- k_first_gpr_powerpc,
- gpr_r0_powerpc = k_first_gpr_powerpc,
- gpr_r1_powerpc,
- gpr_r2_powerpc,
- gpr_r3_powerpc,
- gpr_r4_powerpc,
- gpr_r5_powerpc,
- gpr_r6_powerpc,
- gpr_r7_powerpc,
- gpr_r8_powerpc,
- gpr_r9_powerpc,
- gpr_r10_powerpc,
- gpr_r11_powerpc,
- gpr_r12_powerpc,
- gpr_r13_powerpc,
- gpr_r14_powerpc,
- gpr_r15_powerpc,
- gpr_r16_powerpc,
- gpr_r17_powerpc,
- gpr_r18_powerpc,
- gpr_r19_powerpc,
- gpr_r20_powerpc,
- gpr_r21_powerpc,
- gpr_r22_powerpc,
- gpr_r23_powerpc,
- gpr_r24_powerpc,
- gpr_r25_powerpc,
- gpr_r26_powerpc,
- gpr_r27_powerpc,
- gpr_r28_powerpc,
- gpr_r29_powerpc,
- gpr_r30_powerpc,
- gpr_r31_powerpc,
- gpr_lr_powerpc,
- gpr_cr_powerpc,
- gpr_xer_powerpc,
- gpr_ctr_powerpc,
- gpr_pc_powerpc,
- k_last_gpr_powerpc = gpr_pc_powerpc,
-
- k_first_fpr,
- fpr_f0_powerpc = k_first_fpr,
- fpr_f1_powerpc,
- fpr_f2_powerpc,
- fpr_f3_powerpc,
- fpr_f4_powerpc,
- fpr_f5_powerpc,
- fpr_f6_powerpc,
- fpr_f7_powerpc,
- fpr_f8_powerpc,
- fpr_f9_powerpc,
- fpr_f10_powerpc,
- fpr_f11_powerpc,
- fpr_f12_powerpc,
- fpr_f13_powerpc,
- fpr_f14_powerpc,
- fpr_f15_powerpc,
- fpr_f16_powerpc,
- fpr_f17_powerpc,
- fpr_f18_powerpc,
- fpr_f19_powerpc,
- fpr_f20_powerpc,
- fpr_f21_powerpc,
- fpr_f22_powerpc,
- fpr_f23_powerpc,
- fpr_f24_powerpc,
- fpr_f25_powerpc,
- fpr_f26_powerpc,
- fpr_f27_powerpc,
- fpr_f28_powerpc,
- fpr_f29_powerpc,
- fpr_f30_powerpc,
- fpr_f31_powerpc,
- fpr_fpscr_powerpc,
- k_last_fpr = fpr_fpscr_powerpc,
-
- k_first_vmx,
- vmx_v0_powerpc = k_first_vmx,
- vmx_v1_powerpc,
- vmx_v2_powerpc,
- vmx_v3_powerpc,
- vmx_v4_powerpc,
- vmx_v5_powerpc,
- vmx_v6_powerpc,
- vmx_v7_powerpc,
- vmx_v8_powerpc,
- vmx_v9_powerpc,
- vmx_v10_powerpc,
- vmx_v11_powerpc,
- vmx_v12_powerpc,
- vmx_v13_powerpc,
- vmx_v14_powerpc,
- vmx_v15_powerpc,
- vmx_v16_powerpc,
- vmx_v17_powerpc,
- vmx_v18_powerpc,
- vmx_v19_powerpc,
- vmx_v20_powerpc,
- vmx_v21_powerpc,
- vmx_v22_powerpc,
- vmx_v23_powerpc,
- vmx_v24_powerpc,
- vmx_v25_powerpc,
- vmx_v26_powerpc,
- vmx_v27_powerpc,
- vmx_v28_powerpc,
- vmx_v29_powerpc,
- vmx_v30_powerpc,
- vmx_v31_powerpc,
- vmx_vrsave_powerpc,
- vmx_vscr_powerpc,
- k_last_vmx = vmx_vscr_powerpc,
-
- k_num_registers_powerpc,
- k_num_gpr_registers_powerpc = k_last_gpr_powerpc - k_first_gpr_powerpc + 1,
- k_num_fpr_registers_powerpc = k_last_fpr - k_first_fpr + 1,
- k_num_vmx_registers_powerpc = k_last_vmx - k_first_vmx + 1,
-};
-
-class RegisterContextPOSIX_powerpc : public lldb_private::RegisterContext {
-public:
- RegisterContextPOSIX_powerpc(
- lldb_private::Thread &thread, uint32_t concrete_frame_idx,
- lldb_private::RegisterInfoInterface *register_info);
-
- ~RegisterContextPOSIX_powerpc() override;
-
- void Invalidate();
-
- void InvalidateAllRegisters() override;
-
- size_t GetRegisterCount() override;
-
- virtual size_t GetGPRSize();
-
- virtual unsigned GetRegisterSize(unsigned reg);
-
- virtual unsigned GetRegisterOffset(unsigned reg);
-
- const lldb_private::RegisterInfo *GetRegisterInfoAtIndex(size_t reg) override;
-
- size_t GetRegisterSetCount() override;
-
- const lldb_private::RegisterSet *GetRegisterSet(size_t set) override;
-
- const char *GetRegisterName(unsigned reg);
-
-protected:
- uint64_t
- m_gpr_powerpc[k_num_gpr_registers_powerpc]; // general purpose registers.
- uint64_t
- m_fpr_powerpc[k_num_fpr_registers_powerpc]; // floating point registers.
- uint32_t m_vmx_powerpc[k_num_vmx_registers_powerpc][4];
- std::unique_ptr<lldb_private::RegisterInfoInterface>
- m_register_info_up; // Register Info Interface (FreeBSD or Linux)
-
- // Determines if an extended register set is supported on the processor
- // running the inferior process.
- virtual bool IsRegisterSetAvailable(size_t set_index);
-
- virtual const lldb_private::RegisterInfo *GetRegisterInfo();
-
- bool IsGPR(unsigned reg);
-
- bool IsFPR(unsigned reg);
-
- bool IsVMX(unsigned reg);
-
- virtual bool ReadGPR() = 0;
- virtual bool ReadFPR() = 0;
- virtual bool ReadVMX() = 0;
- virtual bool WriteGPR() = 0;
- virtual bool WriteFPR() = 0;
- virtual bool WriteVMX() = 0;
-};
-
-#endif // LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTPOSIX_POWERPC_H
diff --git a/lldb/source/Plugins/Process/elf-core/CMakeLists.txt b/lldb/source/Plugins/Process/elf-core/CMakeLists.txt
index d1addf2f36be39..7b7383b8074440 100644
--- a/lldb/source/Plugins/Process/elf-core/CMakeLists.txt
+++ b/lldb/source/Plugins/Process/elf-core/CMakeLists.txt
@@ -17,6 +17,7 @@ add_lldb_library(lldbPluginProcessElfCore PLUGIN
BinaryFormat
Support
LINK_LIBS
+ lldbProcessContextSupport
lldbCore
lldbTarget
lldbPluginDynamicLoaderPosixDYLD
diff --git a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm.h b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm.h
index 3b41cbc24d5547..7761e27eefcf03 100644
--- a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm.h
+++ b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm.h
@@ -9,7 +9,7 @@
#ifndef LLDB_SOURCE_PLUGINS_PROCESS_ELF_CORE_REGISTERCONTEXTPOSIXCORE_ARM_H
#define LLDB_SOURCE_PLUGINS_PROCESS_ELF_CORE_REGISTERCONTEXTPOSIXCORE_ARM_H
-#include "Plugins/Process/Utility/RegisterContextPOSIX_arm.h"
+#include "Plugins/Process/Common/RegisterContext/POSIX/RegisterContextPOSIX_arm.h"
#include "Plugins/Process/elf-core/RegisterUtilities.h"
#include "lldb/Utility/DataBufferHeap.h"
#include "lldb/Utility/DataExtractor.h"
diff --git a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.h b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.h
index c9314b6b7ea1d2..c241a27309bc01 100644
--- a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.h
+++ b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_arm64.h
@@ -10,7 +10,7 @@
#define LLDB_SOURCE_PLUGINS_PROCESS_ELF_CORE_REGISTERCONTEXTPOSIXCORE_ARM64_H
#include "Plugins/Process/Utility/LinuxPTraceDefines_arm64sve.h"
-#include "Plugins/Process/Utility/RegisterContextPOSIX_arm64.h"
+#include "Plugins/Process/Common/RegisterContext/POSIX/RegisterContextPOSIX_arm64.h"
#include "Register/Common/RegisterTypeDetector_arm64.h"
#include "Plugins/Process/elf-core/RegisterUtilities.h"
diff --git a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_loongarch64.h b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_loongarch64.h
index a12a23adf89dd0..b8e7b71930c965 100644
--- a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_loongarch64.h
+++ b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_loongarch64.h
@@ -9,7 +9,7 @@
#ifndef LLDB_SOURCE_PLUGINS_PROCESS_ELF_CORE_REGISTERCONTEXTPOSIXCORE_LOONGARCH64_H
#define LLDB_SOURCE_PLUGINS_PROCESS_ELF_CORE_REGISTERCONTEXTPOSIXCORE_LOONGARCH64_H
-#include "Plugins/Process/Utility/RegisterContextPOSIX_loongarch64.h"
+#include "Plugins/Process/Common/RegisterContext/POSIX/RegisterContextPOSIX_loongarch64.h"
#include "Register/Common/RegisterInfoCommon_loongarch64.h"
#include "Plugins/Process/elf-core/RegisterUtilities.h"
diff --git a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_powerpc.h b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_powerpc.h
index 5364c5589238a1..5b47bcae28fe8f 100644
--- a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_powerpc.h
+++ b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_powerpc.h
@@ -9,7 +9,7 @@
#ifndef LLDB_SOURCE_PLUGINS_PROCESS_ELF_CORE_REGISTERCONTEXTPOSIXCORE_POWERPC_H
#define LLDB_SOURCE_PLUGINS_PROCESS_ELF_CORE_REGISTERCONTEXTPOSIXCORE_POWERPC_H
-#include "Plugins/Process/Utility/RegisterContextPOSIX_powerpc.h"
+#include "Plugins/Process/Common/RegisterContext/POSIX/RegisterContextPOSIX_powerpc.h"
#include "Plugins/Process/elf-core/RegisterUtilities.h"
#include "lldb/Utility/DataExtractor.h"
diff --git a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_ppc64le.h b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_ppc64le.h
index 8de77a7e25bff0..4c7068485cc09d 100644
--- a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_ppc64le.h
+++ b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_ppc64le.h
@@ -9,7 +9,7 @@
#ifndef LLDB_SOURCE_PLUGINS_PROCESS_ELF_CORE_REGISTERCONTEXTPOSIXCORE_PPC64LE_H
#define LLDB_SOURCE_PLUGINS_PROCESS_ELF_CORE_REGISTERCONTEXTPOSIXCORE_PPC64LE_H
-#include "Plugins/Process/Utility/RegisterContextPOSIX_ppc64le.h"
+#include "Plugins/Process/Common/RegisterContext/POSIX/RegisterContextPOSIX_ppc64le.h"
#include "Plugins/Process/elf-core/RegisterUtilities.h"
#include "lldb/Utility/DataExtractor.h"
diff --git a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv64.h b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv64.h
index 22a67654bbc790..0ac278711f7fe7 100644
--- a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv64.h
+++ b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv64.h
@@ -9,7 +9,7 @@
#ifndef LLDB_SOURCE_PLUGINS_PROCESS_ELF_CORE_REGISTERCONTEXTPOSIXCORE_RISCV64_H
#define LLDB_SOURCE_PLUGINS_PROCESS_ELF_CORE_REGISTERCONTEXTPOSIXCORE_RISCV64_H
-#include "Plugins/Process/Utility/RegisterContextPOSIX_riscv64.h"
+#include "Plugins/Process/Common/RegisterContext/POSIX/RegisterContextPOSIX_riscv64.h"
#include "Register/Common/RegisterInfoCommon_riscv64.h"
#include "Plugins/Process/elf-core/RegisterUtilities.h"
diff --git a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_s390x.h b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_s390x.h
index edb7cbc9462f6a..d92a3740430ff2 100644
--- a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_s390x.h
+++ b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_s390x.h
@@ -9,7 +9,7 @@
#ifndef LLDB_SOURCE_PLUGINS_PROCESS_ELF_CORE_REGISTERCONTEXTPOSIXCORE_S390X_H
#define LLDB_SOURCE_PLUGINS_PROCESS_ELF_CORE_REGISTERCONTEXTPOSIXCORE_S390X_H
-#include "Plugins/Process/Utility/RegisterContextPOSIX_s390x.h"
+#include "Plugins/Process/Common/RegisterContext/POSIX/RegisterContextPOSIX_s390x.h"
#include "Plugins/Process/elf-core/RegisterUtilities.h"
#include "lldb/Utility/DataExtractor.h"
diff --git a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_x86.h b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_x86.h
index 56f910b18683ae..5e45f17b2a19e8 100644
--- a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_x86.h
+++ b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_x86.h
@@ -9,7 +9,7 @@
#ifndef LLDB_SOURCE_PLUGINS_PROCESS_ELF_CORE_REGISTERCONTEXTPOSIXCORE_X86_H
#define LLDB_SOURCE_PLUGINS_PROCESS_ELF_CORE_REGISTERCONTEXTPOSIXCORE_X86_H
-#include "Plugins/Process/Utility/RegisterContextPOSIX_x86.h"
+#include "Plugins/Process/Common/RegisterContext/POSIX/RegisterContextPOSIX_x86.h"
#include "Plugins/Process/elf-core/RegisterUtilities.h"
class RegisterContextCorePOSIX_x86 : public RegisterContextPOSIX_x86 {
diff --git a/lldb/source/Register/Arch/RegisterContext_powerpc.h b/lldb/source/Register/Arch/RegisterContext_powerpc.h
index 1ca6ac4685720f..070e5e1f10ccde 100644
--- a/lldb/source/Register/Arch/RegisterContext_powerpc.h
+++ b/lldb/source/Register/Arch/RegisterContext_powerpc.h
@@ -120,4 +120,125 @@ enum {
dwarf_v31_powerpc,
};
+// Internal codes for all powerpc registers.
+enum {
+ k_first_gpr_powerpc,
+ gpr_r0_powerpc = k_first_gpr_powerpc,
+ gpr_r1_powerpc,
+ gpr_r2_powerpc,
+ gpr_r3_powerpc,
+ gpr_r4_powerpc,
+ gpr_r5_powerpc,
+ gpr_r6_powerpc,
+ gpr_r7_powerpc,
+ gpr_r8_powerpc,
+ gpr_r9_powerpc,
+ gpr_r10_powerpc,
+ gpr_r11_powerpc,
+ gpr_r12_powerpc,
+ gpr_r13_powerpc,
+ gpr_r14_powerpc,
+ gpr_r15_powerpc,
+ gpr_r16_powerpc,
+ gpr_r17_powerpc,
+ gpr_r18_powerpc,
+ gpr_r19_powerpc,
+ gpr_r20_powerpc,
+ gpr_r21_powerpc,
+ gpr_r22_powerpc,
+ gpr_r23_powerpc,
+ gpr_r24_powerpc,
+ gpr_r25_powerpc,
+ gpr_r26_powerpc,
+ gpr_r27_powerpc,
+ gpr_r28_powerpc,
+ gpr_r29_powerpc,
+ gpr_r30_powerpc,
+ gpr_r31_powerpc,
+ gpr_lr_powerpc,
+ gpr_cr_powerpc,
+ gpr_xer_powerpc,
+ gpr_ctr_powerpc,
+ gpr_pc_powerpc,
+ k_last_gpr_powerpc = gpr_pc_powerpc,
+
+ k_first_fpr,
+ fpr_f0_powerpc = k_first_fpr,
+ fpr_f1_powerpc,
+ fpr_f2_powerpc,
+ fpr_f3_powerpc,
+ fpr_f4_powerpc,
+ fpr_f5_powerpc,
+ fpr_f6_powerpc,
+ fpr_f7_powerpc,
+ fpr_f8_powerpc,
+ fpr_f9_powerpc,
+ fpr_f10_powerpc,
+ fpr_f11_powerpc,
+ fpr_f12_powerpc,
+ fpr_f13_powerpc,
+ fpr_f14_powerpc,
+ fpr_f15_powerpc,
+ fpr_f16_powerpc,
+ fpr_f17_powerpc,
+ fpr_f18_powerpc,
+ fpr_f19_powerpc,
+ fpr_f20_powerpc,
+ fpr_f21_powerpc,
+ fpr_f22_powerpc,
+ fpr_f23_powerpc,
+ fpr_f24_powerpc,
+ fpr_f25_powerpc,
+ fpr_f26_powerpc,
+ fpr_f27_powerpc,
+ fpr_f28_powerpc,
+ fpr_f29_powerpc,
+ fpr_f30_powerpc,
+ fpr_f31_powerpc,
+ fpr_fpscr_powerpc,
+ k_last_fpr = fpr_fpscr_powerpc,
+
+ k_first_vmx,
+ vmx_v0_powerpc = k_first_vmx,
+ vmx_v1_powerpc,
+ vmx_v2_powerpc,
+ vmx_v3_powerpc,
+ vmx_v4_powerpc,
+ vmx_v5_powerpc,
+ vmx_v6_powerpc,
+ vmx_v7_powerpc,
+ vmx_v8_powerpc,
+ vmx_v9_powerpc,
+ vmx_v10_powerpc,
+ vmx_v11_powerpc,
+ vmx_v12_powerpc,
+ vmx_v13_powerpc,
+ vmx_v14_powerpc,
+ vmx_v15_powerpc,
+ vmx_v16_powerpc,
+ vmx_v17_powerpc,
+ vmx_v18_powerpc,
+ vmx_v19_powerpc,
+ vmx_v20_powerpc,
+ vmx_v21_powerpc,
+ vmx_v22_powerpc,
+ vmx_v23_powerpc,
+ vmx_v24_powerpc,
+ vmx_v25_powerpc,
+ vmx_v26_powerpc,
+ vmx_v27_powerpc,
+ vmx_v28_powerpc,
+ vmx_v29_powerpc,
+ vmx_v30_powerpc,
+ vmx_v31_powerpc,
+ vmx_vrsave_powerpc,
+ vmx_vscr_powerpc,
+ k_last_vmx = vmx_vscr_powerpc,
+
+ k_num_registers_powerpc,
+ k_num_gpr_registers_powerpc = k_last_gpr_powerpc - k_first_gpr_powerpc + 1,
+ k_num_fpr_registers_powerpc = k_last_fpr - k_first_fpr + 1,
+ k_num_vmx_registers_powerpc = k_last_vmx - k_first_vmx + 1,
+};
+
#endif // LLDB_SOURCE_REGISTER_ARCH_REGISTERCONTEXT_POWERPC_H
diff --git a/lldb/source/Register/FreeBSD/RegisterInfoFreeBSD_powerpc.cpp b/lldb/source/Register/FreeBSD/RegisterInfoFreeBSD_powerpc.cpp
index 7213723fdfc1c0..4a5ee015c9192f 100644
--- a/lldb/source/Register/FreeBSD/RegisterInfoFreeBSD_powerpc.cpp
+++ b/lldb/source/Register/FreeBSD/RegisterInfoFreeBSD_powerpc.cpp
@@ -7,7 +7,8 @@
//===---------------------------------------------------------------------===//
#include "Register/FreeBSD/RegisterInfoFreeBSD_powerpc.h"
-#include "Plugins/Process/Utility/RegisterContextPOSIX_powerpc.h"
+#include "Register/Arch/RegisterContext_powerpc.h"
+#include "lldb/lldb-defines.h"
#include <vector>
using namespace lldb_private;
diff --git a/lldb/source/Register/Linux/RegisterInfoLinux_s390x.cpp b/lldb/source/Register/Linux/RegisterInfoLinux_s390x.cpp
index 682b83f723ade2..b2abed1d3ed9c4 100644
--- a/lldb/source/Register/Linux/RegisterInfoLinux_s390x.cpp
+++ b/lldb/source/Register/Linux/RegisterInfoLinux_s390x.cpp
@@ -7,7 +7,9 @@
//===----------------------------------------------------------------------===//
#include "Register/Linux/RegisterInfoLinux_s390x.h"
-#include "Plugins/Process/Utility/RegisterContextPOSIX_s390x.h"
+#include "Register/Arch/RegisterContext_s390x.h"
+#include "Register/Arch/lldb-s390x-register-enums.h"
+#include "lldb/lldb-defines.h"
using namespace lldb_private;
using namespace lldb;
diff --git a/lldb/unittests/Process/Utility/CMakeLists.txt b/lldb/unittests/Process/Utility/CMakeLists.txt
index c7dc4e969bd6f4..8b5118b9f36b96 100644
--- a/lldb/unittests/Process/Utility/CMakeLists.txt
+++ b/lldb/unittests/Process/Utility/CMakeLists.txt
@@ -30,4 +30,5 @@ add_lldb_unittest(RegisterSupportTests
${PLATFORM_SOURCES}
LINK_LIBS
- lldbRegister)
+ lldbRegister
+ lldbProcessContextSupport)
diff --git a/lldb/unittests/Process/Utility/RegisterInfoFreeBSDTest.cpp b/lldb/unittests/Process/Utility/RegisterInfoFreeBSDTest.cpp
index 332100f5c9c8fd..327071cb682c66 100644
--- a/lldb/unittests/Process/Utility/RegisterInfoFreeBSDTest.cpp
+++ b/lldb/unittests/Process/Utility/RegisterInfoFreeBSDTest.cpp
@@ -20,7 +20,7 @@
#include "Register/FreeBSD/RegisterInfoFreeBSD_i386.h"
#include "Register/FreeBSD/RegisterInfoFreeBSD_powerpc.h"
#include "Register/FreeBSD/RegisterInfoFreeBSD_x86_64.h"
-#include "Plugins/Process/Utility/RegisterContextPOSIX_powerpc.h"
+#include "Plugins/Process/Common/RegisterContext/POSIX/RegisterContextPOSIX_powerpc.h"
#include "Register/Common/RegisterInfoCommon_arm.h"
#include "Register/Common/RegisterInfoCommon_arm64.h"
#include "Register/Arch/lldb-arm-register-enums.h"
diff --git a/llvm/utils/gn/secondary/lldb/source/Plugins/Process/Common/BUILD.gn b/llvm/utils/gn/secondary/lldb/source/Plugins/Process/Common/BUILD.gn
new file mode 100644
index 00000000000000..f566b4336cafff
--- /dev/null
+++ b/llvm/utils/gn/secondary/lldb/source/Plugins/Process/Common/BUILD.gn
@@ -0,0 +1,23 @@
+static_library("Common") {
+ output_name = "lldbProcessContextSupport"
+ configs += [ "//llvm/utils/gn/build:lldb_code" ]
+ deps = [
+ "//lldb/source/Register",
+ "//lldb/source/Target",
+ "//lldb/source/Utility",
+ "//llvm/lib/Support",
+ ]
+
+ include_dirs = [ "//lldb/source" ]
+ sources = [
+ "RegisterContext/POSIX/RegisterContextPOSIX_arm.cpp",
+ "RegisterContext/POSIX/RegisterContextPOSIX_arm64.cpp",
+ "RegisterContext/POSIX/RegisterContextPOSIX_loongarch64.cpp",
+ "RegisterContext/POSIX/RegisterContextPOSIX_powerpc.cpp",
+ "RegisterContext/POSIX/RegisterContextPOSIX_ppc64le.cpp",
+ "RegisterContext/POSIX/RegisterContextPOSIX_riscv32.cpp",
+ "RegisterContext/POSIX/RegisterContextPOSIX_riscv64.cpp",
+ "RegisterContext/POSIX/RegisterContextPOSIX_s390x.cpp",
+ "RegisterContext/POSIX/RegisterContextPOSIX_x86.cpp",
+ ]
+}
diff --git a/llvm/utils/gn/secondary/lldb/source/Plugins/Process/Utility/BUILD.gn b/llvm/utils/gn/secondary/lldb/source/Plugins/Process/Utility/BUILD.gn
index 175599f39f62ec..a2ffee0f15f19b 100644
--- a/llvm/utils/gn/secondary/lldb/source/Plugins/Process/Utility/BUILD.gn
+++ b/llvm/utils/gn/secondary/lldb/source/Plugins/Process/Utility/BUILD.gn
@@ -41,15 +41,6 @@ static_library("Utility") {
"RegisterContextMach_arm.cpp",
"RegisterContextMach_x86_64.cpp",
"RegisterContextMemory.cpp",
- "RegisterContextPOSIX_arm.cpp",
- "RegisterContextPOSIX_arm64.cpp",
- "RegisterContextPOSIX_loongarch64.cpp",
- "RegisterContextPOSIX_powerpc.cpp",
- "RegisterContextPOSIX_ppc64le.cpp",
- "RegisterContextPOSIX_riscv32.cpp",
- "RegisterContextPOSIX_riscv64.cpp",
- "RegisterContextPOSIX_s390x.cpp",
- "RegisterContextPOSIX_x86.cpp",
"RegisterContextThreadMemory.cpp",
"StopInfoMachException.cpp",
"ThreadMemory.cpp",
diff --git a/llvm/utils/gn/secondary/lldb/source/Plugins/Process/elf-core/BUILD.gn b/llvm/utils/gn/secondary/lldb/source/Plugins/Process/elf-core/BUILD.gn
index c102b6abce9658..2475f2f46069ee 100644
--- a/llvm/utils/gn/secondary/lldb/source/Plugins/Process/elf-core/BUILD.gn
+++ b/llvm/utils/gn/secondary/lldb/source/Plugins/Process/elf-core/BUILD.gn
@@ -5,6 +5,7 @@ static_library("elf-core") {
"//lldb/source/Core",
"//lldb/source/Plugins/DynamicLoader/POSIX-DYLD",
"//lldb/source/Plugins/ObjectFile/ELF",
+ "//lldb/source/Plugins/Process/Common",
"//lldb/source/Plugins/Process/Utility",
"//lldb/source/Target",
"//llvm/lib/BinaryFormat",
>From 5ccb963b1646d243ea98233736b3261dec63ec35 Mon Sep 17 00:00:00 2001
From: Minsoo Choo <minsoo at minsoo.io>
Date: Sun, 6 Sep 2026 10:14:33 -0400
Subject: [PATCH 5/5] [lldb] Isolate reusable Darwin register contexts
---
lldb/source/Plugins/ObjectFile/Mach-O/CMakeLists.txt | 2 +-
lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp | 8 ++++----
lldb/source/Plugins/Process/Common/CMakeLists.txt | 6 ++++++
.../Darwin}/RegisterContextDarwinConstants.h | 6 +++---
.../RegisterContext/Darwin}/RegisterContextDarwin_arm.cpp | 0
.../RegisterContext/Darwin}/RegisterContextDarwin_arm.h | 6 +++---
.../Darwin}/RegisterContextDarwin_arm64.cpp | 2 +-
.../RegisterContext/Darwin}/RegisterContextDarwin_arm64.h | 6 +++---
.../Darwin}/RegisterContextDarwin_riscv32.cpp | 0
.../Darwin}/RegisterContextDarwin_riscv32.h | 6 +++---
.../Darwin}/RegisterContextDarwin_x86_64.cpp | 0
.../Darwin}/RegisterContextDarwin_x86_64.h | 6 +++---
.../RegisterContext/Darwin}/RegisterContextMach_arm.cpp | 0
.../RegisterContext/Darwin}/RegisterContextMach_arm.h | 6 +++---
.../Darwin}/RegisterContextMach_x86_64.cpp | 0
.../RegisterContext/Darwin}/RegisterContextMach_x86_64.h | 6 +++---
lldb/source/Plugins/Process/MacOSX-Kernel/CMakeLists.txt | 2 +-
.../Process/MacOSX-Kernel/RegisterContextKDP_arm.h | 2 +-
.../Process/MacOSX-Kernel/RegisterContextKDP_arm64.h | 2 +-
.../Process/MacOSX-Kernel/RegisterContextKDP_x86_64.h | 2 +-
lldb/source/Plugins/Process/Utility/CMakeLists.txt | 6 ------
.../lldb/source/Plugins/ObjectFile/Mach-O/BUILD.gn | 2 +-
.../secondary/lldb/source/Plugins/Process/Common/BUILD.gn | 6 ++++++
.../lldb/source/Plugins/Process/Utility/BUILD.gn | 6 ------
24 files changed, 44 insertions(+), 44 deletions(-)
rename lldb/source/Plugins/Process/{Utility => Common/RegisterContext/Darwin}/RegisterContextDarwinConstants.h (67%)
rename lldb/source/Plugins/Process/{Utility => Common/RegisterContext/Darwin}/RegisterContextDarwin_arm.cpp (100%)
rename lldb/source/Plugins/Process/{Utility => Common/RegisterContext/Darwin}/RegisterContextDarwin_arm.h (96%)
rename lldb/source/Plugins/Process/{Utility => Common/RegisterContext/Darwin}/RegisterContextDarwin_arm64.cpp (99%)
rename lldb/source/Plugins/Process/{Utility => Common/RegisterContext/Darwin}/RegisterContextDarwin_arm64.h (95%)
rename lldb/source/Plugins/Process/{Utility => Common/RegisterContext/Darwin}/RegisterContextDarwin_riscv32.cpp (100%)
rename lldb/source/Plugins/Process/{Utility => Common/RegisterContext/Darwin}/RegisterContextDarwin_riscv32.h (95%)
rename lldb/source/Plugins/Process/{Utility => Common/RegisterContext/Darwin}/RegisterContextDarwin_x86_64.cpp (100%)
rename lldb/source/Plugins/Process/{Utility => Common/RegisterContext/Darwin}/RegisterContextDarwin_x86_64.h (94%)
rename lldb/source/Plugins/Process/{Utility => Common/RegisterContext/Darwin}/RegisterContextMach_arm.cpp (100%)
rename lldb/source/Plugins/Process/{Utility => Common/RegisterContext/Darwin}/RegisterContextMach_arm.h (81%)
rename lldb/source/Plugins/Process/{Utility => Common/RegisterContext/Darwin}/RegisterContextMach_x86_64.cpp (100%)
rename lldb/source/Plugins/Process/{Utility => Common/RegisterContext/Darwin}/RegisterContextMach_x86_64.h (79%)
diff --git a/lldb/source/Plugins/ObjectFile/Mach-O/CMakeLists.txt b/lldb/source/Plugins/ObjectFile/Mach-O/CMakeLists.txt
index 6bd4ab32e28ce2..566252aa312351 100644
--- a/lldb/source/Plugins/ObjectFile/Mach-O/CMakeLists.txt
+++ b/lldb/source/Plugins/ObjectFile/Mach-O/CMakeLists.txt
@@ -5,10 +5,10 @@ add_lldb_library(lldbPluginObjectFileMachO PLUGIN
LINK_COMPONENTS
Support
LINK_LIBS
+ lldbProcessContextSupport
lldbCore
lldbHost
lldbSymbol
lldbTarget
lldbUtility
- lldbPluginProcessUtility
)
diff --git a/lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp b/lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp
index 4570df57c42cb3..a6a756b9ac123a 100644
--- a/lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp
+++ b/lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp
@@ -11,10 +11,10 @@
#include <algorithm>
-#include "Plugins/Process/Utility/RegisterContextDarwin_arm.h"
-#include "Plugins/Process/Utility/RegisterContextDarwin_arm64.h"
-#include "Plugins/Process/Utility/RegisterContextDarwin_riscv32.h"
-#include "Plugins/Process/Utility/RegisterContextDarwin_x86_64.h"
+#include "Plugins/Process/Common/RegisterContext/Darwin/RegisterContextDarwin_arm.h"
+#include "Plugins/Process/Common/RegisterContext/Darwin/RegisterContextDarwin_arm64.h"
+#include "Plugins/Process/Common/RegisterContext/Darwin/RegisterContextDarwin_riscv32.h"
+#include "Plugins/Process/Common/RegisterContext/Darwin/RegisterContextDarwin_x86_64.h"
#include "lldb/Core/Debugger.h"
#include "lldb/Core/Module.h"
#include "lldb/Core/ModuleSpec.h"
diff --git a/lldb/source/Plugins/Process/Common/CMakeLists.txt b/lldb/source/Plugins/Process/Common/CMakeLists.txt
index f9f7289f9c1276..519569fc22e16a 100644
--- a/lldb/source/Plugins/Process/Common/CMakeLists.txt
+++ b/lldb/source/Plugins/Process/Common/CMakeLists.txt
@@ -1,4 +1,10 @@
add_lldb_library(lldbProcessContextSupport NO_PLUGIN_DEPENDENCIES
+ RegisterContext/Darwin/RegisterContextDarwin_arm.cpp
+ RegisterContext/Darwin/RegisterContextDarwin_arm64.cpp
+ RegisterContext/Darwin/RegisterContextDarwin_riscv32.cpp
+ RegisterContext/Darwin/RegisterContextDarwin_x86_64.cpp
+ RegisterContext/Darwin/RegisterContextMach_arm.cpp
+ RegisterContext/Darwin/RegisterContextMach_x86_64.cpp
RegisterContext/POSIX/RegisterContextPOSIX_arm.cpp
RegisterContext/POSIX/RegisterContextPOSIX_arm64.cpp
RegisterContext/POSIX/RegisterContextPOSIX_loongarch64.cpp
diff --git a/lldb/source/Plugins/Process/Utility/RegisterContextDarwinConstants.h b/lldb/source/Plugins/Process/Common/RegisterContext/Darwin/RegisterContextDarwinConstants.h
similarity index 67%
rename from lldb/source/Plugins/Process/Utility/RegisterContextDarwinConstants.h
rename to lldb/source/Plugins/Process/Common/RegisterContext/Darwin/RegisterContextDarwinConstants.h
index 21582df91fb039..e06eaaf5c166ce 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterContextDarwinConstants.h
+++ b/lldb/source/Plugins/Process/Common/RegisterContext/Darwin/RegisterContextDarwinConstants.h
@@ -6,8 +6,8 @@
//
//===----------------------------------------------------------------------===//
-#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTDARWINCONSTANTS_H
-#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTDARWINCONSTANTS_H
+#ifndef LLDB_SOURCE_PLUGINS_PROCESS_COMMON_REGISTERCONTEXT_DARWIN_REGISTERCONTEXTDARWINCONSTANTS_H
+#define LLDB_SOURCE_PLUGINS_PROCESS_COMMON_REGISTERCONTEXT_DARWIN_REGISTERCONTEXTDARWINCONSTANTS_H
namespace lldb_private {
@@ -22,4 +22,4 @@ namespace lldb_private {
} // namespace lldb_private
-#endif // LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTDARWINCONSTANTS_H
+#endif // LLDB_SOURCE_PLUGINS_PROCESS_COMMON_REGISTERCONTEXT_DARWIN_REGISTERCONTEXTDARWINCONSTANTS_H
diff --git a/lldb/source/Plugins/Process/Utility/RegisterContextDarwin_arm.cpp b/lldb/source/Plugins/Process/Common/RegisterContext/Darwin/RegisterContextDarwin_arm.cpp
similarity index 100%
rename from lldb/source/Plugins/Process/Utility/RegisterContextDarwin_arm.cpp
rename to lldb/source/Plugins/Process/Common/RegisterContext/Darwin/RegisterContextDarwin_arm.cpp
diff --git a/lldb/source/Plugins/Process/Utility/RegisterContextDarwin_arm.h b/lldb/source/Plugins/Process/Common/RegisterContext/Darwin/RegisterContextDarwin_arm.h
similarity index 96%
rename from lldb/source/Plugins/Process/Utility/RegisterContextDarwin_arm.h
rename to lldb/source/Plugins/Process/Common/RegisterContext/Darwin/RegisterContextDarwin_arm.h
index 7ff1bded81f4b7..5521caa38cf6b6 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterContextDarwin_arm.h
+++ b/lldb/source/Plugins/Process/Common/RegisterContext/Darwin/RegisterContextDarwin_arm.h
@@ -6,8 +6,8 @@
//
//===----------------------------------------------------------------------===//
-#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTDARWIN_ARM_H
-#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTDARWIN_ARM_H
+#ifndef LLDB_SOURCE_PLUGINS_PROCESS_COMMON_REGISTERCONTEXT_DARWIN_REGISTERCONTEXTDARWIN_ARM_H
+#define LLDB_SOURCE_PLUGINS_PROCESS_COMMON_REGISTERCONTEXT_DARWIN_REGISTERCONTEXTDARWIN_ARM_H
#include "lldb/Target/RegisterContext.h"
#include "lldb/lldb-private.h"
@@ -261,4 +261,4 @@ class RegisterContextDarwin_arm : public lldb_private::RegisterContext {
static const lldb_private::RegisterInfo *GetRegisterInfos();
};
-#endif // LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTDARWIN_ARM_H
+#endif // LLDB_SOURCE_PLUGINS_PROCESS_COMMON_REGISTERCONTEXT_DARWIN_REGISTERCONTEXTDARWIN_ARM_H
diff --git a/lldb/source/Plugins/Process/Utility/RegisterContextDarwin_arm64.cpp b/lldb/source/Plugins/Process/Common/RegisterContext/Darwin/RegisterContextDarwin_arm64.cpp
similarity index 99%
rename from lldb/source/Plugins/Process/Utility/RegisterContextDarwin_arm64.cpp
rename to lldb/source/Plugins/Process/Common/RegisterContext/Darwin/RegisterContextDarwin_arm64.cpp
index 43338c8cbc792f..0b30d3f3fa8172 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterContextDarwin_arm64.cpp
+++ b/lldb/source/Plugins/Process/Common/RegisterContext/Darwin/RegisterContextDarwin_arm64.cpp
@@ -67,7 +67,7 @@ using namespace lldb_private;
// Include RegisterInfos_arm64 to declare our g_register_infos_arm64 structure.
#define DECLARE_REGISTER_INFOS_ARM64_STRUCT
-#include "RegisterInfos_arm64.h"
+#include "Register/Arch/RegisterInfos_arm64.h"
#undef DECLARE_REGISTER_INFOS_ARM64_STRUCT
// General purpose registers
diff --git a/lldb/source/Plugins/Process/Utility/RegisterContextDarwin_arm64.h b/lldb/source/Plugins/Process/Common/RegisterContext/Darwin/RegisterContextDarwin_arm64.h
similarity index 95%
rename from lldb/source/Plugins/Process/Utility/RegisterContextDarwin_arm64.h
rename to lldb/source/Plugins/Process/Common/RegisterContext/Darwin/RegisterContextDarwin_arm64.h
index a0d7821ae9e8b5..bfc70243af5760 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterContextDarwin_arm64.h
+++ b/lldb/source/Plugins/Process/Common/RegisterContext/Darwin/RegisterContextDarwin_arm64.h
@@ -7,8 +7,8 @@
//
//===----------------------------------------------------------------------===//
-#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTDARWIN_ARM64_H
-#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTDARWIN_ARM64_H
+#ifndef LLDB_SOURCE_PLUGINS_PROCESS_COMMON_REGISTERCONTEXT_DARWIN_REGISTERCONTEXTDARWIN_ARM64_H
+#define LLDB_SOURCE_PLUGINS_PROCESS_COMMON_REGISTERCONTEXT_DARWIN_REGISTERCONTEXTDARWIN_ARM64_H
#include "lldb/Target/RegisterContext.h"
#include "lldb/lldb-private.h"
@@ -228,4 +228,4 @@ class RegisterContextDarwin_arm64 : public lldb_private::RegisterContext {
static const lldb_private::RegisterInfo *GetRegisterInfos();
};
-#endif // LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTDARWIN_ARM64_H
+#endif // LLDB_SOURCE_PLUGINS_PROCESS_COMMON_REGISTERCONTEXT_DARWIN_REGISTERCONTEXTDARWIN_ARM64_H
diff --git a/lldb/source/Plugins/Process/Utility/RegisterContextDarwin_riscv32.cpp b/lldb/source/Plugins/Process/Common/RegisterContext/Darwin/RegisterContextDarwin_riscv32.cpp
similarity index 100%
rename from lldb/source/Plugins/Process/Utility/RegisterContextDarwin_riscv32.cpp
rename to lldb/source/Plugins/Process/Common/RegisterContext/Darwin/RegisterContextDarwin_riscv32.cpp
diff --git a/lldb/source/Plugins/Process/Utility/RegisterContextDarwin_riscv32.h b/lldb/source/Plugins/Process/Common/RegisterContext/Darwin/RegisterContextDarwin_riscv32.h
similarity index 95%
rename from lldb/source/Plugins/Process/Utility/RegisterContextDarwin_riscv32.h
rename to lldb/source/Plugins/Process/Common/RegisterContext/Darwin/RegisterContextDarwin_riscv32.h
index 22d61aef712a60..9655a87e07d040 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterContextDarwin_riscv32.h
+++ b/lldb/source/Plugins/Process/Common/RegisterContext/Darwin/RegisterContextDarwin_riscv32.h
@@ -6,8 +6,8 @@
//
//===----------------------------------------------------------------------===//
-#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTDARWIN_RISCV32_H
-#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTDARWIN_RISCV32_H
+#ifndef LLDB_SOURCE_PLUGINS_PROCESS_COMMON_REGISTERCONTEXT_DARWIN_REGISTERCONTEXTDARWIN_RISCV32_H
+#define LLDB_SOURCE_PLUGINS_PROCESS_COMMON_REGISTERCONTEXT_DARWIN_REGISTERCONTEXTDARWIN_RISCV32_H
#include "lldb/Target/RegisterContext.h"
#include "lldb/lldb-private.h"
@@ -257,4 +257,4 @@ class RegisterContextDarwin_riscv32 : public lldb_private::RegisterContext {
static const lldb_private::RegisterInfo *GetRegisterInfos();
};
-#endif // LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTDARWIN_RISCV32_H
+#endif // LLDB_SOURCE_PLUGINS_PROCESS_COMMON_REGISTERCONTEXT_DARWIN_REGISTERCONTEXTDARWIN_RISCV32_H
diff --git a/lldb/source/Plugins/Process/Utility/RegisterContextDarwin_x86_64.cpp b/lldb/source/Plugins/Process/Common/RegisterContext/Darwin/RegisterContextDarwin_x86_64.cpp
similarity index 100%
rename from lldb/source/Plugins/Process/Utility/RegisterContextDarwin_x86_64.cpp
rename to lldb/source/Plugins/Process/Common/RegisterContext/Darwin/RegisterContextDarwin_x86_64.cpp
diff --git a/lldb/source/Plugins/Process/Utility/RegisterContextDarwin_x86_64.h b/lldb/source/Plugins/Process/Common/RegisterContext/Darwin/RegisterContextDarwin_x86_64.h
similarity index 94%
rename from lldb/source/Plugins/Process/Utility/RegisterContextDarwin_x86_64.h
rename to lldb/source/Plugins/Process/Common/RegisterContext/Darwin/RegisterContextDarwin_x86_64.h
index a132f92d4d497b..27ee7e8f0b155d 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterContextDarwin_x86_64.h
+++ b/lldb/source/Plugins/Process/Common/RegisterContext/Darwin/RegisterContextDarwin_x86_64.h
@@ -6,8 +6,8 @@
//
//===----------------------------------------------------------------------===//
-#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTDARWIN_X86_64_H
-#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTDARWIN_X86_64_H
+#ifndef LLDB_SOURCE_PLUGINS_PROCESS_COMMON_REGISTERCONTEXT_DARWIN_REGISTERCONTEXTDARWIN_X86_64_H
+#define LLDB_SOURCE_PLUGINS_PROCESS_COMMON_REGISTERCONTEXT_DARWIN_REGISTERCONTEXTDARWIN_X86_64_H
#include "lldb/Target/RegisterContext.h"
#include "lldb/lldb-private.h"
@@ -210,4 +210,4 @@ class RegisterContextDarwin_x86_64 : public lldb_private::RegisterContext {
static const lldb_private::RegisterInfo *GetRegisterInfos();
};
-#endif // LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTDARWIN_X86_64_H
+#endif // LLDB_SOURCE_PLUGINS_PROCESS_COMMON_REGISTERCONTEXT_DARWIN_REGISTERCONTEXTDARWIN_X86_64_H
diff --git a/lldb/source/Plugins/Process/Utility/RegisterContextMach_arm.cpp b/lldb/source/Plugins/Process/Common/RegisterContext/Darwin/RegisterContextMach_arm.cpp
similarity index 100%
rename from lldb/source/Plugins/Process/Utility/RegisterContextMach_arm.cpp
rename to lldb/source/Plugins/Process/Common/RegisterContext/Darwin/RegisterContextMach_arm.cpp
diff --git a/lldb/source/Plugins/Process/Utility/RegisterContextMach_arm.h b/lldb/source/Plugins/Process/Common/RegisterContext/Darwin/RegisterContextMach_arm.h
similarity index 81%
rename from lldb/source/Plugins/Process/Utility/RegisterContextMach_arm.h
rename to lldb/source/Plugins/Process/Common/RegisterContext/Darwin/RegisterContextMach_arm.h
index fedd0062c99c7d..d56271a1a19e25 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterContextMach_arm.h
+++ b/lldb/source/Plugins/Process/Common/RegisterContext/Darwin/RegisterContextMach_arm.h
@@ -6,8 +6,8 @@
//
//===----------------------------------------------------------------------===//
-#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTMACH_ARM_H
-#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTMACH_ARM_H
+#ifndef LLDB_SOURCE_PLUGINS_PROCESS_COMMON_REGISTERCONTEXT_DARWIN_REGISTERCONTEXTMACH_ARM_H
+#define LLDB_SOURCE_PLUGINS_PROCESS_COMMON_REGISTERCONTEXT_DARWIN_REGISTERCONTEXTMACH_ARM_H
#include "RegisterContextDarwin_arm.h"
@@ -36,4 +36,4 @@ class RegisterContextMach_arm : public RegisterContextDarwin_arm {
int DoWriteDBG(lldb::tid_t tid, int flavor, const DBG &dbg) override;
};
-#endif // LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTMACH_ARM_H
+#endif // LLDB_SOURCE_PLUGINS_PROCESS_COMMON_REGISTERCONTEXT_DARWIN_REGISTERCONTEXTMACH_ARM_H
diff --git a/lldb/source/Plugins/Process/Utility/RegisterContextMach_x86_64.cpp b/lldb/source/Plugins/Process/Common/RegisterContext/Darwin/RegisterContextMach_x86_64.cpp
similarity index 100%
rename from lldb/source/Plugins/Process/Utility/RegisterContextMach_x86_64.cpp
rename to lldb/source/Plugins/Process/Common/RegisterContext/Darwin/RegisterContextMach_x86_64.cpp
diff --git a/lldb/source/Plugins/Process/Utility/RegisterContextMach_x86_64.h b/lldb/source/Plugins/Process/Common/RegisterContext/Darwin/RegisterContextMach_x86_64.h
similarity index 79%
rename from lldb/source/Plugins/Process/Utility/RegisterContextMach_x86_64.h
rename to lldb/source/Plugins/Process/Common/RegisterContext/Darwin/RegisterContextMach_x86_64.h
index 99841a8e9a8d2d..ac4e31050de4cd 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterContextMach_x86_64.h
+++ b/lldb/source/Plugins/Process/Common/RegisterContext/Darwin/RegisterContextMach_x86_64.h
@@ -7,8 +7,8 @@
//
//===----------------------------------------------------------------------===//
-#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTMACH_X86_64_H
-#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTMACH_X86_64_H
+#ifndef LLDB_SOURCE_PLUGINS_PROCESS_COMMON_REGISTERCONTEXT_DARWIN_REGISTERCONTEXTMACH_X86_64_H
+#define LLDB_SOURCE_PLUGINS_PROCESS_COMMON_REGISTERCONTEXT_DARWIN_REGISTERCONTEXTMACH_X86_64_H
#include "RegisterContextDarwin_x86_64.h"
@@ -33,4 +33,4 @@ class RegisterContextMach_x86_64 : public RegisterContextDarwin_x86_64 {
int DoWriteEXC(lldb::tid_t tid, int flavor, const EXC &exc) override;
};
-#endif // LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTMACH_X86_64_H
+#endif // LLDB_SOURCE_PLUGINS_PROCESS_COMMON_REGISTERCONTEXT_DARWIN_REGISTERCONTEXTMACH_X86_64_H
diff --git a/lldb/source/Plugins/Process/MacOSX-Kernel/CMakeLists.txt b/lldb/source/Plugins/Process/MacOSX-Kernel/CMakeLists.txt
index f84d468bea5537..87b18ea0c6871c 100644
--- a/lldb/source/Plugins/Process/MacOSX-Kernel/CMakeLists.txt
+++ b/lldb/source/Plugins/Process/MacOSX-Kernel/CMakeLists.txt
@@ -21,6 +21,7 @@ if (CMAKE_SYSTEM_NAME MATCHES "Darwin")
ThreadKDP.cpp
LINK_LIBS
+ lldbProcessContextSupport
lldbBreakpoint
lldbCore
lldbHost
@@ -30,7 +31,6 @@ if (CMAKE_SYSTEM_NAME MATCHES "Darwin")
lldbUtility
lldbPluginDynamicLoaderDarwinKernel
lldbPluginDynamicLoaderStatic
- lldbPluginProcessUtility
)
add_dependencies(lldbPluginProcessMacOSXKernel
diff --git a/lldb/source/Plugins/Process/MacOSX-Kernel/RegisterContextKDP_arm.h b/lldb/source/Plugins/Process/MacOSX-Kernel/RegisterContextKDP_arm.h
index 5e8f5fad133e29..aa667e4d3e9081 100644
--- a/lldb/source/Plugins/Process/MacOSX-Kernel/RegisterContextKDP_arm.h
+++ b/lldb/source/Plugins/Process/MacOSX-Kernel/RegisterContextKDP_arm.h
@@ -9,7 +9,7 @@
#ifndef LLDB_SOURCE_PLUGINS_PROCESS_MACOSX_KERNEL_REGISTERCONTEXTKDP_ARM_H
#define LLDB_SOURCE_PLUGINS_PROCESS_MACOSX_KERNEL_REGISTERCONTEXTKDP_ARM_H
-#include "Plugins/Process/Utility/RegisterContextDarwin_arm.h"
+#include "Plugins/Process/Common/RegisterContext/Darwin/RegisterContextDarwin_arm.h"
class ThreadKDP;
diff --git a/lldb/source/Plugins/Process/MacOSX-Kernel/RegisterContextKDP_arm64.h b/lldb/source/Plugins/Process/MacOSX-Kernel/RegisterContextKDP_arm64.h
index d88d03e273fe3c..5c1007deeffcf6 100644
--- a/lldb/source/Plugins/Process/MacOSX-Kernel/RegisterContextKDP_arm64.h
+++ b/lldb/source/Plugins/Process/MacOSX-Kernel/RegisterContextKDP_arm64.h
@@ -10,7 +10,7 @@
#ifndef LLDB_SOURCE_PLUGINS_PROCESS_MACOSX_KERNEL_REGISTERCONTEXTKDP_ARM64_H
#define LLDB_SOURCE_PLUGINS_PROCESS_MACOSX_KERNEL_REGISTERCONTEXTKDP_ARM64_H
-#include "Plugins/Process/Utility/RegisterContextDarwin_arm64.h"
+#include "Plugins/Process/Common/RegisterContext/Darwin/RegisterContextDarwin_arm64.h"
class ThreadKDP;
diff --git a/lldb/source/Plugins/Process/MacOSX-Kernel/RegisterContextKDP_x86_64.h b/lldb/source/Plugins/Process/MacOSX-Kernel/RegisterContextKDP_x86_64.h
index 8e837c0630ab00..9a332aea237a9f 100644
--- a/lldb/source/Plugins/Process/MacOSX-Kernel/RegisterContextKDP_x86_64.h
+++ b/lldb/source/Plugins/Process/MacOSX-Kernel/RegisterContextKDP_x86_64.h
@@ -9,7 +9,7 @@
#ifndef LLDB_SOURCE_PLUGINS_PROCESS_MACOSX_KERNEL_REGISTERCONTEXTKDP_X86_64_H
#define LLDB_SOURCE_PLUGINS_PROCESS_MACOSX_KERNEL_REGISTERCONTEXTKDP_X86_64_H
-#include "Plugins/Process/Utility/RegisterContextDarwin_x86_64.h"
+#include "Plugins/Process/Common/RegisterContext/Darwin/RegisterContextDarwin_x86_64.h"
class ThreadKDP;
diff --git a/lldb/source/Plugins/Process/Utility/CMakeLists.txt b/lldb/source/Plugins/Process/Utility/CMakeLists.txt
index 6dbd6a5279e9cc..78bcd3b52d23e7 100644
--- a/lldb/source/Plugins/Process/Utility/CMakeLists.txt
+++ b/lldb/source/Plugins/Process/Utility/CMakeLists.txt
@@ -14,14 +14,8 @@ add_lldb_library(lldbPluginProcessUtility
NativeProcessSoftwareSingleStep.cpp
NetBSDSignals.cpp
OpenBSDSignals.cpp
- RegisterContextDarwin_arm.cpp
- RegisterContextDarwin_arm64.cpp
- RegisterContextDarwin_riscv32.cpp
- RegisterContextDarwin_x86_64.cpp
RegisterContextDummy.cpp
RegisterContextHistory.cpp
- RegisterContextMach_arm.cpp
- RegisterContextMach_x86_64.cpp
RegisterContextMemory.cpp
RegisterContextThreadMemory.cpp
StopInfoMachException.cpp
diff --git a/llvm/utils/gn/secondary/lldb/source/Plugins/ObjectFile/Mach-O/BUILD.gn b/llvm/utils/gn/secondary/lldb/source/Plugins/ObjectFile/Mach-O/BUILD.gn
index c321d989a7ed64..3c72603b995bc7 100644
--- a/llvm/utils/gn/secondary/lldb/source/Plugins/ObjectFile/Mach-O/BUILD.gn
+++ b/llvm/utils/gn/secondary/lldb/source/Plugins/ObjectFile/Mach-O/BUILD.gn
@@ -4,7 +4,7 @@ static_library("Mach-O") {
deps = [
"//lldb/source/Core",
"//lldb/source/Host",
- "//lldb/source/Plugins/Process/Utility",
+ "//lldb/source/Plugins/Process/Common",
"//lldb/source/Symbol",
"//lldb/source/Target",
"//lldb/source/Utility",
diff --git a/llvm/utils/gn/secondary/lldb/source/Plugins/Process/Common/BUILD.gn b/llvm/utils/gn/secondary/lldb/source/Plugins/Process/Common/BUILD.gn
index f566b4336cafff..f2dde58504d37d 100644
--- a/llvm/utils/gn/secondary/lldb/source/Plugins/Process/Common/BUILD.gn
+++ b/llvm/utils/gn/secondary/lldb/source/Plugins/Process/Common/BUILD.gn
@@ -10,6 +10,12 @@ static_library("Common") {
include_dirs = [ "//lldb/source" ]
sources = [
+ "RegisterContext/Darwin/RegisterContextDarwin_arm.cpp",
+ "RegisterContext/Darwin/RegisterContextDarwin_arm64.cpp",
+ "RegisterContext/Darwin/RegisterContextDarwin_riscv32.cpp",
+ "RegisterContext/Darwin/RegisterContextDarwin_x86_64.cpp",
+ "RegisterContext/Darwin/RegisterContextMach_arm.cpp",
+ "RegisterContext/Darwin/RegisterContextMach_x86_64.cpp",
"RegisterContext/POSIX/RegisterContextPOSIX_arm.cpp",
"RegisterContext/POSIX/RegisterContextPOSIX_arm64.cpp",
"RegisterContext/POSIX/RegisterContextPOSIX_loongarch64.cpp",
diff --git a/llvm/utils/gn/secondary/lldb/source/Plugins/Process/Utility/BUILD.gn b/llvm/utils/gn/secondary/lldb/source/Plugins/Process/Utility/BUILD.gn
index a2ffee0f15f19b..2252e0e72f0c00 100644
--- a/llvm/utils/gn/secondary/lldb/source/Plugins/Process/Utility/BUILD.gn
+++ b/llvm/utils/gn/secondary/lldb/source/Plugins/Process/Utility/BUILD.gn
@@ -32,14 +32,8 @@ static_library("Utility") {
"NativeProcessSoftwareSingleStep.cpp",
"NetBSDSignals.cpp",
"OpenBSDSignals.cpp",
- "RegisterContextDarwin_arm.cpp",
- "RegisterContextDarwin_arm64.cpp",
- "RegisterContextDarwin_riscv32.cpp",
- "RegisterContextDarwin_x86_64.cpp",
"RegisterContextDummy.cpp",
"RegisterContextHistory.cpp",
- "RegisterContextMach_arm.cpp",
- "RegisterContextMach_x86_64.cpp",
"RegisterContextMemory.cpp",
"RegisterContextThreadMemory.cpp",
"StopInfoMachException.cpp",
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