[Lldb-commits] [lldb] [lldb][RISCV] Add CSRI patch set for 'Xqci' (PR #216087)
Ayush Sahay via lldb-commits
lldb-commits at lists.llvm.org
Thu Aug 27 03:20:24 PDT 2026
https://github.com/ayushsahay1837 updated https://github.com/llvm/llvm-project/pull/216087
>From 4b11512934902f2435ec5fbaed110c410902bdd5 Mon Sep 17 00:00:00 2001
From: Ayush Sahay <asahay at qti.qualcomm.com>
Date: Thu, 13 Aug 2026 20:05:07 +0530
Subject: [PATCH 1/2] [lldb][RISCV] Add CSRI patch set for 'Xqci'
Add the CS register information patch set for 'Xqci' and its sub-
extensions.
---
.../RegisterInfoPOSIXDynamic_riscv32.cpp | 5 +-
.../Process/Utility/RegisterInfos_riscv32.h | 72 ++++++++++++
.../Utility/lldb-riscv-register-enums.h | 67 +++++++++++
lldb/source/Utility/RISCV_DWARF_Registers.h | 67 +++++++++++
.../postmortem/elf-core/TestLinuxCore.py | 108 +++++++++---------
5 files changed, 264 insertions(+), 55 deletions(-)
diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIXDynamic_riscv32.cpp b/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIXDynamic_riscv32.cpp
index 0aee4cf51bf7d..de6d10f9e9910 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIXDynamic_riscv32.cpp
+++ b/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIXDynamic_riscv32.cpp
@@ -23,7 +23,10 @@
static const llvm::StringMap<llvm::ArrayRef<lldb_private::RegisterInfo>>
g_register_infos_riscv32_csr_patches = {
- {"default", llvm::ArrayRef(g_register_infos_riscv32_csr_patch)}};
+ {"default", llvm::ArrayRef(g_register_infos_riscv32_csr_patch)},
+ {"xqci", llvm::ArrayRef(g_register_infos_riscv32_csr_xqci_patch)},
+ {"xqciint",
+ llvm::ArrayRef(g_register_infos_riscv32_csr_xqciint_patch)}};
RegisterInfoPOSIXDynamic_riscv32::RegisterInfoPOSIXDynamic_riscv32(
const lldb_private::ArchSpec &target_arch)
diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfos_riscv32.h b/lldb/source/Plugins/Process/Utility/RegisterInfos_riscv32.h
index 3cf77d6624b04..309499c0c5444 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterInfos_riscv32.h
+++ b/lldb/source/Plugins/Process/Utility/RegisterInfos_riscv32.h
@@ -681,4 +681,76 @@ static lldb_private::RegisterInfo g_register_infos_riscv32_csr_patch[] = {
DEFINE_CSR32_ALT(mconfigptr, csr_0xf15, LLDB_INVALID_REGNUM),
};
+static lldb_private::RegisterInfo g_register_infos_riscv32_csr_xqci_patch[] = {
+ DEFINE_CSR32_ALT(qc_mmcr, csr_0x7c0, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(qc_mntvec, csr_0x7c3, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(qc_mstktopaddr, csr_0x7c4, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(qc_mstkbottomaddr, csr_0x7c5, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(qc_mscratch0, csr_0x7c6, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(qc_mscratch1, csr_0x7c7, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(qc_mthreadptr, csr_0x7c8, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(qc_mwpstartaddr0, csr_0x7d0, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(qc_mwpstartaddr1, csr_0x7d1, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(qc_mwpstartaddr2, csr_0x7d2, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(qc_mwpstartaddr3, csr_0x7d3, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(qc_mwpendaddr0, csr_0x7d4, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(qc_mwpendaddr1, csr_0x7d5, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(qc_mwpendaddr2, csr_0x7d6, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(qc_mwpendaddr3, csr_0x7d7, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(qc_mclicilvl0, csr_0xbc0, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(qc_mclicilvl1, csr_0xbc1, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(qc_mclicilvl2, csr_0xbc2, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(qc_mclicilvl3, csr_0xbc3, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(qc_mclicilvl4, csr_0xbc4, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(qc_mclicilvl5, csr_0xbc5, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(qc_mclicilvl6, csr_0xbc6, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(qc_mclicilvl7, csr_0xbc7, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(qc_mclicilvl8, csr_0xbc8, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(qc_mclicilvl9, csr_0xbc9, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(qc_mclicilvl10, csr_0xbca, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(qc_mclicilvl11, csr_0xbcb, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(qc_mclicilvl12, csr_0xbcc, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(qc_mclicilvl13, csr_0xbcd, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(qc_mclicilvl14, csr_0xbce, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(qc_mclicilvl15, csr_0xbcf, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(qc_mclicilvl16, csr_0xbd0, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(qc_mclicilvl17, csr_0xbd1, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(qc_mclicilvl18, csr_0xbd2, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(qc_mclicilvl19, csr_0xbd3, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(qc_mclicilvl20, csr_0xbd4, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(qc_mclicilvl21, csr_0xbd5, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(qc_mclicilvl22, csr_0xbd6, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(qc_mclicilvl23, csr_0xbd7, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(qc_mclicilvl24, csr_0xbd8, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(qc_mclicilvl25, csr_0xbd9, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(qc_mclicilvl26, csr_0xbda, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(qc_mclicilvl27, csr_0xbdb, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(qc_mclicilvl28, csr_0xbdc, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(qc_mclicilvl29, csr_0xbdd, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(qc_mclicilvl30, csr_0xbde, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(qc_mclicilvl31, csr_0xbdf, LLDB_INVALID_REGNUM),
+};
+
+static lldb_private::RegisterInfo g_register_infos_riscv32_csr_xqciint_patch[] =
+ {
+ DEFINE_CSR32_ALT(qc_mnepc, csr_0x7c1, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(qc_mncause, csr_0x7c2, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(qc_mclicip0, csr_0x7f0, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(qc_mclicip1, csr_0x7f1, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(qc_mclicip2, csr_0x7f2, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(qc_mclicip3, csr_0x7f3, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(qc_mclicip4, csr_0x7f4, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(qc_mclicip5, csr_0x7f5, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(qc_mclicip6, csr_0x7f6, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(qc_mclicip7, csr_0x7f7, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(qc_mclicie0, csr_0x7f8, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(qc_mclicie1, csr_0x7f9, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(qc_mclicie2, csr_0x7fa, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(qc_mclicie3, csr_0x7fb, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(qc_mclicie4, csr_0x7fc, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(qc_mclicie5, csr_0x7fd, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(qc_mclicie6, csr_0x7fe, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(qc_mclicie7, csr_0x7ff, LLDB_INVALID_REGNUM),
+};
+
#endif // DECLARE_REGISTER_INFOS_RISCV32_STRUCT
diff --git a/lldb/source/Plugins/Process/Utility/lldb-riscv-register-enums.h b/lldb/source/Plugins/Process/Utility/lldb-riscv-register-enums.h
index 37d1753575110..1d3a718958330 100644
--- a/lldb/source/Plugins/Process/Utility/lldb-riscv-register-enums.h
+++ b/lldb/source/Plugins/Process/Utility/lldb-riscv-register-enums.h
@@ -4660,6 +4660,73 @@ enum {
csr_mconfigptr_riscv = csr_3861_riscv,
csr_last_riscv = csr_4095_riscv,
+ // Custom CSRs specified by 'Xqci' and its sub-extensions.
+ csr_qc_mmcr_riscv = csr_1984_riscv,
+ csr_qc_mnepc_riscv = csr_1985_riscv,
+ csr_qc_mncause_riscv = csr_1986_riscv,
+ csr_qc_mntvec_riscv = csr_1987_riscv,
+ csr_qc_mstktopaddr_riscv = csr_1988_riscv,
+ csr_qc_mstkbottomaddr_riscv = csr_1989_riscv,
+ csr_qc_mscratch0_riscv = csr_1990_riscv,
+ csr_qc_mscratch1_riscv = csr_1991_riscv,
+ csr_qc_mthreadptr_riscv = csr_1992_riscv,
+ csr_qc_mwpstartaddr0_riscv = csr_2000_riscv,
+ csr_qc_mwpstartaddr1_riscv = csr_2001_riscv,
+ csr_qc_mwpstartaddr2_riscv = csr_2002_riscv,
+ csr_qc_mwpstartaddr3_riscv = csr_2003_riscv,
+ csr_qc_mwpendaddr0_riscv = csr_2004_riscv,
+ csr_qc_mwpendaddr1_riscv = csr_2005_riscv,
+ csr_qc_mwpendaddr2_riscv = csr_2006_riscv,
+ csr_qc_mwpendaddr3_riscv = csr_2007_riscv,
+ csr_qc_mclicip0_riscv = csr_2032_riscv,
+ csr_qc_mclicip1_riscv = csr_2033_riscv,
+ csr_qc_mclicip2_riscv = csr_2034_riscv,
+ csr_qc_mclicip3_riscv = csr_2035_riscv,
+ csr_qc_mclicip4_riscv = csr_2036_riscv,
+ csr_qc_mclicip5_riscv = csr_2037_riscv,
+ csr_qc_mclicip6_riscv = csr_2038_riscv,
+ csr_qc_mclicip7_riscv = csr_2039_riscv,
+ csr_qc_mclicie0_riscv = csr_2040_riscv,
+ csr_qc_mclicie1_riscv = csr_2041_riscv,
+ csr_qc_mclicie2_riscv = csr_2042_riscv,
+ csr_qc_mclicie3_riscv = csr_2043_riscv,
+ csr_qc_mclicie4_riscv = csr_2044_riscv,
+ csr_qc_mclicie5_riscv = csr_2045_riscv,
+ csr_qc_mclicie6_riscv = csr_2046_riscv,
+ csr_qc_mclicie7_riscv = csr_2047_riscv,
+ csr_qc_mclicilvl0_riscv = csr_3008_riscv,
+ csr_qc_mclicilvl1_riscv = csr_3009_riscv,
+ csr_qc_mclicilvl2_riscv = csr_3010_riscv,
+ csr_qc_mclicilvl3_riscv = csr_3011_riscv,
+ csr_qc_mclicilvl4_riscv = csr_3012_riscv,
+ csr_qc_mclicilvl5_riscv = csr_3013_riscv,
+ csr_qc_mclicilvl6_riscv = csr_3014_riscv,
+ csr_qc_mclicilvl7_riscv = csr_3015_riscv,
+ csr_qc_mclicilvl8_riscv = csr_3016_riscv,
+ csr_qc_mclicilvl9_riscv = csr_3017_riscv,
+ csr_qc_mclicilvl10_riscv = csr_3018_riscv,
+ csr_qc_mclicilvl11_riscv = csr_3019_riscv,
+ csr_qc_mclicilvl12_riscv = csr_3020_riscv,
+ csr_qc_mclicilvl13_riscv = csr_3021_riscv,
+ csr_qc_mclicilvl14_riscv = csr_3022_riscv,
+ csr_qc_mclicilvl15_riscv = csr_3023_riscv,
+ csr_qc_mclicilvl16_riscv = csr_3024_riscv,
+ csr_qc_mclicilvl17_riscv = csr_3025_riscv,
+ csr_qc_mclicilvl18_riscv = csr_3026_riscv,
+ csr_qc_mclicilvl19_riscv = csr_3027_riscv,
+ csr_qc_mclicilvl20_riscv = csr_3028_riscv,
+ csr_qc_mclicilvl21_riscv = csr_3029_riscv,
+ csr_qc_mclicilvl22_riscv = csr_3030_riscv,
+ csr_qc_mclicilvl23_riscv = csr_3031_riscv,
+ csr_qc_mclicilvl24_riscv = csr_3032_riscv,
+ csr_qc_mclicilvl25_riscv = csr_3033_riscv,
+ csr_qc_mclicilvl26_riscv = csr_3034_riscv,
+ csr_qc_mclicilvl27_riscv = csr_3035_riscv,
+ csr_qc_mclicilvl28_riscv = csr_3036_riscv,
+ csr_qc_mclicilvl29_riscv = csr_3037_riscv,
+ csr_qc_mclicilvl30_riscv = csr_3038_riscv,
+ csr_qc_mclicilvl31_riscv = csr_3039_riscv,
+
k_num_registers_riscv
};
diff --git a/lldb/source/Utility/RISCV_DWARF_Registers.h b/lldb/source/Utility/RISCV_DWARF_Registers.h
index 0e91c431e7296..e3ec252d1bf60 100644
--- a/lldb/source/Utility/RISCV_DWARF_Registers.h
+++ b/lldb/source/Utility/RISCV_DWARF_Registers.h
@@ -4672,6 +4672,73 @@ enum {
dwarf_csr_mhartid = dwarf_csr_3860,
dwarf_csr_mconfigptr = dwarf_csr_3861,
+ // Custom CSRs specified by 'Xqci' and its sub-extensions.
+ dwarf_csr_qc_mmcr = dwarf_csr_1984,
+ dwarf_csr_qc_mnepc = dwarf_csr_1985,
+ dwarf_csr_qc_mncause = dwarf_csr_1986,
+ dwarf_csr_qc_mntvec = dwarf_csr_1987,
+ dwarf_csr_qc_mstktopaddr = dwarf_csr_1988,
+ dwarf_csr_qc_mstkbottomaddr = dwarf_csr_1989,
+ dwarf_csr_qc_mscratch0 = dwarf_csr_1990,
+ dwarf_csr_qc_mscratch1 = dwarf_csr_1991,
+ dwarf_csr_qc_mthreadptr = dwarf_csr_1992,
+ dwarf_csr_qc_mwpstartaddr0 = dwarf_csr_2000,
+ dwarf_csr_qc_mwpstartaddr1 = dwarf_csr_2001,
+ dwarf_csr_qc_mwpstartaddr2 = dwarf_csr_2002,
+ dwarf_csr_qc_mwpstartaddr3 = dwarf_csr_2003,
+ dwarf_csr_qc_mwpendaddr0 = dwarf_csr_2004,
+ dwarf_csr_qc_mwpendaddr1 = dwarf_csr_2005,
+ dwarf_csr_qc_mwpendaddr2 = dwarf_csr_2006,
+ dwarf_csr_qc_mwpendaddr3 = dwarf_csr_2007,
+ dwarf_csr_qc_mclicip0 = dwarf_csr_2032,
+ dwarf_csr_qc_mclicip1 = dwarf_csr_2033,
+ dwarf_csr_qc_mclicip2 = dwarf_csr_2034,
+ dwarf_csr_qc_mclicip3 = dwarf_csr_2035,
+ dwarf_csr_qc_mclicip4 = dwarf_csr_2036,
+ dwarf_csr_qc_mclicip5 = dwarf_csr_2037,
+ dwarf_csr_qc_mclicip6 = dwarf_csr_2038,
+ dwarf_csr_qc_mclicip7 = dwarf_csr_2039,
+ dwarf_csr_qc_mclicie0 = dwarf_csr_2040,
+ dwarf_csr_qc_mclicie1 = dwarf_csr_2041,
+ dwarf_csr_qc_mclicie2 = dwarf_csr_2042,
+ dwarf_csr_qc_mclicie3 = dwarf_csr_2043,
+ dwarf_csr_qc_mclicie4 = dwarf_csr_2044,
+ dwarf_csr_qc_mclicie5 = dwarf_csr_2045,
+ dwarf_csr_qc_mclicie6 = dwarf_csr_2046,
+ dwarf_csr_qc_mclicie7 = dwarf_csr_2047,
+ dwarf_csr_qc_mclicilvl0 = dwarf_csr_3008,
+ dwarf_csr_qc_mclicilvl1 = dwarf_csr_3009,
+ dwarf_csr_qc_mclicilvl2 = dwarf_csr_3010,
+ dwarf_csr_qc_mclicilvl3 = dwarf_csr_3011,
+ dwarf_csr_qc_mclicilvl4 = dwarf_csr_3012,
+ dwarf_csr_qc_mclicilvl5 = dwarf_csr_3013,
+ dwarf_csr_qc_mclicilvl6 = dwarf_csr_3014,
+ dwarf_csr_qc_mclicilvl7 = dwarf_csr_3015,
+ dwarf_csr_qc_mclicilvl8 = dwarf_csr_3016,
+ dwarf_csr_qc_mclicilvl9 = dwarf_csr_3017,
+ dwarf_csr_qc_mclicilvl10 = dwarf_csr_3018,
+ dwarf_csr_qc_mclicilvl11 = dwarf_csr_3019,
+ dwarf_csr_qc_mclicilvl12 = dwarf_csr_3020,
+ dwarf_csr_qc_mclicilvl13 = dwarf_csr_3021,
+ dwarf_csr_qc_mclicilvl14 = dwarf_csr_3022,
+ dwarf_csr_qc_mclicilvl15 = dwarf_csr_3023,
+ dwarf_csr_qc_mclicilvl16 = dwarf_csr_3024,
+ dwarf_csr_qc_mclicilvl17 = dwarf_csr_3025,
+ dwarf_csr_qc_mclicilvl18 = dwarf_csr_3026,
+ dwarf_csr_qc_mclicilvl19 = dwarf_csr_3027,
+ dwarf_csr_qc_mclicilvl20 = dwarf_csr_3028,
+ dwarf_csr_qc_mclicilvl21 = dwarf_csr_3029,
+ dwarf_csr_qc_mclicilvl22 = dwarf_csr_3030,
+ dwarf_csr_qc_mclicilvl23 = dwarf_csr_3031,
+ dwarf_csr_qc_mclicilvl24 = dwarf_csr_3032,
+ dwarf_csr_qc_mclicilvl25 = dwarf_csr_3033,
+ dwarf_csr_qc_mclicilvl26 = dwarf_csr_3034,
+ dwarf_csr_qc_mclicilvl27 = dwarf_csr_3035,
+ dwarf_csr_qc_mclicilvl28 = dwarf_csr_3036,
+ dwarf_csr_qc_mclicilvl29 = dwarf_csr_3037,
+ dwarf_csr_qc_mclicilvl30 = dwarf_csr_3038,
+ dwarf_csr_qc_mclicilvl31 = dwarf_csr_3039,
+
// mock pc regnum
dwarf_gpr_pc = 11451,
};
diff --git a/lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py b/lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py
index 53744327992cf..2fc2446ee1dd7 100644
--- a/lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py
+++ b/lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py
@@ -969,7 +969,7 @@ def test_riscv64_regs_gpr_only(self):
@skipIfLLVMTargetMissing("RISCV")
def test_riscv32_regs_gpr_csr(self):
# check basic registers using 32 bit RISC-V core file
- target = self.dbg.CreateTarget(None)
+ target = self.dbg.CreateTarget("riscv32-imcxqcixqccmp.gpr_csr.out")
self.assertTrue(target, VALID_TARGET)
process = target.LoadCore("riscv32-imcxqcixqccmp.gpr_csr.core")
@@ -1016,66 +1016,66 @@ def test_riscv32_regs_gpr_csr(self):
"mepc": ("0x00000000", "csr_0x341"),
"mcause": ("0x00000000", "csr_0x342"),
"mip": ("0x00000000", "csr_0x344"),
- "csr_0x7c0": ("0x00081000", "csr_0x7c0"),
+ "qc_mmcr": ("0x00081000", "csr_0x7c0"),
"mnepc": ("0x00000000", "csr_0x741"),
"mncause": ("0x00000000", "csr_0x742"),
- "csr_0x7c3": ("0x00000004", "csr_0x7c3"),
- "csr_0x7d0": ("0x00000000", "csr_0x7d0"),
- "csr_0x7d4": ("0x00000000", "csr_0x7d4"),
+ "qc_mntvec": ("0x00000004", "csr_0x7c3"),
+ "qc_mwpstartaddr0": ("0x00000000", "csr_0x7d0"),
+ "qc_mwpendaddr0": ("0x00000000", "csr_0x7d4"),
"mscratch": ("0x00000000", "csr_0x340"),
"mnscratch": ("0x00000000", "csr_0x740"),
- "csr_0x7c8": ("0x00000000", "csr_0x7c8"),
+ "qc_mthreadptr": ("0x00000000", "csr_0x7c8"),
"mcycle": ("0x00000000", "csr_0xb00"),
"mimpid": ("0x00000100", "csr_0xf13"),
"mhartid": ("0x00000000", "csr_0xf14"),
- "csr_0x7f0": ("0x00000000", "csr_0x7f0"),
- "csr_0x7f1": ("0x00000000", "csr_0x7f1"),
- "csr_0x7f2": ("0x00000000", "csr_0x7f2"),
- "csr_0x7f3": ("0x00000000", "csr_0x7f3"),
- "csr_0x7f4": ("0x00000000", "csr_0x7f4"),
- "csr_0x7f5": ("0x00000000", "csr_0x7f5"),
- "csr_0x7f6": ("0x00000000", "csr_0x7f6"),
- "csr_0x7f7": ("0x00000000", "csr_0x7f7"),
- "csr_0x7f8": ("0xfffffffe", "csr_0x7f8"),
- "csr_0x7f9": ("0x00000000", "csr_0x7f9"),
- "csr_0x7fa": ("0x00000000", "csr_0x7fa"),
- "csr_0x7fb": ("0x00000000", "csr_0x7fb"),
- "csr_0x7fc": ("0x00000000", "csr_0x7fc"),
- "csr_0x7fd": ("0x00000000", "csr_0x7fd"),
- "csr_0x7fe": ("0x00000000", "csr_0x7fe"),
- "csr_0x7ff": ("0x00000000", "csr_0x7ff"),
- "csr_0xbc0": ("0x00000000", "csr_0xbc0"),
- "csr_0xbc1": ("0x00000000", "csr_0xbc1"),
- "csr_0xbc2": ("0x00000000", "csr_0xbc2"),
- "csr_0xbc3": ("0x00000000", "csr_0xbc3"),
- "csr_0xbc4": ("0x00000000", "csr_0xbc4"),
- "csr_0xbc5": ("0x00000000", "csr_0xbc5"),
- "csr_0xbc6": ("0x00000000", "csr_0xbc6"),
- "csr_0xbc7": ("0x00000000", "csr_0xbc7"),
- "csr_0xbc8": ("0x00000000", "csr_0xbc8"),
- "csr_0xbc9": ("0x00000000", "csr_0xbc9"),
- "csr_0xbca": ("0x00000000", "csr_0xbca"),
- "csr_0xbcb": ("0x00000000", "csr_0xbcb"),
- "csr_0xbcc": ("0x00000000", "csr_0xbcc"),
- "csr_0xbcd": ("0x00000000", "csr_0xbcd"),
- "csr_0xbce": ("0x00000000", "csr_0xbce"),
- "csr_0xbcf": ("0x00000000", "csr_0xbcf"),
- "csr_0xbd0": ("0x00000000", "csr_0xbd0"),
- "csr_0xbd1": ("0x00000000", "csr_0xbd1"),
- "csr_0xbd2": ("0x00000000", "csr_0xbd2"),
- "csr_0xbd3": ("0x00000000", "csr_0xbd3"),
- "csr_0xbd4": ("0x00000000", "csr_0xbd4"),
- "csr_0xbd5": ("0x00000000", "csr_0xbd5"),
- "csr_0xbd6": ("0x00000000", "csr_0xbd6"),
- "csr_0xbd7": ("0x00000000", "csr_0xbd7"),
- "csr_0xbd8": ("0x00000000", "csr_0xbd8"),
- "csr_0xbd9": ("0x00000000", "csr_0xbd9"),
- "csr_0xbda": ("0x00000000", "csr_0xbda"),
- "csr_0xbdb": ("0x00000000", "csr_0xbdb"),
- "csr_0xbdc": ("0x00000000", "csr_0xbdc"),
- "csr_0xbdd": ("0x00000000", "csr_0xbdd"),
- "csr_0xbde": ("0x00000000", "csr_0xbde"),
- "csr_0xbdf": ("0x00000000", "csr_0xbdf"),
+ "qc_mclicip0": ("0x00000000", "csr_0x7f0"),
+ "qc_mclicip1": ("0x00000000", "csr_0x7f1"),
+ "qc_mclicip2": ("0x00000000", "csr_0x7f2"),
+ "qc_mclicip3": ("0x00000000", "csr_0x7f3"),
+ "qc_mclicip4": ("0x00000000", "csr_0x7f4"),
+ "qc_mclicip5": ("0x00000000", "csr_0x7f5"),
+ "qc_mclicip6": ("0x00000000", "csr_0x7f6"),
+ "qc_mclicip7": ("0x00000000", "csr_0x7f7"),
+ "qc_mclicie0": ("0xfffffffe", "csr_0x7f8"),
+ "qc_mclicie1": ("0x00000000", "csr_0x7f9"),
+ "qc_mclicie2": ("0x00000000", "csr_0x7fa"),
+ "qc_mclicie3": ("0x00000000", "csr_0x7fb"),
+ "qc_mclicie4": ("0x00000000", "csr_0x7fc"),
+ "qc_mclicie5": ("0x00000000", "csr_0x7fd"),
+ "qc_mclicie6": ("0x00000000", "csr_0x7fe"),
+ "qc_mclicie7": ("0x00000000", "csr_0x7ff"),
+ "qc_mclicilvl0": ("0x00000000", "csr_0xbc0"),
+ "qc_mclicilvl1": ("0x00000000", "csr_0xbc1"),
+ "qc_mclicilvl2": ("0x00000000", "csr_0xbc2"),
+ "qc_mclicilvl3": ("0x00000000", "csr_0xbc3"),
+ "qc_mclicilvl4": ("0x00000000", "csr_0xbc4"),
+ "qc_mclicilvl5": ("0x00000000", "csr_0xbc5"),
+ "qc_mclicilvl6": ("0x00000000", "csr_0xbc6"),
+ "qc_mclicilvl7": ("0x00000000", "csr_0xbc7"),
+ "qc_mclicilvl8": ("0x00000000", "csr_0xbc8"),
+ "qc_mclicilvl9": ("0x00000000", "csr_0xbc9"),
+ "qc_mclicilvl10": ("0x00000000", "csr_0xbca"),
+ "qc_mclicilvl11": ("0x00000000", "csr_0xbcb"),
+ "qc_mclicilvl12": ("0x00000000", "csr_0xbcc"),
+ "qc_mclicilvl13": ("0x00000000", "csr_0xbcd"),
+ "qc_mclicilvl14": ("0x00000000", "csr_0xbce"),
+ "qc_mclicilvl15": ("0x00000000", "csr_0xbcf"),
+ "qc_mclicilvl16": ("0x00000000", "csr_0xbd0"),
+ "qc_mclicilvl17": ("0x00000000", "csr_0xbd1"),
+ "qc_mclicilvl18": ("0x00000000", "csr_0xbd2"),
+ "qc_mclicilvl19": ("0x00000000", "csr_0xbd3"),
+ "qc_mclicilvl20": ("0x00000000", "csr_0xbd4"),
+ "qc_mclicilvl21": ("0x00000000", "csr_0xbd5"),
+ "qc_mclicilvl22": ("0x00000000", "csr_0xbd6"),
+ "qc_mclicilvl23": ("0x00000000", "csr_0xbd7"),
+ "qc_mclicilvl24": ("0x00000000", "csr_0xbd8"),
+ "qc_mclicilvl25": ("0x00000000", "csr_0xbd9"),
+ "qc_mclicilvl26": ("0x00000000", "csr_0xbda"),
+ "qc_mclicilvl27": ("0x00000000", "csr_0xbdb"),
+ "qc_mclicilvl28": ("0x00000000", "csr_0xbdc"),
+ "qc_mclicilvl29": ("0x00000000", "csr_0xbdd"),
+ "qc_mclicilvl30": ("0x00000000", "csr_0xbde"),
+ "qc_mclicilvl31": ("0x00000000", "csr_0xbdf"),
}
for regname, values in {**gpr_values, **csr_values}.items():
>From ac424e1453625dff1c503aa65047c91fc97d88c2 Mon Sep 17 00:00:00 2001
From: Ayush Sahay <asahay at qti.qualcomm.com>
Date: Thu, 27 Aug 2026 09:55:09 +0530
Subject: [PATCH 2/2] Use qc.<name> instead of qc_<name> for Xqci CSRs
---
.../Process/Utility/RegisterInfos_riscv32.h | 144 +++++++++---------
.../postmortem/elf-core/TestLinuxCore.py | 106 ++++++-------
2 files changed, 129 insertions(+), 121 deletions(-)
diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfos_riscv32.h b/lldb/source/Plugins/Process/Utility/RegisterInfos_riscv32.h
index 309499c0c5444..8ceec7fa234dc 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterInfos_riscv32.h
+++ b/lldb/source/Plugins/Process/Utility/RegisterInfos_riscv32.h
@@ -98,15 +98,23 @@ using namespace riscv_dwarf;
#define DEFINE_CSR32(reg, generic_kind) DEFINE_CSR32_ALT(reg, reg, generic_kind)
// Defines a 32-bit CSR.
-// The byte offset of 0 is a placeholder and should be corrected at runtime.
#define DEFINE_CSR32_ALT(reg, alt, generic_kind) \
- {#reg, \
+ DEFINE_CSR32_ALT_REGID(reg, alt, reg, generic_kind)
+
+// Defines a 32-bit CSR specified by Xqci or its sub-extension.
+#define DEFINE_QC_CSR32_ALT(name, alt, generic_kind) \
+ DEFINE_CSR32_ALT_REGID(qc.name, alt, qc_##name, generic_kind)
+
+// Defines a 32-bit CSR.
+// The byte offset of 0 is a placeholder and should be corrected at runtime.
+#define DEFINE_CSR32_ALT_REGID(name, alt, regid, generic_kind) \
+ {#name, \
#alt, \
4, \
0, \
lldb::eEncodingUint, \
lldb::eFormatHex, \
- CSR_KIND(csr_##reg, generic_kind), \
+ CSR_KIND(csr_##regid, generic_kind), \
nullptr, \
nullptr, \
nullptr}
@@ -682,75 +690,75 @@ static lldb_private::RegisterInfo g_register_infos_riscv32_csr_patch[] = {
};
static lldb_private::RegisterInfo g_register_infos_riscv32_csr_xqci_patch[] = {
- DEFINE_CSR32_ALT(qc_mmcr, csr_0x7c0, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(qc_mntvec, csr_0x7c3, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(qc_mstktopaddr, csr_0x7c4, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(qc_mstkbottomaddr, csr_0x7c5, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(qc_mscratch0, csr_0x7c6, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(qc_mscratch1, csr_0x7c7, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(qc_mthreadptr, csr_0x7c8, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(qc_mwpstartaddr0, csr_0x7d0, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(qc_mwpstartaddr1, csr_0x7d1, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(qc_mwpstartaddr2, csr_0x7d2, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(qc_mwpstartaddr3, csr_0x7d3, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(qc_mwpendaddr0, csr_0x7d4, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(qc_mwpendaddr1, csr_0x7d5, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(qc_mwpendaddr2, csr_0x7d6, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(qc_mwpendaddr3, csr_0x7d7, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(qc_mclicilvl0, csr_0xbc0, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(qc_mclicilvl1, csr_0xbc1, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(qc_mclicilvl2, csr_0xbc2, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(qc_mclicilvl3, csr_0xbc3, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(qc_mclicilvl4, csr_0xbc4, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(qc_mclicilvl5, csr_0xbc5, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(qc_mclicilvl6, csr_0xbc6, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(qc_mclicilvl7, csr_0xbc7, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(qc_mclicilvl8, csr_0xbc8, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(qc_mclicilvl9, csr_0xbc9, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(qc_mclicilvl10, csr_0xbca, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(qc_mclicilvl11, csr_0xbcb, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(qc_mclicilvl12, csr_0xbcc, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(qc_mclicilvl13, csr_0xbcd, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(qc_mclicilvl14, csr_0xbce, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(qc_mclicilvl15, csr_0xbcf, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(qc_mclicilvl16, csr_0xbd0, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(qc_mclicilvl17, csr_0xbd1, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(qc_mclicilvl18, csr_0xbd2, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(qc_mclicilvl19, csr_0xbd3, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(qc_mclicilvl20, csr_0xbd4, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(qc_mclicilvl21, csr_0xbd5, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(qc_mclicilvl22, csr_0xbd6, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(qc_mclicilvl23, csr_0xbd7, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(qc_mclicilvl24, csr_0xbd8, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(qc_mclicilvl25, csr_0xbd9, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(qc_mclicilvl26, csr_0xbda, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(qc_mclicilvl27, csr_0xbdb, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(qc_mclicilvl28, csr_0xbdc, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(qc_mclicilvl29, csr_0xbdd, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(qc_mclicilvl30, csr_0xbde, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(qc_mclicilvl31, csr_0xbdf, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mmcr, csr_0x7c0, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mntvec, csr_0x7c3, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mstktopaddr, csr_0x7c4, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mstkbottomaddr, csr_0x7c5, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mscratch0, csr_0x7c6, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mscratch1, csr_0x7c7, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mthreadptr, csr_0x7c8, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mwpstartaddr0, csr_0x7d0, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mwpstartaddr1, csr_0x7d1, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mwpstartaddr2, csr_0x7d2, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mwpstartaddr3, csr_0x7d3, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mwpendaddr0, csr_0x7d4, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mwpendaddr1, csr_0x7d5, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mwpendaddr2, csr_0x7d6, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mwpendaddr3, csr_0x7d7, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl0, csr_0xbc0, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl1, csr_0xbc1, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl2, csr_0xbc2, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl3, csr_0xbc3, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl4, csr_0xbc4, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl5, csr_0xbc5, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl6, csr_0xbc6, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl7, csr_0xbc7, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl8, csr_0xbc8, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl9, csr_0xbc9, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl10, csr_0xbca, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl11, csr_0xbcb, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl12, csr_0xbcc, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl13, csr_0xbcd, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl14, csr_0xbce, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl15, csr_0xbcf, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl16, csr_0xbd0, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl17, csr_0xbd1, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl18, csr_0xbd2, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl19, csr_0xbd3, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl20, csr_0xbd4, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl21, csr_0xbd5, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl22, csr_0xbd6, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl23, csr_0xbd7, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl24, csr_0xbd8, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl25, csr_0xbd9, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl26, csr_0xbda, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl27, csr_0xbdb, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl28, csr_0xbdc, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl29, csr_0xbdd, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl30, csr_0xbde, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicilvl31, csr_0xbdf, LLDB_INVALID_REGNUM),
};
static lldb_private::RegisterInfo g_register_infos_riscv32_csr_xqciint_patch[] =
{
- DEFINE_CSR32_ALT(qc_mnepc, csr_0x7c1, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(qc_mncause, csr_0x7c2, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(qc_mclicip0, csr_0x7f0, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(qc_mclicip1, csr_0x7f1, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(qc_mclicip2, csr_0x7f2, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(qc_mclicip3, csr_0x7f3, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(qc_mclicip4, csr_0x7f4, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(qc_mclicip5, csr_0x7f5, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(qc_mclicip6, csr_0x7f6, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(qc_mclicip7, csr_0x7f7, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(qc_mclicie0, csr_0x7f8, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(qc_mclicie1, csr_0x7f9, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(qc_mclicie2, csr_0x7fa, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(qc_mclicie3, csr_0x7fb, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(qc_mclicie4, csr_0x7fc, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(qc_mclicie5, csr_0x7fd, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(qc_mclicie6, csr_0x7fe, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(qc_mclicie7, csr_0x7ff, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mnepc, csr_0x7c1, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mncause, csr_0x7c2, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicip0, csr_0x7f0, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicip1, csr_0x7f1, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicip2, csr_0x7f2, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicip3, csr_0x7f3, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicip4, csr_0x7f4, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicip5, csr_0x7f5, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicip6, csr_0x7f6, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicip7, csr_0x7f7, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicie0, csr_0x7f8, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicie1, csr_0x7f9, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicie2, csr_0x7fa, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicie3, csr_0x7fb, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicie4, csr_0x7fc, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicie5, csr_0x7fd, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicie6, csr_0x7fe, LLDB_INVALID_REGNUM),
+ DEFINE_QC_CSR32_ALT(mclicie7, csr_0x7ff, LLDB_INVALID_REGNUM),
};
#endif // DECLARE_REGISTER_INFOS_RISCV32_STRUCT
diff --git a/lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py b/lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py
index 2fc2446ee1dd7..76d5115d60a72 100644
--- a/lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py
+++ b/lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py
@@ -1016,66 +1016,66 @@ def test_riscv32_regs_gpr_csr(self):
"mepc": ("0x00000000", "csr_0x341"),
"mcause": ("0x00000000", "csr_0x342"),
"mip": ("0x00000000", "csr_0x344"),
- "qc_mmcr": ("0x00081000", "csr_0x7c0"),
+ "qc.mmcr": ("0x00081000", "csr_0x7c0"),
"mnepc": ("0x00000000", "csr_0x741"),
"mncause": ("0x00000000", "csr_0x742"),
- "qc_mntvec": ("0x00000004", "csr_0x7c3"),
- "qc_mwpstartaddr0": ("0x00000000", "csr_0x7d0"),
- "qc_mwpendaddr0": ("0x00000000", "csr_0x7d4"),
+ "qc.mntvec": ("0x00000004", "csr_0x7c3"),
+ "qc.mwpstartaddr0": ("0x00000000", "csr_0x7d0"),
+ "qc.mwpendaddr0": ("0x00000000", "csr_0x7d4"),
"mscratch": ("0x00000000", "csr_0x340"),
"mnscratch": ("0x00000000", "csr_0x740"),
- "qc_mthreadptr": ("0x00000000", "csr_0x7c8"),
+ "qc.mthreadptr": ("0x00000000", "csr_0x7c8"),
"mcycle": ("0x00000000", "csr_0xb00"),
"mimpid": ("0x00000100", "csr_0xf13"),
"mhartid": ("0x00000000", "csr_0xf14"),
- "qc_mclicip0": ("0x00000000", "csr_0x7f0"),
- "qc_mclicip1": ("0x00000000", "csr_0x7f1"),
- "qc_mclicip2": ("0x00000000", "csr_0x7f2"),
- "qc_mclicip3": ("0x00000000", "csr_0x7f3"),
- "qc_mclicip4": ("0x00000000", "csr_0x7f4"),
- "qc_mclicip5": ("0x00000000", "csr_0x7f5"),
- "qc_mclicip6": ("0x00000000", "csr_0x7f6"),
- "qc_mclicip7": ("0x00000000", "csr_0x7f7"),
- "qc_mclicie0": ("0xfffffffe", "csr_0x7f8"),
- "qc_mclicie1": ("0x00000000", "csr_0x7f9"),
- "qc_mclicie2": ("0x00000000", "csr_0x7fa"),
- "qc_mclicie3": ("0x00000000", "csr_0x7fb"),
- "qc_mclicie4": ("0x00000000", "csr_0x7fc"),
- "qc_mclicie5": ("0x00000000", "csr_0x7fd"),
- "qc_mclicie6": ("0x00000000", "csr_0x7fe"),
- "qc_mclicie7": ("0x00000000", "csr_0x7ff"),
- "qc_mclicilvl0": ("0x00000000", "csr_0xbc0"),
- "qc_mclicilvl1": ("0x00000000", "csr_0xbc1"),
- "qc_mclicilvl2": ("0x00000000", "csr_0xbc2"),
- "qc_mclicilvl3": ("0x00000000", "csr_0xbc3"),
- "qc_mclicilvl4": ("0x00000000", "csr_0xbc4"),
- "qc_mclicilvl5": ("0x00000000", "csr_0xbc5"),
- "qc_mclicilvl6": ("0x00000000", "csr_0xbc6"),
- "qc_mclicilvl7": ("0x00000000", "csr_0xbc7"),
- "qc_mclicilvl8": ("0x00000000", "csr_0xbc8"),
- "qc_mclicilvl9": ("0x00000000", "csr_0xbc9"),
- "qc_mclicilvl10": ("0x00000000", "csr_0xbca"),
- "qc_mclicilvl11": ("0x00000000", "csr_0xbcb"),
- "qc_mclicilvl12": ("0x00000000", "csr_0xbcc"),
- "qc_mclicilvl13": ("0x00000000", "csr_0xbcd"),
- "qc_mclicilvl14": ("0x00000000", "csr_0xbce"),
- "qc_mclicilvl15": ("0x00000000", "csr_0xbcf"),
- "qc_mclicilvl16": ("0x00000000", "csr_0xbd0"),
- "qc_mclicilvl17": ("0x00000000", "csr_0xbd1"),
- "qc_mclicilvl18": ("0x00000000", "csr_0xbd2"),
- "qc_mclicilvl19": ("0x00000000", "csr_0xbd3"),
- "qc_mclicilvl20": ("0x00000000", "csr_0xbd4"),
- "qc_mclicilvl21": ("0x00000000", "csr_0xbd5"),
- "qc_mclicilvl22": ("0x00000000", "csr_0xbd6"),
- "qc_mclicilvl23": ("0x00000000", "csr_0xbd7"),
- "qc_mclicilvl24": ("0x00000000", "csr_0xbd8"),
- "qc_mclicilvl25": ("0x00000000", "csr_0xbd9"),
- "qc_mclicilvl26": ("0x00000000", "csr_0xbda"),
- "qc_mclicilvl27": ("0x00000000", "csr_0xbdb"),
- "qc_mclicilvl28": ("0x00000000", "csr_0xbdc"),
- "qc_mclicilvl29": ("0x00000000", "csr_0xbdd"),
- "qc_mclicilvl30": ("0x00000000", "csr_0xbde"),
- "qc_mclicilvl31": ("0x00000000", "csr_0xbdf"),
+ "qc.mclicip0": ("0x00000000", "csr_0x7f0"),
+ "qc.mclicip1": ("0x00000000", "csr_0x7f1"),
+ "qc.mclicip2": ("0x00000000", "csr_0x7f2"),
+ "qc.mclicip3": ("0x00000000", "csr_0x7f3"),
+ "qc.mclicip4": ("0x00000000", "csr_0x7f4"),
+ "qc.mclicip5": ("0x00000000", "csr_0x7f5"),
+ "qc.mclicip6": ("0x00000000", "csr_0x7f6"),
+ "qc.mclicip7": ("0x00000000", "csr_0x7f7"),
+ "qc.mclicie0": ("0xfffffffe", "csr_0x7f8"),
+ "qc.mclicie1": ("0x00000000", "csr_0x7f9"),
+ "qc.mclicie2": ("0x00000000", "csr_0x7fa"),
+ "qc.mclicie3": ("0x00000000", "csr_0x7fb"),
+ "qc.mclicie4": ("0x00000000", "csr_0x7fc"),
+ "qc.mclicie5": ("0x00000000", "csr_0x7fd"),
+ "qc.mclicie6": ("0x00000000", "csr_0x7fe"),
+ "qc.mclicie7": ("0x00000000", "csr_0x7ff"),
+ "qc.mclicilvl0": ("0x00000000", "csr_0xbc0"),
+ "qc.mclicilvl1": ("0x00000000", "csr_0xbc1"),
+ "qc.mclicilvl2": ("0x00000000", "csr_0xbc2"),
+ "qc.mclicilvl3": ("0x00000000", "csr_0xbc3"),
+ "qc.mclicilvl4": ("0x00000000", "csr_0xbc4"),
+ "qc.mclicilvl5": ("0x00000000", "csr_0xbc5"),
+ "qc.mclicilvl6": ("0x00000000", "csr_0xbc6"),
+ "qc.mclicilvl7": ("0x00000000", "csr_0xbc7"),
+ "qc.mclicilvl8": ("0x00000000", "csr_0xbc8"),
+ "qc.mclicilvl9": ("0x00000000", "csr_0xbc9"),
+ "qc.mclicilvl10": ("0x00000000", "csr_0xbca"),
+ "qc.mclicilvl11": ("0x00000000", "csr_0xbcb"),
+ "qc.mclicilvl12": ("0x00000000", "csr_0xbcc"),
+ "qc.mclicilvl13": ("0x00000000", "csr_0xbcd"),
+ "qc.mclicilvl14": ("0x00000000", "csr_0xbce"),
+ "qc.mclicilvl15": ("0x00000000", "csr_0xbcf"),
+ "qc.mclicilvl16": ("0x00000000", "csr_0xbd0"),
+ "qc.mclicilvl17": ("0x00000000", "csr_0xbd1"),
+ "qc.mclicilvl18": ("0x00000000", "csr_0xbd2"),
+ "qc.mclicilvl19": ("0x00000000", "csr_0xbd3"),
+ "qc.mclicilvl20": ("0x00000000", "csr_0xbd4"),
+ "qc.mclicilvl21": ("0x00000000", "csr_0xbd5"),
+ "qc.mclicilvl22": ("0x00000000", "csr_0xbd6"),
+ "qc.mclicilvl23": ("0x00000000", "csr_0xbd7"),
+ "qc.mclicilvl24": ("0x00000000", "csr_0xbd8"),
+ "qc.mclicilvl25": ("0x00000000", "csr_0xbd9"),
+ "qc.mclicilvl26": ("0x00000000", "csr_0xbda"),
+ "qc.mclicilvl27": ("0x00000000", "csr_0xbdb"),
+ "qc.mclicilvl28": ("0x00000000", "csr_0xbdc"),
+ "qc.mclicilvl29": ("0x00000000", "csr_0xbdd"),
+ "qc.mclicilvl30": ("0x00000000", "csr_0xbde"),
+ "qc.mclicilvl31": ("0x00000000", "csr_0xbdf"),
}
for regname, values in {**gpr_values, **csr_values}.items():
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