[Lldb-commits] [lldb] [lldb][RISCV] Add float registers stubs (PR #214034)

[via lldb-commits]

https://github.com/Qwinci updated https://github.com/llvm/llvm-project/pull/214034

>From d920db6e044e6984147fe44aeb13f0dec85dddfb Mon Sep 17 00:00:00 2001
From: Qwinci <qwinci222 at gmail.com>
Date: Tue, 4 Aug 2026 20:43:16 +0300
Subject: [PATCH] [lldb][RISCV] Add float register ABI stubs

This allows retrieving the float registers for variables in other frames
from e.g. QEMU gdbstub via DWARF rules.
---
 .../Plugins/ABI/RISCV/ABISysV_riscv.cpp       | 70 ++++++++++++++++++-
 1 file changed, 67 insertions(+), 3 deletions(-)

diff --git a/lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.cpp b/lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.cpp
index 19bbef9c4119e..7443adf764816 100644
--- a/lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.cpp
+++ b/lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.cpp
@@ -83,10 +83,42 @@ enum regnums {
   t4,
   t5,
   t6,
-  pc
+  pc = riscv_dwarf::dwarf_gpr_pc,
+  ft0 = riscv_dwarf::dwarf_fpr_f0,
+  ft1,
+  ft2,
+  ft3,
+  ft4,
+  ft5,
+  ft6,
+  ft7,
+  fs0,
+  fs1,
+  fa0,
+  fa1,
+  fa2,
+  fa3,
+  fa4,
+  fa5,
+  fa6,
+  fa7,
+  fs2,
+  fs3,
+  fs4,
+  fs5,
+  fs6,
+  fs7,
+  fs8,
+  fs9,
+  fs10,
+  fs11,
+  ft8,
+  ft9,
+  ft10,
+  ft11
 };
 
-static const std::array<RegisterInfo, 33> g_register_infos = {
+static const std::array<RegisterInfo, 65> g_register_infos = {
     {DEFINE_REGISTER_STUB(zero, nullptr),
      DEFINE_GENERIC_REGISTER_STUB(ra, nullptr, LLDB_REGNUM_GENERIC_RA),
      DEFINE_GENERIC_REGISTER_STUB(sp, nullptr, LLDB_REGNUM_GENERIC_SP),
@@ -119,7 +151,39 @@ static const std::array<RegisterInfo, 33> g_register_infos = {
      DEFINE_REGISTER_STUB(t4, nullptr),
      DEFINE_REGISTER_STUB(t5, nullptr),
      DEFINE_REGISTER_STUB(t6, nullptr),
-     DEFINE_GENERIC_REGISTER_STUB(pc, nullptr, LLDB_REGNUM_GENERIC_PC)}};
+     DEFINE_GENERIC_REGISTER_STUB(pc, nullptr, LLDB_REGNUM_GENERIC_PC),
+     DEFINE_REGISTER_STUB(ft0, nullptr),
+     DEFINE_REGISTER_STUB(ft1, nullptr),
+     DEFINE_REGISTER_STUB(ft2, nullptr),
+     DEFINE_REGISTER_STUB(ft3, nullptr),
+     DEFINE_REGISTER_STUB(ft4, nullptr),
+     DEFINE_REGISTER_STUB(ft5, nullptr),
+     DEFINE_REGISTER_STUB(ft6, nullptr),
+     DEFINE_REGISTER_STUB(ft7, nullptr),
+     DEFINE_REGISTER_STUB(fs0, nullptr),
+     DEFINE_REGISTER_STUB(fs1, nullptr),
+     DEFINE_REGISTER_STUB(fa0, nullptr),
+     DEFINE_REGISTER_STUB(fa1, nullptr),
+     DEFINE_REGISTER_STUB(fa2, nullptr),
+     DEFINE_REGISTER_STUB(fa3, nullptr),
+     DEFINE_REGISTER_STUB(fa4, nullptr),
+     DEFINE_REGISTER_STUB(fa5, nullptr),
+     DEFINE_REGISTER_STUB(fa6, nullptr),
+     DEFINE_REGISTER_STUB(fa7, nullptr),
+     DEFINE_REGISTER_STUB(fs2, nullptr),
+     DEFINE_REGISTER_STUB(fs3, nullptr),
+     DEFINE_REGISTER_STUB(fs4, nullptr),
+     DEFINE_REGISTER_STUB(fs5, nullptr),
+     DEFINE_REGISTER_STUB(fs6, nullptr),
+     DEFINE_REGISTER_STUB(fs7, nullptr),
+     DEFINE_REGISTER_STUB(fs8, nullptr),
+     DEFINE_REGISTER_STUB(fs9, nullptr),
+     DEFINE_REGISTER_STUB(fs10, nullptr),
+     DEFINE_REGISTER_STUB(fs11, nullptr),
+     DEFINE_REGISTER_STUB(ft8, nullptr),
+     DEFINE_REGISTER_STUB(ft9, nullptr),
+     DEFINE_REGISTER_STUB(ft10, nullptr),
+     DEFINE_REGISTER_STUB(ft11, nullptr)}};
 } // namespace dwarf
 } // namespace