[Lldb-commits] [lldb] [lldb][RISCV] Construct CSR information dynamically (PR #203234)
via lldb-commits
lldb-commits at lists.llvm.org
Thu Jun 11 03:15:48 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: Ayush Sahay (ayushsahay1837)
<details>
<summary>Changes</summary>
Custom RISC-V extensions may define control and status registers (CSRs) with overlapping addresses. Therefore, when performing postmortem debug of 32-bit RISC-V core dump images, dynamically construct CSR information based on the set of enabled extensions.
Assisted-by: OpenAI GPT-5
---
Patch is 275.00 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/203234.diff
6 Files Affected:
- (modified) lldb/source/Plugins/Process/Utility/RegisterInfoPOSIXDynamic_riscv32.cpp (+80)
- (modified) lldb/source/Plugins/Process/Utility/RegisterInfoPOSIXDynamic_riscv32.h (+31)
- (modified) lldb/source/Plugins/Process/Utility/RegisterInfos_riscv32.h (+383-4107)
- (modified) lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv32.cpp (+54-6)
- (modified) lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv32.h (+13)
- (modified) lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py (+66-66)
``````````diff
diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIXDynamic_riscv32.cpp b/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIXDynamic_riscv32.cpp
index 5f0f965e4ca08..a05efa49622cc 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIXDynamic_riscv32.cpp
+++ b/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIXDynamic_riscv32.cpp
@@ -8,11 +8,18 @@
#include "RegisterInfoPOSIXDynamic_riscv32.h"
+#include "lldb-riscv-register-enums.h"
#include "lldb/lldb-defines.h"
#include "llvm/Support/Compiler.h"
+#include <iomanip>
+#include <sstream>
#include <stddef.h>
+#define DECLARE_REGISTER_INFOS_RISCV32_STRUCT
+#include "Plugins/Process/Utility/RegisterInfos_riscv32.h"
+#undef DECLARE_REGISTER_INFOS_RISCV32_STRUCT
+
RegisterInfoPOSIXDynamic_riscv32::RegisterInfoPOSIXDynamic_riscv32(
const lldb_private::ArchSpec &target_arch)
: lldb_private::RegisterInfoAndSetInterface(target_arch),
@@ -84,3 +91,76 @@ RegisterInfoPOSIXDynamic_riscv32::GetRegisterInfo(
llvm::StringRef reg_name) const {
return m_dyn_reg_infos.GetRegisterInfo(reg_name);
}
+
+std::vector<lldb_private::RegisterInfo>
+RegisterInfoPOSIXDynamic_riscv32::GetCSRegisterInfos(
+ const std::vector<std::string> &features) {
+ // Sort and deduplicate the feature list to make the resulting CSR metadata
+ // independent of caller ordering.
+ llvm::SmallVector<llvm::StringRef, 32> normalized_features;
+ normalized_features.reserve(features.size());
+ for (const std::string &feature : features)
+ normalized_features.push_back(feature);
+ std::sort(normalized_features.begin(), normalized_features.end());
+ normalized_features.erase(
+ std::unique(normalized_features.begin(), normalized_features.end()),
+ normalized_features.end());
+
+ const uint32_t k_num_csr_registers = csr_last_riscv - csr_first_riscv + 1;
+ std::vector<lldb_private::RegisterInfo> cs_reg_infos;
+ cs_reg_infos.reserve(k_num_csr_registers);
+
+ // Construct default CS register information.
+ for (uint32_t reg = 0; reg < k_num_csr_registers; ++reg) {
+ lldb_private::RegisterInfo csr{};
+ for (auto &kind : csr.kinds)
+ kind = LLDB_INVALID_REGNUM;
+
+ std::stringstream reg_hex;
+ reg_hex << "0x" << std::hex << reg;
+ lldb_private::ConstString name(std::string("csr_") + reg_hex.str());
+
+ csr.name = name.GetCString();
+ csr.alt_name = csr.name;
+ csr.byte_size = 4;
+ csr.byte_offset = 0;
+ csr.encoding = lldb::eEncodingUint;
+ csr.format = lldb::eFormatHex;
+ csr.kinds[lldb::eRegisterKindEHFrame] = riscv_dwarf::dwarf_first_csr + reg;
+ csr.kinds[lldb::eRegisterKindDWARF] = riscv_dwarf::dwarf_first_csr + reg;
+ csr.kinds[lldb::eRegisterKindGeneric] = LLDB_INVALID_REGNUM;
+ csr.kinds[lldb::eRegisterKindProcessPlugin] = LLDB_INVALID_REGNUM;
+ csr.kinds[lldb::eRegisterKindLLDB] = csr_first_riscv + reg;
+ csr.value_regs = nullptr;
+ csr.invalidate_regs = nullptr;
+ csr.flags_type = nullptr;
+
+ cs_reg_infos.push_back(csr);
+ }
+
+ // Patch application is order-dependent; later patches override earlier ones
+ // for the same CSR address.
+ ConfigureCSRegInfos(cs_reg_infos, "default");
+
+ for (const auto &feature : normalized_features)
+ ConfigureCSRegInfos(cs_reg_infos, feature);
+
+ return cs_reg_infos;
+}
+
+void RegisterInfoPOSIXDynamic_riscv32::ConfigureCSRegInfos(
+ std::vector<lldb_private::RegisterInfo> &cs_reg_infos,
+ llvm::StringRef feature) {
+ auto it = g_register_infos_riscv32_csr_patches.find(feature);
+ if (it == g_register_infos_riscv32_csr_patches.end())
+ return;
+
+ for (const auto &csr : it->second) {
+ const uint32_t lldb_reg = csr.kinds[lldb::eRegisterKindLLDB];
+ if (lldb_reg < csr_first_riscv || lldb_reg > csr_last_riscv)
+ continue;
+ uint32_t idx = lldb_reg - csr_first_riscv;
+ if (idx < cs_reg_infos.size())
+ cs_reg_infos[idx] = csr;
+ }
+}
diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIXDynamic_riscv32.h b/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIXDynamic_riscv32.h
index bfd6a83b4b10d..87c7b8109cdea 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIXDynamic_riscv32.h
+++ b/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIXDynamic_riscv32.h
@@ -40,9 +40,40 @@ class RegisterInfoPOSIXDynamic_riscv32
const lldb_private::RegisterInfo *
GetRegisterInfo(llvm::StringRef reg_name) const;
+ /// @brief Builds CS register information entries for 32-bit RISC-V debug
+ /// targets on the basis of the enabled ISA extensions.
+ ///
+ /// Custom and vendor RISC-V extensions can define CSRs that overlap
+ /// in address space. This routine constructs a baseline CSR container and
+ /// applies extension patches in a deterministic order so that the final CSR
+ /// metadata depends only on the feature set and conflict resolution is
+ /// predictable.
+ ///
+ /// @param[in] features ISA extension feature names.
+ ///
+ /// @return Vector of CS register information entries for the 32-bit RISC-V
+ /// debug target configuration.
+ std::vector<lldb_private::RegisterInfo>
+ GetCSRegisterInfos(const std::vector<std::string> &features);
+
private:
lldb_private::DynamicRegisterInfo m_dyn_reg_infos;
const lldb_private::ArchSpec m_target_arch;
+
+ /// @brief Applies the CS register information patch set for a given feature.
+ ///
+ /// CSR metadata is constructed from a baseline container and then selectively
+ /// overridden by feature-specific definitions. This helper performs the
+ /// override by looking up the patch list for the feature and updating only
+ /// the affected CSR entries in-place.
+ ///
+ /// @param[in,out] cs_reg_infos CS register information vector to update
+ /// in-place.
+ /// @param[in] feature Feature name used to select a patch set
+ /// (e.g., "default").
+ void
+ ConfigureCSRegInfos(std::vector<lldb_private::RegisterInfo> &cs_reg_infos,
+ llvm::StringRef feature);
};
#endif // LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOPOSIXDYNAMIC_RISCV32_H
diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfos_riscv32.h b/lldb/source/Plugins/Process/Utility/RegisterInfos_riscv32.h
index c0c9f1390bb32..eda92ec95bbcb 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterInfos_riscv32.h
+++ b/lldb/source/Plugins/Process/Utility/RegisterInfos_riscv32.h
@@ -16,14 +16,6 @@
#include <stddef.h>
-#ifndef GPR_OFFSET
-#error GPR_OFFSET must be defined before including this header file
-#endif
-
-#ifndef FPR_OFFSET
-#error FPR_OFFSET must be defined before including this header file
-#endif
-
using namespace riscv_dwarf;
// Assuming register numbers seen in eh_frame and DWARF to be the same.
@@ -47,11 +39,12 @@ using namespace riscv_dwarf;
#define DEFINE_GPR32(reg, generic_kind) DEFINE_GPR32_ALT(reg, reg, generic_kind)
// Defines a 32-bit GPR.
+// The byte offset of 0 is a placeholder and should be corrected at runtime.
#define DEFINE_GPR32_ALT(reg, alt, generic_kind) \
{#reg, \
#alt, \
4, \
- GPR_OFFSET(gpr_##reg##_riscv - gpr_first_riscv), \
+ 0, \
lldb::eEncodingUint, \
lldb::eFormatHex, \
GPR32_KIND(gpr_##reg, generic_kind), \
@@ -64,11 +57,12 @@ using namespace riscv_dwarf;
DEFINE_FPR_ALT(reg, alt, 8, generic_kind)
// Defines a 32-bit FPR.
+// The byte offset of 0 is a placeholder and should be corrected at runtime.
#define DEFINE_FPR_ALT(reg, alt, size, generic_kind) \
{#reg, \
#alt, \
size, \
- FPR_OFFSET(fpr_##reg##_riscv - fpr_first_riscv), \
+ 0, \
lldb::eEncodingIEEE754, \
lldb::eFormatHex, \
FPR32_KIND(fpr_##reg, generic_kind), \
@@ -98,6 +92,7 @@ using namespace riscv_dwarf;
#define DEFINE_CSR32(reg, generic_kind) DEFINE_CSR32_ALT(reg, reg, generic_kind)
// Defines a 32-bit CSR.
+// The byte offset of 0 is a placeholder and should be corrected at runtime.
#define DEFINE_CSR32_ALT(reg, alt, generic_kind) \
{#reg, \
#alt, \
@@ -304,4103 +299,384 @@ static lldb_private::RegisterInfo g_register_infos_riscv32_vpr[] = {
DEFINE_VPR(v30, LLDB_INVALID_REGNUM), DEFINE_VPR(v31, LLDB_INVALID_REGNUM),
};
-static lldb_private::RegisterInfo g_register_infos_riscv32_csr[] = {
- DEFINE_CSR32_ALT(0, 0x000, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(fflags, 0x001, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(frm, 0x002, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(fcsr, 0x003, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(4, 0x004, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(5, 0x005, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(6, 0x006, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(7, 0x007, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(vstart, 0x008, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(vxsat, 0x009, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(vxrm, 0x00a, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(11, 0x00b, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(12, 0x00c, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(13, 0x00d, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(14, 0x00e, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(vcsr, 0x00f, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(16, 0x010, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(17, 0x011, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(18, 0x012, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(19, 0x013, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(20, 0x014, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(21, 0x015, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(22, 0x016, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(23, 0x017, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(24, 0x018, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(25, 0x019, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(26, 0x01a, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(27, 0x01b, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(28, 0x01c, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(29, 0x01d, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(30, 0x01e, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(31, 0x01f, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(32, 0x020, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(33, 0x021, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(34, 0x022, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(35, 0x023, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(36, 0x024, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(37, 0x025, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(38, 0x026, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(39, 0x027, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(40, 0x028, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(41, 0x029, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(42, 0x02a, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(43, 0x02b, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(44, 0x02c, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(45, 0x02d, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(46, 0x02e, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(47, 0x02f, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(48, 0x030, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(49, 0x031, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(50, 0x032, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(51, 0x033, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(52, 0x034, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(53, 0x035, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(54, 0x036, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(55, 0x037, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(56, 0x038, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(57, 0x039, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(58, 0x03a, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(59, 0x03b, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(60, 0x03c, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(61, 0x03d, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(62, 0x03e, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(63, 0x03f, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(64, 0x040, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(65, 0x041, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(66, 0x042, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(67, 0x043, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(68, 0x044, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(69, 0x045, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(70, 0x046, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(71, 0x047, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(72, 0x048, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(73, 0x049, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(74, 0x04a, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(75, 0x04b, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(76, 0x04c, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(77, 0x04d, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(78, 0x04e, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(79, 0x04f, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(80, 0x050, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(81, 0x051, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(82, 0x052, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(83, 0x053, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(84, 0x054, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(85, 0x055, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(86, 0x056, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(87, 0x057, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(88, 0x058, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(89, 0x059, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(90, 0x05a, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(91, 0x05b, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(92, 0x05c, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(93, 0x05d, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(94, 0x05e, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(95, 0x05f, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(96, 0x060, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(97, 0x061, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(98, 0x062, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(99, 0x063, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(100, 0x064, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(101, 0x065, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(102, 0x066, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(103, 0x067, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(104, 0x068, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(105, 0x069, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(106, 0x06a, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(107, 0x06b, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(108, 0x06c, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(109, 0x06d, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(110, 0x06e, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(111, 0x06f, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(112, 0x070, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(113, 0x071, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(114, 0x072, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(115, 0x073, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(116, 0x074, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(117, 0x075, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(118, 0x076, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(119, 0x077, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(120, 0x078, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(121, 0x079, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(122, 0x07a, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(123, 0x07b, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(124, 0x07c, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(125, 0x07d, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(126, 0x07e, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(127, 0x07f, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(128, 0x080, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(129, 0x081, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(130, 0x082, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(131, 0x083, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(132, 0x084, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(133, 0x085, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(134, 0x086, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(135, 0x087, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(136, 0x088, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(137, 0x089, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(138, 0x08a, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(139, 0x08b, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(140, 0x08c, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(141, 0x08d, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(142, 0x08e, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(143, 0x08f, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(144, 0x090, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(145, 0x091, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(146, 0x092, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(147, 0x093, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(148, 0x094, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(149, 0x095, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(150, 0x096, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(151, 0x097, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(152, 0x098, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(153, 0x099, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(154, 0x09a, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(155, 0x09b, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(156, 0x09c, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(157, 0x09d, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(158, 0x09e, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(159, 0x09f, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(160, 0x0a0, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(161, 0x0a1, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(162, 0x0a2, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(163, 0x0a3, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(164, 0x0a4, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(165, 0x0a5, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(166, 0x0a6, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(167, 0x0a7, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(168, 0x0a8, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(169, 0x0a9, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(170, 0x0aa, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(171, 0x0ab, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(172, 0x0ac, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(173, 0x0ad, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(174, 0x0ae, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(175, 0x0af, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(176, 0x0b0, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(177, 0x0b1, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(178, 0x0b2, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(179, 0x0b3, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(180, 0x0b4, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(181, 0x0b5, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(182, 0x0b6, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(183, 0x0b7, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(184, 0x0b8, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(185, 0x0b9, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(186, 0x0ba, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(187, 0x0bb, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(188, 0x0bc, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(189, 0x0bd, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(190, 0x0be, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(191, 0x0bf, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(192, 0x0c0, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(193, 0x0c1, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(194, 0x0c2, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(195, 0x0c3, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(196, 0x0c4, LLDB_INVALID_REGNUM),
- DEFINE_CSR32_ALT(197, 0x0c5, LLDB_INVALID_REGNUM),
- DE...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/203234
More information about the lldb-commits
mailing list