[Lldb-commits] [lldb] [llvm] [AArch64][llvm] Tighten SYSP parsing; don't disassemble invalid encodings (PR #182410)

[via lldb-commits]

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@@ -11593,37 +11593,12 @@ let Predicates = [HasRCPC3, HasNEON] in {
 //===----------------------------------------------------------------------===//
 // 128-bit System Instructions (FEAT_SYSINSTR128)
 //===----------------------------------------------------------------------===//
-def SYSPxt  : SystemPXtI<0, "sysp">;
-
-def SYSPxt_XZR
-  : BaseSystemI<0, (outs),
-      (ins imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2, SyspXzrPairOperand:$xzr_pair),
-      "sysp", "\t$op1, $Cn, $Cm, $op2, $xzr_pair">,
-    Sched<[WriteSys]>
-{
-  // Had to use a custom decoder because tablegen interprets this as having 4 fields (why?)
-  // and therefore autogenerates a decoder that builds an MC representation that has 4 fields
-  // (decodeToMCInst), but when printing we expect the MC representation to have 5 fields (one
-  // extra for the XZR) because AArch64InstPrinter::printInstruction in AArch64GenAsmWriter.inc
-  // is based off of the asm template (maybe) and therefore wants to print 5 operands.
-  // I could add a bits<5> xzr_pair. But without a way to constrain it to 0b11111 here it would
-  // overlap with the main SYSP instruction.
-  let DecoderMethod = "DecodeSyspXzrInstruction";
-  bits<3> op1;
-  bits<4> Cn;
-  bits<4> Cm;
-  bits<3> op2;
-  let Inst{22}    = 0b1; // override BaseSystemI
-  let Inst{20-19} = 0b01;
-  let Inst{18-16} = op1;
-  let Inst{15-12} = Cn;
-  let Inst{11-8}  = Cm;
-  let Inst{7-5}   = op2;
-  let Inst{4-0}   = 0b11111;
+def SYSPxt  : SystemPXtI<0, "sysp"> {
+  let DecoderMethod = "DecodeSyspInstruction";
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Lukacma wrote:

This should probably be moved to BaseSYSPEncoding

https://github.com/llvm/llvm-project/pull/182410