[Lldb-commits] [lldb] [llvm] [AArch64][llvm] Tighten SYSP parsing; don't disassemble invalid encodings (PR #182410)

[Jonathan Thackray via lldb-commits]

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@@ -8701,52 +8700,56 @@ ParseStatus AArch64AsmParser::tryParseGPRSeqPair(OperandVector &Operands) {
   MCRegister FirstReg;
   ParseStatus Res = tryParseScalarRegister(FirstReg);
   if (!Res.isSuccess())
-    return Error(S, "expected first even register of a consecutive same-size "
-                    "even/odd register pair");
+    return Error(S, FirstRegExpected);
 
   const MCRegisterClass &WRegClass =
       AArch64MCRegisterClasses[AArch64::GPR32RegClassID];
   const MCRegisterClass &XRegClass =
       AArch64MCRegisterClasses[AArch64::GPR64RegClassID];
 
-  bool isXReg = XRegClass.contains(FirstReg),
-       isWReg = WRegClass.contains(FirstReg);
-  if (!isXReg && !isWReg)
-    return Error(S, "expected first even register of a consecutive same-size "
-                    "even/odd register pair");
+  bool IsXZRPair = AllowXZRPair && FirstReg == AArch64::XZR;
+  bool IsXReg = XRegClass.contains(FirstReg);
+  bool IsWReg = WPairClass && WRegClass.contains(FirstReg);
+  if (!IsXZRPair && !IsXReg && !IsWReg)
+    return Error(S, FirstRegExpected);
 
   const MCRegisterInfo *RI = getContext().getRegisterInfo();
   unsigned FirstEncoding = RI->getEncodingValue(FirstReg);
 
-  if (FirstEncoding & 0x1)
-    return Error(S, "expected first even register of a consecutive same-size "
-                    "even/odd register pair");
+  if (!IsXZRPair && (FirstEncoding & 0x1))
+    return Error(S, FirstRegExpected);
 
   if (getTok().isNot(AsmToken::Comma))
     return Error(getLoc(), "expected comma");
-  // Eat the comma
   Lex();
 
   SMLoc E = getLoc();
   MCRegister SecondReg;
   Res = tryParseScalarRegister(SecondReg);
   if (!Res.isSuccess())
-    return Error(E, "expected second odd register of a consecutive same-size "
-                    "even/odd register pair");
+    return Error(E, IsXZRPair ? "expected second xzr in xzr/xzr register pair"
+                              : SecondRegExpected);
+
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jthackray wrote:

Sure, done.

https://github.com/llvm/llvm-project/pull/182410