[Lldb-commits] [lldb] [llvm] [AArch64][llvm] Tighten SYSP parsing; don't disassemble invalid encodings (PR #182410)

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@@ -13,150 +13,154 @@
 // registers with 128-bit formats (op0, op1, Cn, Cm, op2)
 // For sysp, op0 is 0
 
-sysp #0, c2, c0, #0, x0, x1// TTBR0_EL1     3  0  2  0  0
-// CHECK-INST: sysp #0, c2, c0, #0, x0, x1
-// CHECK-ENCODING: encoding: [0x00,0x20,0x48,0xd5]
+sysp #0, c8, c0, #0, x0, x1
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CarolineConcatto wrote:

Can you add a test in armv9a-tlbip.s using sysp and see if that is assemble to a tlbip instruction.
Something like:

```
 sysp #0, c8, c7, #1, x8, x9
 // CHECK-INST: tlbip vae1, x8, x9
// CHECK-ENCODING: encoding: [0xa8,0x97,0x48,0xd5]
// CHECK-ERROR: error: instruction requires: d128
// CHECK-TLBID: error: instruction requires: d128
// CHECK-UNKNOWN: d54897a8 sysp #0, c9, c7, #5, x8, x9
```

https://github.com/llvm/llvm-project/pull/182410