[Lldb-commits] [lldb] [lldb] New expedited register specfication for unavailable regs (PR #193894)

[David Spickett via lldb-commits]

DavidSpickett wrote:

> maybe one of the s or d subsets of a neon register would show the issue on aarch64

Writing to a subset of a Neon register sets the rest of the register to 0s - https://developer.arm.com/documentation/dui0801/e/Advanced-SIMD-Programming/Advanced-SIMD-scalars?lang=en

> In A64 Advanced SIMD scalar instructions, you refer to registers using a name that indicates the number of significant bits. The names are Bn, Hn, Sn, or Dn, where n is the register number (0-31). The unused high bits are ignored on a read and set to zero on a write.

So filling with 0s would work. Same for SVE, SIMD overlaps SVE registers.

Still could be considered a bug generally.

https://github.com/llvm/llvm-project/pull/193894