[Lldb-commits] [lldb] [lldb] Override default struct layout when building register types (PR #189590)

[David Spickett via lldb-commits]

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@@ -28,31 +28,18 @@ static void dump_type_value(lldb_private::CompilerType &fields_type, T value,
                             lldb_private::Stream &strm) {
   lldb::ByteOrder target_order = exe_scope->CalculateProcess()->GetByteOrder();
 
-  // For the bitfield types we generate, it is expected that the fields are
-  // in what is usually a big endian order. Most significant field first.
-  // This is also clang's internal ordering and the order we want to print
-  // them. On a big endian host this all matches up, for a little endian
-  // host we have to swap the order of the fields before display.
-  if (target_order == lldb::ByteOrder::eByteOrderLittle) {
-    value = reg_info.flags_type->ReverseFieldOrder(value);
-  }
-
-  // Then we need to match the target's endian on a byte level as well.
+  // The type will be rendered in the target's type system, so it must match
+  // its endian.
   if (lldb_private::endian::InlHostByteOrder() != target_order)
     value = llvm::byteswap(value);
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DavidSpickett wrote:

Yes that's a good find but the class `RegisterValue` can in theory hold other endian. So later while I implement handling for any register size, I'll do it this way:
```
  auto heap_buf_sp =
      std::make_shared<lldb_private::DataBufferHeap>(reg_val.GetByteSize(), 0);
  lldb::ByteOrder target_order = exe_scope->CalculateProcess()->GetByteOrder();
  lldb_private::Status err;
  uint32_t wrote =
      reg_val.GetAsMemoryData(reg_info, heap_buf_sp->GetBytes(),
                              reg_val.GetByteSize(), target_order, err);
  if (wrote != reg_val.GetByteSize() || err.Fail())
    return;

  lldb_private::DataExtractor data_extractor(heap_buf_sp);
  data_extractor.SetByteOrder(target_order);
```
Which is basically the same except that it asks the register value what order it has instead of us hard coding host order.

Kept that out of this PR as we don't need the larger register support yet.

https://github.com/llvm/llvm-project/pull/189590