[Lldb-commits] [lldb] [lldb][RISCV] Handle subsets of CSRs in RV32 core dump images (PR #142932)
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``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp,h -- lldb/source/Plugins/Process/Utility/RegisterInfoPOSIXDynamic_riscv32.cpp lldb/source/Plugins/Process/Utility/RegisterInfoPOSIXDynamic_riscv32.h lldb/include/lldb/Target/DynamicRegisterInfo.h lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_riscv32.cpp lldb/source/Plugins/Process/Utility/RegisterInfos_riscv32.h lldb/source/Plugins/Process/Utility/lldb-riscv-register-enums.h lldb/source/Plugins/Process/elf-core/ProcessElfCore.cpp lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv32.cpp lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv32.h lldb/source/Plugins/Process/elf-core/RegisterUtilities.h lldb/source/Utility/RISCV_DWARF_Registers.h --diff_from_common_commit
``````````
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diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfos_riscv32.h b/lldb/source/Plugins/Process/Utility/RegisterInfos_riscv32.h
index e0d8a13eb..e77034ffd 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterInfos_riscv32.h
+++ b/lldb/source/Plugins/Process/Utility/RegisterInfos_riscv32.h
@@ -32,10 +32,8 @@ using namespace riscv_dwarf;
// Assuming register numbers seen in eh_frame and DWARF to be the same.
#define KIND_HELPER(reg, generic_kind) \
- { \
- riscv_dwarf::dwarf_##reg, riscv_dwarf::dwarf_##reg, generic_kind, \
- LLDB_INVALID_REGNUM, reg##_riscv \
- }
+ {riscv_dwarf::dwarf_##reg, riscv_dwarf::dwarf_##reg, generic_kind, \
+ LLDB_INVALID_REGNUM, reg##_riscv}
// Generates RegisterInfo::kinds for GPRs.
#define GPR32_KIND(reg, generic_kind) KIND_HELPER(reg, generic_kind)
@@ -55,9 +53,16 @@ using namespace riscv_dwarf;
// Defines a 32-bit GPR.
#define DEFINE_GPR32_ALT(reg, alt, generic_kind) \
{ \
- #reg, #alt, 4, GPR_OFFSET(gpr_##reg##_riscv - gpr_first_riscv), \
- lldb::eEncodingUint, lldb::eFormatHex, \
- GPR32_KIND(gpr_##reg, generic_kind), nullptr, nullptr, nullptr, \
+ #reg, \
+ #alt, \
+ 4, \
+ GPR_OFFSET(gpr_##reg##_riscv - gpr_first_riscv), \
+ lldb::eEncodingUint, \
+ lldb::eFormatHex, \
+ GPR32_KIND(gpr_##reg, generic_kind), \
+ nullptr, \
+ nullptr, \
+ nullptr, \
}
// Defines a 32-bit FPR.
@@ -67,9 +72,16 @@ using namespace riscv_dwarf;
// Defines a 32-bit FPR.
#define DEFINE_FPR_ALT(reg, alt, size, generic_kind) \
{ \
- #reg, #alt, size, FPR_OFFSET(fpr_##reg##_riscv - fpr_first_riscv), \
- lldb::eEncodingIEEE754, lldb::eFormatHex, \
- FPR32_KIND(fpr_##reg, generic_kind), nullptr, nullptr, nullptr, \
+ #reg, \
+ #alt, \
+ size, \
+ FPR_OFFSET(fpr_##reg##_riscv - fpr_first_riscv), \
+ lldb::eEncodingIEEE754, \
+ lldb::eFormatHex, \
+ FPR32_KIND(fpr_##reg, generic_kind), \
+ nullptr, \
+ nullptr, \
+ nullptr, \
}
// Defines a 32-bit VPR.
@@ -79,20 +91,32 @@ using namespace riscv_dwarf;
// The byte offset of 0 is a placeholder and should be corrected at runtime.
// Defines a 32-bit VPR.
#define DEFINE_VPR_ALT(reg, alt, generic_kind) \
- { \
- #reg, #alt, 16, 0, lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, \
- VPR_KIND(vpr_##reg, generic_kind), nullptr, nullptr, nullptr \
- }
+ {#reg, \
+ #alt, \
+ 16, \
+ 0, \
+ lldb::eEncodingVector, \
+ lldb::eFormatVectorOfUInt8, \
+ VPR_KIND(vpr_##reg, generic_kind), \
+ nullptr, \
+ nullptr, \
+ nullptr}
// Defines a 32-bit CSR.
#define DEFINE_CSR32(reg, generic_kind) DEFINE_CSR32_ALT(reg, reg, generic_kind)
// Defines a 32-bit CSR.
#define DEFINE_CSR32_ALT(reg, alt, generic_kind) \
- { \
- #reg, #alt, 4, 0, lldb::eEncodingUint, lldb::eFormatHex, \
- CSR_KIND(csr_##reg, generic_kind), nullptr, nullptr, nullptr \
- }
+ {#reg, \
+ #alt, \
+ 4, \
+ 0, \
+ lldb::eEncodingUint, \
+ lldb::eFormatHex, \
+ CSR_KIND(csr_##reg, generic_kind), \
+ nullptr, \
+ nullptr, \
+ nullptr}
static lldb_private::RegisterInfo g_register_infos_riscv32_le[] = {
// DEFINE_GPR32(name, GENERIC KIND)
``````````
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https://github.com/llvm/llvm-project/pull/142932
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