[Lldb-commits] [lldb] [llvm] [AArch64][llvm] Tighten SYSP parsing; don't disassemble invalid encodings (PR #182410)

[via lldb-commits]

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@@ -833,14 +833,14 @@ def MrrsMssrPairClassOperand :
     RegisterOperand<XSeqPairsClass, "printGPRSeqPairsClassOperand<64>"> {
   let ParserMatchClass = XSeqPairsAsmOperandClass;
 }
-def SyspXzrPairOperandMatcherClass : AsmOperandClass {
-  let Name = "SyspXzrPair";
-  let RenderMethod = "addSyspXzrPairOperand";
-  let ParserMethod = "tryParseSyspXzrPair";
-}
-def SyspXzrPairOperand :
-    RegisterOperand<GPR64, "printSyspXzrPair"> { // needed to allow alias with XZR operand
-  let ParserMatchClass = SyspXzrPairOperandMatcherClass;
+def SyspPairOperandMatcherClass : AsmOperandClass {
+  let Name = "SyspPair";
+  let RenderMethod = "addRegOperands";
+  let ParserMethod = "tryParseSyspPair";
+}
+def SyspPairOperand :
+    RegisterOperand<GPR64, "printSyspPair"> {
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Lukacma wrote:

I missed this before but this is incorrect. In terms of register classes, this operand is basically XSeqPairsClass + [XZR, XZR] and you need to treat it as such. Now I don't know if compiler will allow you to specify it like that. Even if it does I am not sure if reg allocation will work on this, But we can figure that out if we ever need it for codegen. If this approach works, I think we will also not need custom printer, assembler etc... but can reuse the ones from XSeqPairsClass with maybe minor modifications

https://github.com/llvm/llvm-project/pull/182410