[Lldb-commits] [lldb] [lldb] AArch64 register 33 is not cpsr (PR #183860)
Jason Molenda via lldb-commits
lldb-commits at lists.llvm.org
Mon Mar 2 20:52:16 PST 2026
https://github.com/jasonmolenda updated https://github.com/llvm/llvm-project/pull/183860
>From efec85dbce173597ef27912fb02ba3c851808c03 Mon Sep 17 00:00:00 2001
From: Jason Molenda <jmolenda at apple.com>
Date: Fri, 27 Feb 2026 15:01:41 -0800
Subject: [PATCH 1/2] [lldb] AArch64 register 33 is not cpsr
I have an unwind failure where the eh_frame for a
trap handler states that the caller's return address
is in eh_frame register 33, which lldb treats as cpsr.
https://github.com/ARM-software/abi-aa/blob/main/aadwarf64/aadwarf64.rst#dwarf-register-names
Register 33 is ELR_mode, which isn't defined as a register in any
of the AArch64 register definition files in lldb today, so I'm not
adding it to the header files.
rdar://170602999
---
.../source/Plugins/ABI/AArch64/ABIAArch64.cpp | 2 -
.../Utility/RegisterContextDarwin_arm64.cpp | 4 -
.../Process/Utility/RegisterInfos_arm64.h | 28 ++--
.../Process/Utility/RegisterInfos_arm64_sve.h | 10 +-
.../RegisterContextMinidump_ARM64.cpp | 150 ++++++++++--------
lldb/source/Utility/ARM64_DWARF_Registers.h | 10 +-
lldb/source/Utility/ARM64_ehframe_Registers.h | 10 +-
7 files changed, 118 insertions(+), 96 deletions(-)
diff --git a/lldb/source/Plugins/ABI/AArch64/ABIAArch64.cpp b/lldb/source/Plugins/ABI/AArch64/ABIAArch64.cpp
index 8bfb4327a5f73..72d03e2348e59 100644
--- a/lldb/source/Plugins/ABI/AArch64/ABIAArch64.cpp
+++ b/lldb/source/Plugins/ABI/AArch64/ABIAArch64.cpp
@@ -71,8 +71,6 @@ std::pair<uint32_t, uint32_t>
ABIAArch64::GetEHAndDWARFNums(llvm::StringRef name) {
if (name == "pc")
return {arm64_ehframe::pc, arm64_dwarf::pc};
- if (name == "cpsr")
- return {arm64_ehframe::cpsr, arm64_dwarf::cpsr};
return MCBasedABI::GetEHAndDWARFNums(name);
}
diff --git a/lldb/source/Plugins/Process/Utility/RegisterContextDarwin_arm64.cpp b/lldb/source/Plugins/Process/Utility/RegisterContextDarwin_arm64.cpp
index 3bcd9a28e3f1b..43338c8cbc792 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterContextDarwin_arm64.cpp
+++ b/lldb/source/Plugins/Process/Utility/RegisterContextDarwin_arm64.cpp
@@ -768,8 +768,6 @@ uint32_t RegisterContextDarwin_arm64::ConvertRegisterKindToRegisterNumber(
return gpr_lr;
case arm64_dwarf::pc:
return gpr_pc;
- case arm64_dwarf::cpsr:
- return gpr_cpsr;
case arm64_dwarf::v0:
return fpu_v0;
@@ -907,8 +905,6 @@ uint32_t RegisterContextDarwin_arm64::ConvertRegisterKindToRegisterNumber(
return gpr_lr;
case arm64_ehframe::pc:
return gpr_pc;
- case arm64_ehframe::cpsr:
- return gpr_cpsr;
}
} else if (kind == eRegisterKindLLDB) {
return reg;
diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfos_arm64.h b/lldb/source/Plugins/Process/Utility/RegisterInfos_arm64.h
index 829fa076d221e..f4f9beec3aa49 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterInfos_arm64.h
+++ b/lldb/source/Plugins/Process/Utility/RegisterInfos_arm64.h
@@ -486,9 +486,6 @@ static uint32_t g_d31_invalidates[] = {fpu_v31, fpu_s31, LLDB_INVALID_REGNUM};
// Generates register kinds array for vector registers
#define GPR64_KIND(reg, generic_kind) MISC_KIND(reg, gpr, generic_kind)
#define VREG_KIND(reg) MISC_KIND(reg, fpu, LLDB_INVALID_REGNUM)
-#define MISC_GPR_KIND(lldb_kind) MISC_KIND(cpsr, gpr, LLDB_REGNUM_GENERIC_FLAGS)
-#define MISC_FPU_KIND(lldb_kind) LLDB_KIND(lldb_kind)
-#define MISC_EXC_KIND(lldb_kind) LLDB_KIND(lldb_kind)
// Defines a 64-bit general purpose register
#define DEFINE_GPR64(reg, generic_kind) \
@@ -538,6 +535,15 @@ static uint32_t g_d31_invalidates[] = {fpu_v31, fpu_s31, LLDB_INVALID_REGNUM};
nullptr, \
}
+// Defines miscellaneous status and control registers like cpsr, fpsr etc
+// that have no DWARF/eh_frame register numbers.
+#define DEFINE_MISC_LLDB_REGS(reg, size, TYPE, lldb_kind) \
+ { \
+ #reg, nullptr, size, TYPE##_OFFSET_NAME(reg), lldb::eEncodingUint, \
+ lldb::eFormatHex, LLDB_KIND(lldb_kind), nullptr, nullptr, \
+ nullptr, \
+ }
+
// Defines pointer authentication mask registers
#define DEFINE_EXTENSION_REG(reg) \
{ \
@@ -588,8 +594,8 @@ static lldb_private::RegisterInfo g_register_infos_arm64_le[] = {
DEFINE_GPR64_ALT(sp, x31, LLDB_REGNUM_GENERIC_SP),
DEFINE_GPR64(pc, LLDB_REGNUM_GENERIC_PC),
- // DEFINE_MISC_REGS(name, size, TYPE, lldb kind)
- DEFINE_MISC_REGS(cpsr, 4, GPR, gpr_cpsr),
+ // DEFINE_MISC_LLDB_REGS(name, size, TYPE, lldb kind)
+ DEFINE_MISC_LLDB_REGS(cpsr, 4, GPR, gpr_cpsr),
// DEFINE_GPR32(name, parent name)
DEFINE_GPR32(w0, x0),
@@ -723,12 +729,12 @@ static lldb_private::RegisterInfo g_register_infos_arm64_le[] = {
DEFINE_FPU_PSEUDO(d30, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v30),
DEFINE_FPU_PSEUDO(d31, 8, FPU_D_PSEUDO_REG_ENDIAN_OFFSET, v31),
- // DEFINE_MISC_REGS(name, size, TYPE, lldb kind)
- DEFINE_MISC_REGS(fpsr, 4, FPU, fpu_fpsr),
- DEFINE_MISC_REGS(fpcr, 4, FPU, fpu_fpcr),
- DEFINE_MISC_REGS(far, 8, EXC, exc_far),
- DEFINE_MISC_REGS(esr, 4, EXC, exc_esr),
- DEFINE_MISC_REGS(exception, 4, EXC, exc_exception),
+ // DEFINE_MISC_LLDB_REGS(name, size, TYPE, lldb kind)
+ DEFINE_MISC_LLDB_REGS(fpsr, 4, FPU, fpu_fpsr),
+ DEFINE_MISC_LLDB_REGS(fpcr, 4, FPU, fpu_fpcr),
+ DEFINE_MISC_LLDB_REGS(far, 8, EXC, exc_far),
+ DEFINE_MISC_LLDB_REGS(esr, 4, EXC, exc_esr),
+ DEFINE_MISC_LLDB_REGS(exception, 4, EXC, exc_exception),
{DEFINE_DBG(bvr, 0)},
{DEFINE_DBG(bvr, 1)},
diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfos_arm64_sve.h b/lldb/source/Plugins/Process/Utility/RegisterInfos_arm64_sve.h
index 283c4c17e7605..f1dca1b2a89e4 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterInfos_arm64_sve.h
+++ b/lldb/source/Plugins/Process/Utility/RegisterInfos_arm64_sve.h
@@ -373,8 +373,8 @@ static lldb_private::RegisterInfo g_register_infos_arm64_sve_le[] = {
DEFINE_GPR64_ALT(sp, x31, LLDB_REGNUM_GENERIC_SP),
DEFINE_GPR64(pc, LLDB_REGNUM_GENERIC_PC),
- // DEFINE_MISC_REGS(name, size, TYPE, lldb kind)
- DEFINE_MISC_REGS(cpsr, 4, GPR, gpr_cpsr),
+ // DEFINE_MISC_LLDB_REGS(name, size, TYPE, lldb kind)
+ DEFINE_MISC_LLDB_REGS(cpsr, 4, GPR, gpr_cpsr),
// DEFINE_GPR32(name, parent name)
DEFINE_GPR32(w0, x0),
@@ -508,9 +508,9 @@ static lldb_private::RegisterInfo g_register_infos_arm64_sve_le[] = {
DEFINE_FPU_PSEUDO_SVE(d30, 8, z30),
DEFINE_FPU_PSEUDO_SVE(d31, 8, z31),
- // DEFINE_MISC_REGS(name, size, TYPE, lldb kind)
- DEFINE_MISC_REGS(fpsr, 4, FPU, fpu_fpsr),
- DEFINE_MISC_REGS(fpcr, 4, FPU, fpu_fpcr),
+ // DEFINE_MISC_LLDB_REGS(name, size, TYPE, lldb kind)
+ DEFINE_MISC_LLDB_REGS(fpsr, 4, FPU, fpu_fpsr),
+ DEFINE_MISC_LLDB_REGS(fpcr, 4, FPU, fpu_fpcr),
DEFINE_MISC_REGS(vg, 8, VG, sve_vg),
// DEFINE_ZREG(name)
diff --git a/lldb/source/Plugins/Process/minidump/RegisterContextMinidump_ARM64.cpp b/lldb/source/Plugins/Process/minidump/RegisterContextMinidump_ARM64.cpp
index a0476c962070c..cff14f87ae10e 100644
--- a/lldb/source/Plugins/Process/minidump/RegisterContextMinidump_ARM64.cpp
+++ b/lldb/source/Plugins/Process/minidump/RegisterContextMinidump_ARM64.cpp
@@ -307,49 +307,56 @@ static RegisterInfo g_reg_infos[] = {
DEF_X(26),
DEF_X(27),
DEF_X(28),
- {"fp",
- "x29",
- 8,
- OFFSET(x) + 29 * 8,
- eEncodingUint,
- eFormatHex,
- {arm64_dwarf::x29, arm64_dwarf::x29, LLDB_REGNUM_GENERIC_FP, INV, reg_fp},
- nullptr,
- nullptr,
- nullptr,
+ {
+ "fp",
+ "x29",
+ 8,
+ OFFSET(x) + 29 * 8,
+ eEncodingUint,
+ eFormatHex,
+ {arm64_dwarf::x29, arm64_dwarf::x29, LLDB_REGNUM_GENERIC_FP, INV,
+ reg_fp},
+ nullptr,
+ nullptr,
+ nullptr,
},
- {"lr",
- "x30",
- 8,
- OFFSET(x) + 30 * 8,
- eEncodingUint,
- eFormatHex,
- {arm64_dwarf::x30, arm64_dwarf::x30, LLDB_REGNUM_GENERIC_RA, INV, reg_lr},
- nullptr,
- nullptr,
- nullptr,
+ {
+ "lr",
+ "x30",
+ 8,
+ OFFSET(x) + 30 * 8,
+ eEncodingUint,
+ eFormatHex,
+ {arm64_dwarf::x30, arm64_dwarf::x30, LLDB_REGNUM_GENERIC_RA, INV,
+ reg_lr},
+ nullptr,
+ nullptr,
+ nullptr,
},
- {"sp",
- "x31",
- 8,
- OFFSET(x) + 31 * 8,
- eEncodingUint,
- eFormatHex,
- {arm64_dwarf::x31, arm64_dwarf::x31, LLDB_REGNUM_GENERIC_SP, INV, reg_sp},
- nullptr,
- nullptr,
- nullptr,
+ {
+ "sp",
+ "x31",
+ 8,
+ OFFSET(x) + 31 * 8,
+ eEncodingUint,
+ eFormatHex,
+ {arm64_dwarf::x31, arm64_dwarf::x31, LLDB_REGNUM_GENERIC_SP, INV,
+ reg_sp},
+ nullptr,
+ nullptr,
+ nullptr,
},
- {"pc",
- nullptr,
- 8,
- OFFSET(pc),
- eEncodingUint,
- eFormatHex,
- {arm64_dwarf::pc, arm64_dwarf::pc, LLDB_REGNUM_GENERIC_PC, INV, reg_pc},
- nullptr,
- nullptr,
- nullptr,
+ {
+ "pc",
+ nullptr,
+ 8,
+ OFFSET(pc),
+ eEncodingUint,
+ eFormatHex,
+ {arm64_dwarf::pc, arm64_dwarf::pc, LLDB_REGNUM_GENERIC_PC, INV, reg_pc},
+ nullptr,
+ nullptr,
+ nullptr,
},
// w0 - w31
DEF_W(0),
@@ -384,38 +391,41 @@ static RegisterInfo g_reg_infos[] = {
DEF_W(29),
DEF_W(30),
DEF_W(31),
- {"cpsr",
- "psr",
- 4,
- OFFSET(cpsr),
- eEncodingUint,
- eFormatHex,
- {INV, arm64_dwarf::cpsr, LLDB_REGNUM_GENERIC_FLAGS, INV, reg_cpsr},
- nullptr,
- nullptr,
- nullptr,
+ {
+ "cpsr",
+ "psr",
+ 4,
+ OFFSET(cpsr),
+ eEncodingUint,
+ eFormatHex,
+ {INV, INV, LLDB_REGNUM_GENERIC_FLAGS, INV, reg_cpsr},
+ nullptr,
+ nullptr,
+ nullptr,
},
- {"fpsr",
- nullptr,
- 4,
- OFFSET(fpsr),
- eEncodingUint,
- eFormatHex,
- {INV, INV, INV, INV, reg_fpsr},
- nullptr,
- nullptr,
- nullptr,
+ {
+ "fpsr",
+ nullptr,
+ 4,
+ OFFSET(fpsr),
+ eEncodingUint,
+ eFormatHex,
+ {INV, INV, INV, INV, reg_fpsr},
+ nullptr,
+ nullptr,
+ nullptr,
},
- {"fpcr",
- nullptr,
- 4,
- OFFSET(fpcr),
- eEncodingUint,
- eFormatHex,
- {INV, INV, INV, INV, reg_fpcr},
- nullptr,
- nullptr,
- nullptr,
+ {
+ "fpcr",
+ nullptr,
+ 4,
+ OFFSET(fpcr),
+ eEncodingUint,
+ eFormatHex,
+ {INV, INV, INV, INV, reg_fpcr},
+ nullptr,
+ nullptr,
+ nullptr,
},
// v0 - v31
DEF_V(0),
diff --git a/lldb/source/Utility/ARM64_DWARF_Registers.h b/lldb/source/Utility/ARM64_DWARF_Registers.h
index ed8ff722088dc..47e6de000c8fa 100644
--- a/lldb/source/Utility/ARM64_DWARF_Registers.h
+++ b/lldb/source/Utility/ARM64_DWARF_Registers.h
@@ -50,8 +50,14 @@ enum {
x31 = 31,
sp = x31,
pc = 32,
- cpsr = 33,
- // 34-45 reserved
+ // 33 ELR_mode
+ // 34 RA_SIGN_STATE
+ // 35 TPIDRRO_EL0
+ // 36 TPIDR_ELO
+ // 37 TPIDR_EL1
+ // 38 TPIDR_EL2
+ // 39 TPIDR_EL3
+ // 40-45 Reserved
// 64-bit SVE Vector granule pseudo register
vg = 46,
diff --git a/lldb/source/Utility/ARM64_ehframe_Registers.h b/lldb/source/Utility/ARM64_ehframe_Registers.h
index c235891ec015e..3eb92ed30ad0d 100644
--- a/lldb/source/Utility/ARM64_ehframe_Registers.h
+++ b/lldb/source/Utility/ARM64_ehframe_Registers.h
@@ -49,8 +49,14 @@ enum {
lr, // aka x30
sp, // aka x31 aka wzr
pc, // value is 32
- cpsr,
- // 34-45 reserved
+ // 33 ELR_mode
+ // 34 RA_SIGN_STATE
+ // 35 TPIDRRO_EL0
+ // 36 TPIDR_ELO
+ // 37 TPIDR_EL1
+ // 38 TPIDR_EL2
+ // 39 TPIDR_EL3
+ // 40-45 Reserved
// 64-bit SVE Vector granule pseudo register
vg = 46,
>From 5399518ff03c546fc43c91571c977d62e0362b71 Mon Sep 17 00:00:00 2001
From: Jason Molenda <jmolenda at apple.com>
Date: Mon, 2 Mar 2026 20:51:34 -0800
Subject: [PATCH 2/2] Add enums for the other registers defined in the AArch64
DWARF ABI,
https://github.com/ARM-software/abi-aa/blob/main/aadwarf64/aadwarf64.rst#dwarf-register-names
---
lldb/source/Utility/ARM64_DWARF_Registers.h | 14 +++++++-------
lldb/source/Utility/ARM64_ehframe_Registers.h | 14 +++++++-------
2 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/lldb/source/Utility/ARM64_DWARF_Registers.h b/lldb/source/Utility/ARM64_DWARF_Registers.h
index 47e6de000c8fa..d495876bf7128 100644
--- a/lldb/source/Utility/ARM64_DWARF_Registers.h
+++ b/lldb/source/Utility/ARM64_DWARF_Registers.h
@@ -50,13 +50,13 @@ enum {
x31 = 31,
sp = x31,
pc = 32,
- // 33 ELR_mode
- // 34 RA_SIGN_STATE
- // 35 TPIDRRO_EL0
- // 36 TPIDR_ELO
- // 37 TPIDR_EL1
- // 38 TPIDR_EL2
- // 39 TPIDR_EL3
+ elr_mode = 33,
+ ra_sign_state = 34,
+ tpidrr0_el0 = 35,
+ tpidr_el0 = 36,
+ tpidr_el1 = 37,
+ tpidr_el2 = 38,
+ tpidr_el3 = 39,
// 40-45 Reserved
// 64-bit SVE Vector granule pseudo register
diff --git a/lldb/source/Utility/ARM64_ehframe_Registers.h b/lldb/source/Utility/ARM64_ehframe_Registers.h
index 3eb92ed30ad0d..8b39589f98e96 100644
--- a/lldb/source/Utility/ARM64_ehframe_Registers.h
+++ b/lldb/source/Utility/ARM64_ehframe_Registers.h
@@ -49,13 +49,13 @@ enum {
lr, // aka x30
sp, // aka x31 aka wzr
pc, // value is 32
- // 33 ELR_mode
- // 34 RA_SIGN_STATE
- // 35 TPIDRRO_EL0
- // 36 TPIDR_ELO
- // 37 TPIDR_EL1
- // 38 TPIDR_EL2
- // 39 TPIDR_EL3
+ elr_mode = 33,
+ ra_sign_state = 34,
+ tpidrr0_el0 = 35,
+ tpidr_el0 = 36,
+ tpidr_el1 = 37,
+ tpidr_el2 = 38,
+ tpidr_el3 = 39,
// 40-45 Reserved
// 64-bit SVE Vector granule pseudo register
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