[Lldb-commits] [lldb] [lldb][test] Mark TestDisassembler with @skipIfLLVMTargetMissing("RISCV") (PR #182126)

[via lldb-commits]

https://github.com/daniilavdeev created https://github.com/llvm/llvm-project/pull/182126

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>From 624f2ae150d5f8df962c7664aeb9b86d23ca97bb Mon Sep 17 00:00:00 2001
From: Daniil Avdeev <daniilavdeev237 at gmail.com>
Date: Wed, 18 Feb 2026 20:29:17 +0000
Subject: [PATCH] [lldb][test] Mark TestDisassembler with
 @skipIfLLVMTargetMissing("RISCV")

---
 lldb/test/API/riscv/disassembler/TestDisassembler.py | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/lldb/test/API/riscv/disassembler/TestDisassembler.py b/lldb/test/API/riscv/disassembler/TestDisassembler.py
index 2f01283786b1f..d1badc153f486 100644
--- a/lldb/test/API/riscv/disassembler/TestDisassembler.py
+++ b/lldb/test/API/riscv/disassembler/TestDisassembler.py
@@ -12,6 +12,7 @@
 class TestDisassembler(TestBase):
     expected_zbb_instrs = ["andn", "orn", "xnor", "rol", "ror"]
 
+    @skipIfLLVMTargetMissing("RISCV")
     def test_without_riscv_attributes(self):
         """
         Tests disassembly of a riscv binary without the .riscv.attributes.
@@ -39,6 +40,7 @@ def test_without_riscv_attributes(self):
             "Instructions from the Zbb extension should be displayed as <unknown>",
         )
 
+    @skipIfLLVMTargetMissing("RISCV")
     def test_with_riscv_attributes(self):
         """
         Tests disassembly of a riscv binary with the .riscv.attributes.
@@ -55,6 +57,7 @@ def test_with_riscv_attributes(self):
         for instr in self.expected_zbb_instrs:
             self.assertTrue(instr in output, "Invalid disassembler output")
 
+    @skipIfLLVMTargetMissing("RISCV")
     def test_conflicting_extensions(self):
         """
         This test demonstrates the scenario where: