[Lldb-commits] [lldb] [lldb][RISCV] Use uint64_t for emulating ADDI (PR #160550)

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llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-lldb

Author: Ivan Tadeu Ferreira Antunes Filho (itf)

<details>
<summary>Changes</summary>

In RISC-V, the ADDI instruction simply performs a binary addition on the registers. The same instruction is used for both signed and unsigned additions.

As we are emulating the riscv behavior we should be using uint.

This fix the failure with ubsan: lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp:807:40: runtime error: signed integer overflow: -9223372036854775808 + -16 cannot be represented in type 'int64_t' (aka 'long')

---
Full diff: https://github.com/llvm/llvm-project/pull/160550.diff


1 Files Affected:

- (modified) lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp (+1-1) 


``````````diff
diff --git a/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp b/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
index 20661290ca4c6..5c1b7d4943b3f 100644
--- a/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
+++ b/lldb/source/Plugins/Instruction/RISCV/EmulateInstructionRISCV.cpp
@@ -804,7 +804,7 @@ class Executor {
     return transformOptional(
                inst.rs1.ReadI64(m_emu),
                [&](int64_t rs1) {
-                 int64_t result = rs1 + int64_t(SignExt(inst.imm));
+                 uint64_t result = rs1 + uint64_t(SignExt(inst.imm));
                  // Check if this is a stack pointer adjustment.
                  if (inst.rd.rd == RISCV_GPR_SP &&
                      inst.rs1.rs == RISCV_GPR_SP) {

``````````

</details>


https://github.com/llvm/llvm-project/pull/160550