[Lldb-commits] [lldb] RISCV unwinding enable (PR #158161)

[via lldb-commits]

================
@@ -230,10 +230,36 @@ Load(EmulateInstructionRISCV &emulator, I inst, uint64_t (*extend)(E)) {
   auto addr = LoadStoreAddr(emulator, inst);
   if (!addr)
     return false;
-  return transformOptional(
-             emulator.ReadMem<T>(*addr),
-             [&](T t) { return inst.rd.Write(emulator, extend(E(t))); })
-      .value_or(false);
+
+  // Set up context for the load operation, similar to ARM64
+  EmulateInstructionRISCV::Context context;
+
+  // Get register info for base register
+  uint32_t rs1_lldb = GPREncodingToLLDB(inst.rs1.rs);
+  std::optional<RegisterInfo> reg_info_rs1 =
+      emulator.GetRegisterInfo(eRegisterKindLLDB, rs1_lldb);
+
+  if (!reg_info_rs1)
+    return false;
+
+  // Set context type based on whether this is a stack-based load
+  if (inst.rs1.rs == 2) { // x2 is the stack pointer in RISC-V
+    context.type = EmulateInstruction::eContextPopRegisterOffStack;
+  } else {
+    context.type = EmulateInstruction::eContextRegisterLoad;
+  }
+
+  // Set the context address information
+  context.SetAddress(*addr);
+
+  // Read from memory with context and write to register
+  bool success = false;
+  uint64_t value =
+      emulator.ReadMemoryUnsigned(context, *addr, sizeof(T), 0, &success);
+  if (!success)
+    return false;
+
+  return inst.rd.Write(emulator, extend(E(T(value))));
----------------
barsolo2000 wrote:

yes, it does. 
the chain is: inst.rd.Write -> Rd::Write(EmulateInstructionRISCV &emulator, uint64_t value) -> emulator.WriteRegister(ctx, eRegisterKindLLDB, lldb_reg, registerValue)

https://github.com/llvm/llvm-project/pull/158161