[Lldb-commits] [lldb] [lldb] Fix auto advance PC in `EmulateInstructionARM64` if PC >= 4G (PR #151460)

[David Spickett via lldb-commits]

================
@@ -13,15 +13,124 @@
 #include "lldb/Core/Disassembler.h"
 #include "lldb/Target/ExecutionContext.h"
 #include "lldb/Utility/ArchSpec.h"
+#include "lldb/Utility/RegisterValue.h"
 
 #include "Plugins/Instruction/ARM64/EmulateInstructionARM64.h"
+#include "Plugins/Process/Utility/RegisterInfoPOSIX_arm64.h"
+#include "Plugins/Process/Utility/lldb-arm64-register-enums.h"
 
 using namespace lldb;
 using namespace lldb_private;
 
 struct Arch64EmulatorTester : public EmulateInstructionARM64 {
+  RegisterInfoPOSIX_arm64::GPR gpr;
+  uint8_t memory[64] = {0};
+  uint64_t memory_offset = 0;
+
   Arch64EmulatorTester()
-      : EmulateInstructionARM64(ArchSpec("arm64-apple-ios")) {}
+      : EmulateInstructionARM64(ArchSpec("arm64-apple-ios")) {
+    memset(&gpr, 0, sizeof(gpr));
+    EmulateInstruction::SetCallbacks(ReadMemoryCallback, WriteMemoryCallback,
+                                     ReadRegisterCallback,
+                                     WriteRegisterCallback);
+  }
+
+  static bool ReadRegisterCallback(EmulateInstruction *instruction, void *baton,
+                                   const RegisterInfo *reg_info,
+                                   RegisterValue &reg_value) {
+    auto *tester = static_cast<Arch64EmulatorTester *>(instruction);
+    uint32_t reg = reg_info->kinds[eRegisterKindLLDB];
+    if (reg >= gpr_x1_arm64 && reg <= gpr_x28_arm64) {
+      reg_value.SetUInt64(tester->gpr.x[reg - gpr_x0_arm64]);
+      return true;
+    }
+    if (reg >= gpr_w1_arm64 && reg <= gpr_w28_arm64) {
+      reg_value.SetUInt32(tester->gpr.x[reg - gpr_w0_arm64]);
+      return true;
+    }
+    switch (reg) {
+    case gpr_x0_arm64:
+      reg_value.SetUInt64(0);
+      return true;
+    case gpr_w0_arm64:
+      reg_value.SetUInt32(0);
+      return true;
----------------
DavidSpickett wrote:

Why are these tied to 0? AArch64's zero register is `xzr` and it's not the 0th register as it is for MIPS and RISC-V.

https://github.com/llvm/llvm-project/pull/151460