[Lldb-commits] [lldb] Support disassembling RISC-V proprietary instructions (PR #145793)

David Spickett via lldb-commits lldb-commits at lists.llvm.org
Fri Jun 27 07:52:17 PDT 2025


DavidSpickett wrote:

> Arm M profile has https://developer.arm.com/Architectures/Arm%20Custom%20Instructions, I'll look into that and see if it would benefit from a change of output format too. Just in theory though, I don't think we shipped support for open source debuggers and I'm not about to implement it myself.

CDE works by assigning one of the co-processors to be the encodings for the custom instructions and it has a few fixed formats you can use. It's not like RISC-V where the layout can be anything you want. Which means that the disassembler would probably print some form, with encoding, and that can already be used to filter if you wanted to.

I also checked how AArch64 works:
``
$ cat /tmp/test.c
int main() {
  asm volatile(".inst 0x43214444");
  return 0;
}
```
objdump shows the bytes:
```
0000000000000714 <main>:
     714: d10043ff     	sub	sp, sp, #0x10
     718: 2a1f03e0     	mov	w0, wzr
     71c: b9000fff     	str	wzr, [sp, #0xc]
     720: 43214444     	<unknown>
     724: 910043ff     	add	sp, sp, #0x10
     728: d65f03c0     	ret
```
As does LLDB:
```
(lldb) dis -b
test.o`main:
    0xaaaaaaaaa714 <+0>:  0xd10043ff   sub    sp, sp, #0x10
    0xaaaaaaaaa718 <+4>:  0x2a1f03e0   mov    w0, wzr
    0xaaaaaaaaa71c <+8>:  0xb9000fff   str    wzr, [sp, #0xc]
->  0xaaaaaaaaa720 <+12>: 0x43214444                                    ; unknown opcode
    0xaaaaaaaaa724 <+16>: 0x910043ff   add    sp, sp, #0x10
    0xaaaaaaaaa728 <+20>: 0xd65f03c0   ret
```
So for AArch64 we happen to mostly match objdump's output, and it's useful enough for humans and scripts because it can only ever be 32-bit encodings.

Also having looked at the pretty printer system in llvm-objdump, I think `if riscv` is ok here. LLDB is effectively a selective objdumper and the only difference between what you're adding here and what llvm-objdump has is the framework around it. Which we do not need when only RISC-V wants this.

https://github.com/llvm/llvm-project/pull/145793


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