[Lldb-commits] [lldb] [lldb][RISCV] fix LR/SC atomic sequence handling in lldb-server (PR #127505)

[via lldb-commits]

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@@ -0,0 +1,90 @@
+"""
+Test software step-inst
+"""
+
+import lldb
+from lldbsuite.test.decorators import *
+from lldbsuite.test.lldbtest import *
+from lldbsuite.test import lldbutil
+
+
+class TestSoftwareStep(TestBase):
+    @skipIf(archs=no_match(re.compile("rv*")))
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dlav-sc wrote:

I didn't think about performance here, I just want to ensure this works with any riscv configuration (rv32, rv64, rv64gc, rv64gvc and so on). I can't really say whether your idea about `skipIf` is good, because I think I don't know python well enough to judge here.

https://github.com/llvm/llvm-project/pull/127505