[Lldb-commits] [lldb] [lldb][RISCV] Handle subsets of CSRs in RV32 core dump images (PR #142932)
Ayush Sahay via lldb-commits
lldb-commits at lists.llvm.org
Thu Jun 5 02:00:24 PDT 2025
https://github.com/ayushsahay1837 created https://github.com/llvm/llvm-project/pull/142932
The standard RISC-V ISA sets aside a 12-bit encoding space for up to 4,096 CSRs. However, many of these may remain unutilized and needn't be saved in core dump images. To address this, we've come up with a new note, _NT_CSREGMAP_, that saves subsets of CSRs as key-value pairs. This change provisions support for handling the subsets of CSRs saved in 32-bit RISC-V core dump images by building the register information for GPRs, FPRs, and CSRs dynamically.
Kindly refer to the corresponding topic ([Add RISC-V CSRs to core dumps](https://discourse.llvm.org/t/add-risc-v-csrs-to-core-dumps/84348)) for additional details.
>From d6729ddbea677b53b2b6617e7c863bd8e165ffb4 Mon Sep 17 00:00:00 2001
From: Ayush Sahay <quic_asahay at quicinc.com>
Date: Wed, 4 Jun 2025 15:45:30 +0530
Subject: [PATCH] [lldb][RISCV] Handle subsets of CSRs in RV32 core dump images
The standard RISC-V ISA sets aside a 12-bit encoding space for up to
4,096 CSRs. However, many of these may remain unutilized and needn't be
saved in core dump images. To address this, we've come up with a new
note, NT_CSREGMAP, that saves subsets of CSRs as key-value pairs. This
change provisions support for handling the subsets of CSRs saved in
32-bit RISC-V core dump images by building the register information for
GPRs, FPRs, and CSRs dynamically.
---
.../include/lldb/Target/DynamicRegisterInfo.h | 8 +
.../Plugins/Process/Utility/CMakeLists.txt | 1 +
.../RegisterInfoPOSIXDynamic_riscv32.cpp | 87 +
.../RegisterInfoPOSIXDynamic_riscv32.h | 50 +
.../Utility/RegisterInfoPOSIX_riscv32.cpp | 3 +
.../Process/Utility/RegisterInfos_riscv32.h | 4250 +++++++++++++++-
.../Utility/lldb-riscv-register-enums.h | 4473 ++++++++++++++++
.../Process/elf-core/ProcessElfCore.cpp | 10 +-
.../RegisterContextPOSIXCore_riscv32.cpp | 359 +-
.../RegisterContextPOSIXCore_riscv32.h | 39 +-
.../Process/elf-core/RegisterUtilities.h | 12 +
lldb/source/Utility/RISCV_DWARF_Registers.h | 4502 ++++++++++++++++-
12 files changed, 13716 insertions(+), 78 deletions(-)
create mode 100644 lldb/source/Plugins/Process/Utility/RegisterInfoPOSIXDynamic_riscv32.cpp
create mode 100644 lldb/source/Plugins/Process/Utility/RegisterInfoPOSIXDynamic_riscv32.h
diff --git a/lldb/include/lldb/Target/DynamicRegisterInfo.h b/lldb/include/lldb/Target/DynamicRegisterInfo.h
index 43bba5038e537..558adefe2e151 100644
--- a/lldb/include/lldb/Target/DynamicRegisterInfo.h
+++ b/lldb/include/lldb/Target/DynamicRegisterInfo.h
@@ -95,6 +95,8 @@ class DynamicRegisterInfo {
template <typename T> T registers() = delete;
+ template <typename T> T registers() const = delete;
+
void ConfigureOffsets();
protected:
@@ -145,6 +147,12 @@ DynamicRegisterInfo::registers() {
return reg_collection_range(m_regs);
}
+template <>
+inline DynamicRegisterInfo::reg_collection_const_range
+DynamicRegisterInfo::registers() const {
+ return reg_collection_const_range(m_regs);
+}
+
void addSupplementaryRegister(std::vector<DynamicRegisterInfo::Register> ®s,
DynamicRegisterInfo::Register new_reg_info);
diff --git a/lldb/source/Plugins/Process/Utility/CMakeLists.txt b/lldb/source/Plugins/Process/Utility/CMakeLists.txt
index fd3019613892a..53313e139c4e7 100644
--- a/lldb/source/Plugins/Process/Utility/CMakeLists.txt
+++ b/lldb/source/Plugins/Process/Utility/CMakeLists.txt
@@ -60,6 +60,7 @@ add_lldb_library(lldbPluginProcessUtility
RegisterInfoPOSIX_ppc64le.cpp
RegisterInfoPOSIX_riscv32.cpp
RegisterInfoPOSIX_riscv64.cpp
+ RegisterInfoPOSIXDynamic_riscv32.cpp
StopInfoMachException.cpp
ThreadMemory.cpp
diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIXDynamic_riscv32.cpp b/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIXDynamic_riscv32.cpp
new file mode 100644
index 0000000000000..950c0c3d3cae8
--- /dev/null
+++ b/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIXDynamic_riscv32.cpp
@@ -0,0 +1,87 @@
+//===-- RegisterInfoPOSIXDynamic_riscv32.cpp ------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===---------------------------------------------------------------------===//
+
+#include <lldb/Utility/Flags.h>
+#include <stddef.h>
+
+#include "lldb/lldb-defines.h"
+#include "llvm/Support/Compiler.h"
+
+#include "RegisterInfoPOSIXDynamic_riscv32.h"
+
+RegisterInfoPOSIXDynamic_riscv32::RegisterInfoPOSIXDynamic_riscv32(
+ const lldb_private::ArchSpec &target_arch)
+ : lldb_private::RegisterInfoAndSetInterface(target_arch),
+ m_target_arch(target_arch) {}
+
+uint32_t RegisterInfoPOSIXDynamic_riscv32::GetRegisterCount() const {
+ return m_dyn_reg_infos.GetNumRegisters();
+}
+
+size_t RegisterInfoPOSIXDynamic_riscv32::GetGPRSize() const {
+ for (uint32_t set_idx = 0; set_idx < GetRegisterSetCount(); ++set_idx) {
+ const lldb_private::RegisterSet *set =
+ m_dyn_reg_infos.GetRegisterSet(set_idx);
+ if (lldb_private::ConstString(set->name) == "GPR")
+ return set->num_registers;
+ }
+ return 0;
+}
+
+size_t RegisterInfoPOSIXDynamic_riscv32::GetFPRSize() const {
+ for (uint32_t set_idx = 0; set_idx < GetRegisterSetCount(); ++set_idx) {
+ const lldb_private::RegisterSet *set =
+ m_dyn_reg_infos.GetRegisterSet(set_idx);
+ if (lldb_private::ConstString(set->name) == "FPR")
+ return set->num_registers;
+ }
+ return 0;
+}
+
+const lldb_private::RegisterInfo *
+RegisterInfoPOSIXDynamic_riscv32::GetRegisterInfo() const {
+ return &*m_dyn_reg_infos
+ .registers<lldb_private::DynamicRegisterInfo::
+ reg_collection_const_range>()
+ .begin();
+}
+
+size_t RegisterInfoPOSIXDynamic_riscv32::GetRegisterSetCount() const {
+ return m_dyn_reg_infos.GetNumRegisterSets();
+}
+
+size_t RegisterInfoPOSIXDynamic_riscv32::GetRegisterSetFromRegisterIndex(
+ uint32_t reg_index) const {
+ for (size_t set_index = 0; set_index < m_dyn_reg_infos.GetNumRegisterSets();
+ ++set_index) {
+ const lldb_private::RegisterSet *reg_set =
+ m_dyn_reg_infos.GetRegisterSet(set_index);
+ for (uint32_t idx = 0; idx < reg_set->num_registers; ++idx)
+ if (reg_set->registers[idx] == reg_index)
+ return set_index;
+ }
+ return LLDB_INVALID_REGNUM;
+}
+
+const lldb_private::RegisterSet *
+RegisterInfoPOSIXDynamic_riscv32::GetRegisterSet(size_t set_index) const {
+ if (set_index < GetRegisterSetCount())
+ return m_dyn_reg_infos.GetRegisterSet(set_index);
+ return nullptr;
+}
+
+size_t RegisterInfoPOSIXDynamic_riscv32::SetRegisterInfo(
+ std::vector<lldb_private::DynamicRegisterInfo::Register> regs) {
+ return m_dyn_reg_infos.SetRegisterInfo(std::move(regs), m_target_arch);
+}
+
+const lldb_private::RegisterInfo *
+RegisterInfoPOSIXDynamic_riscv32::GetRegisterInfo(
+ llvm::StringRef reg_name) const {
+ return m_dyn_reg_infos.GetRegisterInfo(reg_name);
+}
diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIXDynamic_riscv32.h b/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIXDynamic_riscv32.h
new file mode 100644
index 0000000000000..b1f9b75e72df9
--- /dev/null
+++ b/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIXDynamic_riscv32.h
@@ -0,0 +1,50 @@
+//===-- RegisterInfoPOSIXDynamic_riscv32.h ----------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOPOSIXDYNAMIC_RISCV32_H
+#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOPOSIXDYNAMIC_RISCV32_H
+
+#include "RegisterInfoAndSetInterface.h"
+#include "lldb/Target/DynamicRegisterInfo.h"
+#include "lldb/Target/RegisterContext.h"
+#include "lldb/Utility/Flags.h"
+#include "lldb/lldb-private.h"
+#include <map>
+
+class RegisterInfoPOSIXDynamic_riscv32
+ : public lldb_private::RegisterInfoAndSetInterface {
+public:
+ RegisterInfoPOSIXDynamic_riscv32(const lldb_private::ArchSpec &target_arch);
+
+ size_t GetGPRSize() const override;
+
+ size_t GetFPRSize() const override;
+
+ const lldb_private::RegisterInfo *GetRegisterInfo() const override;
+
+ uint32_t GetRegisterCount() const override;
+
+ const lldb_private::RegisterSet *
+ GetRegisterSet(size_t reg_set) const override;
+
+ size_t GetRegisterSetCount() const override;
+
+ size_t GetRegisterSetFromRegisterIndex(uint32_t reg_index) const override;
+
+ size_t SetRegisterInfo(
+ std::vector<lldb_private::DynamicRegisterInfo::Register> regs);
+
+ const lldb_private::RegisterInfo *
+ GetRegisterInfo(llvm::StringRef reg_name) const;
+
+private:
+ lldb_private::DynamicRegisterInfo m_dyn_reg_infos;
+ const lldb_private::ArchSpec m_target_arch;
+};
+
+#endif // LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOPOSIXDYNAMIC_RISCV32_H
diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_riscv32.cpp b/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_riscv32.cpp
index e213b4a4a1820..e3093d52ff4ae 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_riscv32.cpp
+++ b/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_riscv32.cpp
@@ -16,6 +16,9 @@
#define GPR_OFFSET(idx) ((idx) * 4 + 0)
#define FPR_OFFSET(idx) ((idx) * 4 + sizeof(RegisterInfoPOSIX_riscv32::GPR))
+#define CSR_OFFSET(idx) \
+ ((idx) * 4 + sizeof(RegisterInfoPOSIX_riscv32::GPR) + \
+ sizeof(RegisterInfoPOSIX_riscv32::FPR))
#define REG_CONTEXT_SIZE \
(sizeof(RegisterInfoPOSIX_riscv32::GPR) + \
diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfos_riscv32.h b/lldb/source/Plugins/Process/Utility/RegisterInfos_riscv32.h
index ab6fec829bbce..1d1ad379d27db 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterInfos_riscv32.h
+++ b/lldb/source/Plugins/Process/Utility/RegisterInfos_riscv32.h
@@ -8,13 +8,14 @@
#ifdef DECLARE_REGISTER_INFOS_RISCV32_STRUCT
-#include "Utility/RISCV_DWARF_Registers.h"
-#include "lldb-riscv-register-enums.h"
+#include <stddef.h>
+
#include "lldb/lldb-defines.h"
#include "lldb/lldb-enumerations.h"
#include "lldb/lldb-private.h"
-#include <stddef.h>
+#include "Utility/RISCV_DWARF_Registers.h"
+#include "lldb-riscv-register-enums.h"
#ifndef GPR_OFFSET
#error GPR_OFFSET must be defined before including this header file
@@ -24,56 +25,76 @@
#error FPR_OFFSET must be defined before including this header file
#endif
+#ifndef CSR_OFFSET
+#error CSR_OFFSET must be defined before including this header file
+#endif
+
using namespace riscv_dwarf;
// clang-format off
-// I suppose EHFrame and DWARF are the same.
+// Assuming register numbers seen in eh_frame and DWARF to be the same.
#define KIND_HELPER(reg, generic_kind) \
{ \
riscv_dwarf::dwarf_##reg, riscv_dwarf::dwarf_##reg, generic_kind, \
- LLDB_INVALID_REGNUM, reg##_riscv \
+ LLDB_INVALID_REGNUM, reg##_riscv \
}
-// Generates register kinds array for vector registers
+// Generates RegisterInfo::kinds for GPRs.
#define GPR32_KIND(reg, generic_kind) KIND_HELPER(reg, generic_kind)
-// FPR register kinds array for vector registers
+// Generates RegisterInfo::kinds for FPRs.
#define FPR32_KIND(reg, generic_kind) KIND_HELPER(reg, generic_kind)
-// VPR register kinds array for vector registers
+// Generates RegisterInfo::kinds for VPRs.
#define VPR_KIND(reg, generic_kind) KIND_HELPER(reg, generic_kind)
-// Defines a 32-bit general purpose register
+// Generates RegisterInfo::kinds for CSRs.
+#define CSR_KIND(reg, generic_kind) KIND_HELPER(reg, generic_kind)
+
+// Defines a 32-bit GPR.
#define DEFINE_GPR32(reg, generic_kind) DEFINE_GPR32_ALT(reg, reg, generic_kind)
-// Defines a 32-bit general purpose register
+// Defines a 32-bit GPR.
#define DEFINE_GPR32_ALT(reg, alt, generic_kind) \
{ \
#reg, #alt, 4, GPR_OFFSET(gpr_##reg##_riscv - gpr_first_riscv), \
- lldb::eEncodingUint, lldb::eFormatHex, \
- GPR32_KIND(gpr_##reg, generic_kind), nullptr, nullptr, nullptr, \
+ lldb::eEncodingUint, lldb::eFormatHex, \
+ GPR32_KIND(gpr_##reg, generic_kind), nullptr, nullptr, nullptr, \
}
-#define DEFINE_FPR32(reg, generic_kind) DEFINE_FPR32_ALT(reg, reg, generic_kind)
-
-#define DEFINE_FPR32_ALT(reg, alt, generic_kind) DEFINE_FPR_ALT(reg, alt, 4, generic_kind)
+// Defines a 32-bit FPR.
+#define DEFINE_FPR32_ALT(reg, alt, generic_kind) \
+ DEFINE_FPR_ALT(reg, alt, 8, generic_kind)
+// Defines a 32-bit FPR.
#define DEFINE_FPR_ALT(reg, alt, size, generic_kind) \
{ \
#reg, #alt, size, FPR_OFFSET(fpr_##reg##_riscv - fpr_first_riscv), \
- lldb::eEncodingUint, lldb::eFormatHex, \
- FPR32_KIND(fpr_##reg, generic_kind), nullptr, nullptr, nullptr, \
+ lldb::eEncodingIEEE754, lldb::eFormatHex, \
+ FPR32_KIND(fpr_##reg, generic_kind), nullptr, nullptr, nullptr, \
}
+// Defines a 32-bit VPR.
#define DEFINE_VPR(reg, generic_kind) DEFINE_VPR_ALT(reg, reg, generic_kind)
-// Defines a scalable vector register, with default size 128 bits
-// The byte offset 0 is a placeholder, which should be corrected at runtime.
+// Defines a scalable vector register with default size of 128 bits.
+// The byte offset of 0 is a placeholder and should be corrected at runtime.
+// Defines a 32-bit VPR.
#define DEFINE_VPR_ALT(reg, alt, generic_kind) \
{ \
#reg, #alt, 16, 0, lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, \
- VPR_KIND(vpr_##reg, generic_kind), nullptr, nullptr, nullptr \
+ VPR_KIND(vpr_##reg, generic_kind), nullptr, nullptr, nullptr \
+ }
+
+// Defines a 32-bit CSR.
+#define DEFINE_CSR32(reg, generic_kind) DEFINE_CSR32_ALT(reg, reg, generic_kind)
+
+// Defines a 32-bit CSR.
+#define DEFINE_CSR32_ALT(reg, alt, generic_kind) \
+ { \
+ #reg, #alt, 4, 0, lldb::eEncodingUint, lldb::eFormatHex, \
+ CSR_KIND(csr_##reg, generic_kind), nullptr, nullptr, nullptr \
}
// clang-format on
@@ -182,4 +203,4193 @@ static lldb_private::RegisterInfo g_register_infos_riscv32_le[] = {
DEFINE_VPR(v31, LLDB_INVALID_REGNUM),
};
+static lldb_private::RegisterInfo g_register_infos_riscv32_gpr[] = {
+ DEFINE_GPR32(pc, LLDB_REGNUM_GENERIC_PC),
+ DEFINE_GPR32_ALT(ra, x1, LLDB_REGNUM_GENERIC_RA),
+ DEFINE_GPR32_ALT(sp, x2, LLDB_REGNUM_GENERIC_SP),
+ DEFINE_GPR32_ALT(gp, x3, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(tp, x4, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(t0, x5, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(t1, x6, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(t2, x7, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(fp, x8, LLDB_REGNUM_GENERIC_FP),
+ DEFINE_GPR32_ALT(s1, x9, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(a0, x10, LLDB_REGNUM_GENERIC_ARG1),
+ DEFINE_GPR32_ALT(a1, x11, LLDB_REGNUM_GENERIC_ARG2),
+ DEFINE_GPR32_ALT(a2, x12, LLDB_REGNUM_GENERIC_ARG3),
+ DEFINE_GPR32_ALT(a3, x13, LLDB_REGNUM_GENERIC_ARG4),
+ DEFINE_GPR32_ALT(a4, x14, LLDB_REGNUM_GENERIC_ARG5),
+ DEFINE_GPR32_ALT(a5, x15, LLDB_REGNUM_GENERIC_ARG6),
+ DEFINE_GPR32_ALT(a6, x16, LLDB_REGNUM_GENERIC_ARG7),
+ DEFINE_GPR32_ALT(a7, x17, LLDB_REGNUM_GENERIC_ARG8),
+ DEFINE_GPR32_ALT(s2, x18, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(s3, x19, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(s4, x20, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(s5, x21, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(s6, x22, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(s7, x23, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(s8, x24, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(s9, x25, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(s10, x26, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(s11, x27, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(t3, x28, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(t4, x29, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(t5, x30, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(t6, x31, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(zero, x0, LLDB_INVALID_REGNUM),
+};
+
+static lldb_private::RegisterInfo g_register_infos_riscv32_fpr[] = {
+ DEFINE_FPR32_ALT(ft0, f0, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(ft1, f1, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(ft2, f2, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(ft3, f3, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(ft4, f4, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(ft5, f5, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(ft6, f6, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(ft7, f7, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fs0, f8, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fs1, f9, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fa0, f10, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fa1, f11, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fa2, f12, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fa3, f13, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fa4, f14, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fa5, f15, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fa6, f16, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fa7, f17, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fs2, f18, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fs3, f19, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fs4, f20, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fs5, f21, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fs6, f22, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fs7, f23, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fs8, f24, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fs9, f25, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fs10, f26, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fs11, f27, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(ft8, f28, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(ft9, f29, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(ft10, f30, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(ft11, f31, LLDB_INVALID_REGNUM),
+};
+
+static lldb_private::RegisterInfo g_register_infos_riscv32_vpr[] = {
+ DEFINE_VPR(v0, LLDB_INVALID_REGNUM), DEFINE_VPR(v1, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v2, LLDB_INVALID_REGNUM), DEFINE_VPR(v3, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v4, LLDB_INVALID_REGNUM), DEFINE_VPR(v5, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v6, LLDB_INVALID_REGNUM), DEFINE_VPR(v7, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v8, LLDB_INVALID_REGNUM), DEFINE_VPR(v9, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v10, LLDB_INVALID_REGNUM), DEFINE_VPR(v11, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v12, LLDB_INVALID_REGNUM), DEFINE_VPR(v13, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v14, LLDB_INVALID_REGNUM), DEFINE_VPR(v15, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v16, LLDB_INVALID_REGNUM), DEFINE_VPR(v17, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v18, LLDB_INVALID_REGNUM), DEFINE_VPR(v19, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v20, LLDB_INVALID_REGNUM), DEFINE_VPR(v21, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v22, LLDB_INVALID_REGNUM), DEFINE_VPR(v23, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v24, LLDB_INVALID_REGNUM), DEFINE_VPR(v25, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v26, LLDB_INVALID_REGNUM), DEFINE_VPR(v27, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v28, LLDB_INVALID_REGNUM), DEFINE_VPR(v29, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v30, LLDB_INVALID_REGNUM), DEFINE_VPR(v31, LLDB_INVALID_REGNUM),
+};
+
+static lldb_private::RegisterInfo g_register_infos_riscv32_csr[] = {
+ DEFINE_CSR32(0, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(fflags, 1, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(frm, 2, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(fcsr, 3, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(5, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(6, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(7, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(vstart, 8, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(vxsat, 9, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(vxrm, 10, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(11, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(12, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(13, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(14, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(vcsr, 15, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(16, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(17, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(18, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(19, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(20, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(21, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(22, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(23, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(24, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(25, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(26, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(27, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(28, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(29, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(30, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(31, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(32, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(33, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(34, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(35, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(36, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(37, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(38, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(39, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(40, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(41, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(42, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(43, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(44, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(45, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(46, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(47, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(48, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(49, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(50, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(51, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(52, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(53, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(54, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(55, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(56, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(57, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(58, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(59, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(60, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(61, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(62, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(63, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(64, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(65, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(66, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(67, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(68, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(69, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(70, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(71, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(72, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(73, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(74, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(75, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(76, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(77, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(78, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(79, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(80, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(81, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(82, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(83, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(84, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(85, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(86, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(87, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(88, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(89, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(90, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(91, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(92, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(93, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(94, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(95, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(96, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(97, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(98, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(99, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(100, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(101, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(102, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(103, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(104, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(105, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(106, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(107, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(108, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(109, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(110, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(111, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(112, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(113, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(114, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(115, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(116, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(117, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(118, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(119, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(120, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(121, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(122, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(123, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(124, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(125, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(126, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(127, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(128, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(129, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(130, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(131, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(132, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(133, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(134, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(135, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(136, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(137, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(138, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(139, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(140, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(141, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(142, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(143, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(144, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(145, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(146, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(147, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(148, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(149, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(150, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(151, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(152, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(153, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(154, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(155, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(156, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(157, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(158, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(159, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(160, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(161, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(162, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(163, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(164, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(165, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(166, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(167, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(168, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(169, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(170, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(171, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(172, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(173, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(174, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(175, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(176, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(177, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(178, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(179, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(180, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(181, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(182, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(183, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(184, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(185, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(186, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(187, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(188, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(189, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(190, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(191, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(192, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(193, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(194, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(195, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(196, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(197, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(198, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(199, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(200, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(201, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(202, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(203, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(204, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(205, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(206, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(207, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(208, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(209, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(210, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(211, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(212, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(213, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(214, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(215, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(216, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(217, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(218, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(219, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(220, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(221, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(222, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(223, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(224, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(225, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(226, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(227, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(228, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(229, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(230, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(231, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(232, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(233, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(234, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(235, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(236, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(237, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(238, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(239, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(240, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(241, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(242, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(243, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(244, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(245, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(246, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(247, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(248, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(249, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(250, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(251, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(252, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(253, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(254, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(255, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(sstatus, 256, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(257, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(258, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(259, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(sie, 260, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(stvec, 261, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(scounteren, 262, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(263, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(264, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(265, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(senvcfg, 266, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(267, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(sstateen0, 268, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(sstateen1, 269, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(sstateen2, 270, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(sstateen3, 271, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(272, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(273, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(274, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(275, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(276, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(277, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(278, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(279, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(280, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(281, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(282, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(283, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(284, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(285, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(286, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(287, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(scountinhibit, 288, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(289, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(290, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(291, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(292, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(293, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(294, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(295, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(296, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(297, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(298, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(299, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(300, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(301, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(302, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(303, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(304, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(305, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(306, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(307, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(308, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(309, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(310, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(311, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(312, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(313, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(314, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(315, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(316, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(317, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(318, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(319, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(sscratch, 320, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(sepc, 321, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(scause, 322, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(stval, 323, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(sip, 324, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(325, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(326, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(327, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(328, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(329, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(330, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(331, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(332, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(333, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(334, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(335, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(336, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(337, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(338, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(339, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(340, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(341, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(342, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(343, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(344, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(345, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(346, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(347, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(348, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(349, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(350, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(351, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(352, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(353, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(354, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(355, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(356, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(357, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(358, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(359, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(360, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(361, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(362, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(363, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(364, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(365, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(366, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(367, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(368, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(369, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(370, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(371, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(372, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(373, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(374, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(375, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(376, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(377, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(378, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(379, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(380, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(381, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(382, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(383, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(satp, 384, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(385, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(386, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(387, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(388, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(389, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(390, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(391, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(392, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(393, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(394, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(395, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(396, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(397, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(398, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(399, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(400, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(401, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(402, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(403, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(404, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(405, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(406, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(407, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(408, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(409, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(410, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(411, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(412, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(413, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(414, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(415, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(416, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(417, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(418, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(419, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(420, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(421, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(422, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(423, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(424, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(425, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(426, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(427, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(428, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(429, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(430, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(431, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(432, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(433, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(434, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(435, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(436, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(437, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(438, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(439, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(440, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(441, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(442, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(443, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(444, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(445, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(446, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(447, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(448, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(449, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(450, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(451, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(452, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(453, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(454, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(455, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(456, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(457, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(458, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(459, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(460, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(461, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(462, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(463, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(464, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(465, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(466, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(467, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(468, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(469, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(470, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(471, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(472, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(473, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(474, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(475, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(476, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(477, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(478, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(479, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(480, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(481, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(482, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(483, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(484, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(485, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(486, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(487, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(488, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(489, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(490, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(491, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(492, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(493, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(494, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(495, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(496, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(497, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(498, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(499, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(500, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(501, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(502, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(503, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(504, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(505, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(506, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(507, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(508, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(509, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(510, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(511, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(vsstatus, 512, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(513, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(514, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(515, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(vsie, 516, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(vstvec, 517, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(518, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(519, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(520, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(521, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(522, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(523, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(524, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(525, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(526, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(527, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(528, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(529, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(530, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(531, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(532, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(533, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(534, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(535, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(536, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(537, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(538, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(539, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(540, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(541, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(542, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(543, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(544, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(545, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(546, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(547, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(548, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(549, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(550, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(551, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(552, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(553, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(554, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(555, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(556, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(557, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(558, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(559, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(560, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(561, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(562, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(563, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(564, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(565, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(566, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(567, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(568, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(569, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(570, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(571, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(572, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(573, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(574, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(575, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(vsscratch, 576, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(vsepc, 577, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(vscause, 578, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(vstval, 579, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(vsip, 580, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(581, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(582, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(583, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(584, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(585, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(586, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(587, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(588, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(589, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(590, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(591, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(592, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(593, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(594, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(595, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(596, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(597, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(598, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(599, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(600, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(601, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(602, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(603, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(604, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(605, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(606, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(607, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(608, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(609, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(610, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(611, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(612, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(613, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(614, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(615, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(616, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(617, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(618, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(619, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(620, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(621, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(622, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(623, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(624, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(625, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(626, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(627, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(628, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(629, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(630, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(631, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(632, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(633, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(634, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(635, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(636, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(637, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(638, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(639, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(vsatp, 640, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(641, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(642, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(643, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(644, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(645, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(646, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(647, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(648, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(649, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(650, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(651, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(652, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(653, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(654, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(655, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(656, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(657, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(658, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(659, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(660, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(661, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(662, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(663, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(664, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(665, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(666, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(667, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(668, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(669, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(670, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(671, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(672, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(673, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(674, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(675, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(676, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(677, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(678, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(679, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(680, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(681, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(682, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(683, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(684, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(685, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(686, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(687, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(688, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(689, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(690, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(691, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(692, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(693, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(694, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(695, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(696, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(697, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(698, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(699, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(700, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(701, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(702, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(703, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(704, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(705, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(706, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(707, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(708, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(709, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(710, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(711, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(712, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(713, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(714, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(715, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(716, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(717, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(718, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(719, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(720, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(721, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(722, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(723, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(724, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(725, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(726, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(727, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(728, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(729, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(730, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(731, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(732, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(733, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(734, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(735, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(736, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(737, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(738, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(739, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(740, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(741, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(742, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(743, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(744, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(745, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(746, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(747, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(748, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(749, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(750, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(751, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(752, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(753, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(754, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(755, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(756, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(757, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(758, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(759, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(760, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(761, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(762, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(763, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(764, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(765, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(766, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(767, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mstatus, 768, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(misa, 769, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(medeleg, 770, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mideleg, 771, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mie, 772, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mtvec, 773, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mcounteren, 774, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(775, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(776, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(777, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(menvcfg, 778, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(779, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mstateen0, 780, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mstateen1, 781, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mstateen2, 782, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mstateen3, 783, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mstatush, 784, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(785, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(medelegh, 786, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(787, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(788, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(789, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(790, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(791, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(792, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(793, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(menvcfgh, 794, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(795, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mstateen0h, 796, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mstateen1h, 797, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mstateen2h, 798, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mstateen3h, 799, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mcountinhibit, 800, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(801, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(802, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent3, 803, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent4, 804, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent5, 805, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent6, 806, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent7, 807, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent8, 808, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent9, 809, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent10, 810, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent11, 811, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent12, 812, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent13, 813, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent14, 814, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent15, 815, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent16, 816, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent17, 817, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent18, 818, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent19, 819, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent20, 820, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent21, 821, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent22, 822, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent23, 823, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent24, 824, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent25, 825, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent26, 826, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent27, 827, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent28, 828, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent29, 829, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent30, 830, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent31, 831, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mscratch, 832, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mepc, 833, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mcause, 834, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mtval, 835, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mip, 836, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(837, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(838, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(839, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(840, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(841, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mtinst, 842, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mtval2, 843, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(844, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(845, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(846, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(847, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(848, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(849, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(850, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(851, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(852, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(853, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(854, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(855, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(856, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(857, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(858, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(859, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(860, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(861, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(862, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(863, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(864, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(865, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(866, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(867, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(868, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(869, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(870, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(871, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(872, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(873, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(874, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(875, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(876, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(877, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(878, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(879, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(880, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(881, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(882, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(883, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(884, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(885, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(886, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(887, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(888, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(889, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(890, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(891, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(892, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(893, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(894, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(895, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(896, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(897, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(898, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(899, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(900, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(901, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(902, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(903, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(904, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(905, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(906, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(907, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(908, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(909, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(910, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(911, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(912, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(913, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(914, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(915, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(916, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(917, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(918, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(919, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(920, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(921, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(922, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(923, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(924, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(925, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(926, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(927, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpcfg0, 928, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpcfg1, 929, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpcfg2, 930, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpcfg3, 931, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpcfg4, 932, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpcfg5, 933, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpcfg6, 934, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpcfg7, 935, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpcfg8, 936, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpcfg9, 937, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpcfg10, 938, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpcfg11, 939, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpcfg12, 940, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpcfg13, 941, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpcfg14, 942, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpcfg15, 943, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr0, 944, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr1, 945, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr2, 946, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr3, 947, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr4, 948, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr5, 949, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr6, 950, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr7, 951, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr8, 952, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr9, 953, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr10, 954, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr11, 955, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr12, 956, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr13, 957, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr14, 958, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr15, 959, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr16, 960, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr17, 961, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr18, 962, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr19, 963, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr20, 964, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr21, 965, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr22, 966, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr23, 967, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr24, 968, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr25, 969, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr26, 970, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr27, 971, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr28, 972, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr29, 973, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr30, 974, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr31, 975, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr32, 976, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr33, 977, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr34, 978, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr35, 979, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr36, 980, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr37, 981, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr38, 982, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr39, 983, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr40, 984, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr41, 985, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr42, 986, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr43, 987, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr44, 988, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr45, 989, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr46, 990, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr47, 991, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr48, 992, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr49, 993, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr50, 994, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr51, 995, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr52, 996, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr53, 997, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr54, 998, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr55, 999, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr56, 1000, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr57, 1001, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr58, 1002, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr59, 1003, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr60, 1004, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr61, 1005, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr62, 1006, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(pmpaddr63, 1007, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1008, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1009, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1010, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1011, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1012, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1013, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1014, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1015, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1016, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1017, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1018, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1019, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1020, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1021, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1022, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1023, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1024, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1025, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1026, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1027, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1028, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1029, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1030, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1031, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1032, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1033, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1034, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1035, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1036, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1037, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1038, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1039, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1040, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1041, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1042, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1043, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1044, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1045, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1046, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1047, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1048, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1049, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1050, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1051, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1052, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1053, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1054, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1055, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1056, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1057, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1058, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1059, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1060, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1061, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1062, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1063, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1064, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1065, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1066, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1067, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1068, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1069, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1070, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1071, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1072, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1073, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1074, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1075, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1076, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1077, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1078, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1079, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1080, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1081, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1082, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1083, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1084, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1085, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1086, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1087, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1088, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1089, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1090, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1091, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1092, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1093, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1094, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1095, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1096, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1097, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1098, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1099, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1100, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1101, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1102, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1103, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1104, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1105, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1106, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1107, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1108, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1109, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1110, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1111, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1112, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1113, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1114, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1115, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1116, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1117, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1118, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1119, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1120, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1121, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1122, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1123, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1124, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1125, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1126, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1127, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1128, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1129, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1130, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1131, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1132, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1133, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1134, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1135, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1136, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1137, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1138, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1139, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1140, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1141, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1142, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1143, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1144, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1145, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1146, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1147, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1148, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1149, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1150, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1151, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1152, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1153, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1154, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1155, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1156, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1157, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1158, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1159, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1160, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1161, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1162, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1163, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1164, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1165, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1166, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1167, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1168, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1169, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1170, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1171, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1172, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1173, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1174, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1175, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1176, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1177, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1178, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1179, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1180, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1181, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1182, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1183, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1184, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1185, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1186, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1187, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1188, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1189, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1190, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1191, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1192, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1193, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1194, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1195, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1196, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1197, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1198, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1199, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1200, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1201, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1202, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1203, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1204, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1205, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1206, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1207, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1208, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1209, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1210, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1211, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1212, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1213, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1214, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1215, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1216, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1217, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1218, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1219, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1220, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1221, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1222, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1223, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1224, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1225, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1226, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1227, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1228, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1229, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1230, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1231, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1232, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1233, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1234, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1235, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1236, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1237, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1238, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1239, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1240, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1241, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1242, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1243, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1244, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1245, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1246, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1247, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1248, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1249, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1250, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1251, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1252, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1253, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1254, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1255, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1256, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1257, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1258, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1259, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1260, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1261, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1262, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1263, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1264, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1265, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1266, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1267, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1268, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1269, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1270, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1271, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1272, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1273, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1274, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1275, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1276, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1277, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1278, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1279, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1280, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1281, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1282, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1283, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1284, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1285, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1286, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1287, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1288, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1289, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1290, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1291, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1292, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1293, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1294, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1295, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1296, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1297, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1298, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1299, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1300, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1301, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1302, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1303, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1304, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1305, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1306, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1307, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1308, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1309, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1310, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1311, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1312, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1313, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1314, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1315, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1316, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1317, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1318, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1319, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1320, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1321, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1322, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1323, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1324, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1325, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1326, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1327, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1328, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1329, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1330, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1331, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1332, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1333, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1334, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1335, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1336, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1337, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1338, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1339, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1340, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1341, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1342, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1343, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1344, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1345, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1346, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1347, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1348, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1349, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1350, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1351, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1352, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1353, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1354, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1355, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1356, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1357, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1358, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1359, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1360, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1361, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1362, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1363, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1364, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1365, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1366, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1367, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1368, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1369, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1370, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1371, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1372, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1373, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1374, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1375, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1376, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1377, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1378, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1379, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1380, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1381, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1382, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1383, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1384, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1385, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1386, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1387, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1388, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1389, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1390, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1391, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1392, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1393, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1394, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1395, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1396, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1397, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1398, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1399, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1400, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1401, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1402, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1403, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1404, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1405, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1406, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1407, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1408, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1409, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1410, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1411, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1412, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1413, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1414, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1415, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1416, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1417, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1418, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1419, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1420, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1421, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1422, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1423, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1424, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1425, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1426, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1427, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1428, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1429, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1430, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1431, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1432, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1433, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1434, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1435, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1436, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1437, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1438, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1439, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1440, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1441, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1442, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1443, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1444, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1445, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1446, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1447, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(scontext, 1448, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1449, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1450, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1451, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1452, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1453, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1454, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1455, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1456, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1457, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1458, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1459, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1460, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1461, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1462, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1463, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1464, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1465, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1466, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1467, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1468, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1469, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1470, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1471, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1472, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1473, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1474, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1475, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1476, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1477, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1478, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1479, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1480, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1481, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1482, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1483, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1484, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1485, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1486, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1487, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1488, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1489, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1490, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1491, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1492, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1493, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1494, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1495, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1496, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1497, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1498, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1499, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1500, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1501, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1502, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1503, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1504, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1505, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1506, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1507, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1508, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1509, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1510, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1511, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1512, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1513, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1514, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1515, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1516, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1517, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1518, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1519, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1520, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1521, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1522, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1523, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1524, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1525, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1526, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1527, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1528, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1529, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1530, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1531, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1532, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1533, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1534, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1535, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hstatus, 1536, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1537, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hedeleg, 1538, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hideleg, 1539, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hie, 1540, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(htimedelta, 1541, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hcounteren, 1542, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hgeie, 1543, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1544, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1545, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(henvcfg, 1546, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1547, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hstateen0, 1548, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hstateen1, 1549, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hstateen2, 1550, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hstateen3, 1551, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1552, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1553, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hedelegh, 1554, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1555, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1556, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(htimedeltah, 1557, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1558, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1559, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1560, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1561, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(henvcfgh, 1562, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1563, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hstateen0h, 1564, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hstateen1h, 1565, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hstateen2h, 1566, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hstateen3h, 1567, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1568, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1569, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1570, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1571, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1572, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1573, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1574, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1575, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1576, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1577, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1578, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1579, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1580, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1581, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1582, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1583, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1584, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1585, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1586, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1587, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1588, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1589, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1590, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1591, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1592, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1593, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1594, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1595, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1596, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1597, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1598, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1599, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1600, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1601, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1602, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(htval, 1603, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hip, 1604, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hvip, 1605, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1606, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1607, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1608, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1609, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(htinst, 1610, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1611, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1612, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1613, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1614, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1615, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1616, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1617, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1618, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1619, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1620, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1621, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1622, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1623, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1624, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1625, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1626, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1627, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1628, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1629, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1630, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1631, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1632, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1633, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1634, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1635, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1636, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1637, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1638, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1639, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1640, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1641, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1642, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1643, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1644, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1645, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1646, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1647, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1648, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1649, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1650, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1651, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1652, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1653, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1654, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1655, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1656, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1657, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1658, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1659, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1660, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1661, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1662, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1663, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hgatp, 1664, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1665, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1666, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1667, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1668, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1669, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1670, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1671, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1672, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1673, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1674, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1675, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1676, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1677, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1678, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1679, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1680, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1681, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1682, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1683, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1684, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1685, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1686, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1687, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1688, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1689, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1690, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1691, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1692, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1693, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1694, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1695, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1696, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1697, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1698, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1699, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1700, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1701, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1702, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1703, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hcontext, 1704, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1705, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1706, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1707, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1708, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1709, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1710, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1711, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1712, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1713, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1714, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1715, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1716, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1717, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1718, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1719, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1720, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1721, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1722, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1723, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1724, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1725, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1726, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1727, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1728, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1729, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1730, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1731, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1732, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1733, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1734, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1735, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1736, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1737, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1738, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1739, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1740, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1741, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1742, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1743, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1744, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1745, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1746, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1747, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1748, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1749, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1750, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1751, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1752, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1753, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1754, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1755, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1756, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1757, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1758, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1759, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1760, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1761, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1762, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1763, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1764, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1765, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1766, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1767, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1768, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1769, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1770, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1771, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1772, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1773, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1774, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1775, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1776, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1777, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1778, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1779, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1780, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1781, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1782, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1783, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1784, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1785, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1786, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1787, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1788, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1789, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1790, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1791, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1792, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1793, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1794, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1795, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1796, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1797, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1798, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1799, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1800, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1801, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1802, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1803, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1804, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1805, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1806, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1807, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1808, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1809, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1810, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1811, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1812, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1813, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1814, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1815, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1816, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1817, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1818, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1819, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1820, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1821, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1822, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1823, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1824, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1825, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1826, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent3h, 1827, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent4h, 1828, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent5h, 1829, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent6h, 1830, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent7h, 1831, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent8h, 1832, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent9h, 1833, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent10h, 1834, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent11h, 1835, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent12h, 1836, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent13h, 1837, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent14h, 1838, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent15h, 1839, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent16h, 1840, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent17h, 1841, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent18h, 1842, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent19h, 1843, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent20h, 1844, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent21h, 1845, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent22h, 1846, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent23h, 1847, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent24h, 1848, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent25h, 1849, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent26h, 1850, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent27h, 1851, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent28h, 1852, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent29h, 1853, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent30h, 1854, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmevent31h, 1855, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mnscratch, 1856, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mnepc, 1857, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mncause, 1858, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1859, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mnstatus, 1860, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1861, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1862, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mseccfg, 1863, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1864, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1865, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1866, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1867, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1868, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1869, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1870, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1871, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1872, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1873, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1874, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1875, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1876, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1877, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1878, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mseccfgh, 1879, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1880, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1881, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1882, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1883, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1884, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1885, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1886, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1887, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1888, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1889, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1890, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1891, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1892, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1893, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1894, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1895, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1896, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1897, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1898, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1899, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1900, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1901, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1902, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1903, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1904, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1905, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1906, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1907, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1908, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1909, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1910, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1911, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1912, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1913, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1914, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1915, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1916, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1917, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1918, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1919, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1920, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1921, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1922, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1923, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1924, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1925, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1926, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1927, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1928, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1929, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1930, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1931, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1932, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1933, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1934, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1935, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1936, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1937, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1938, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1939, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1940, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1941, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1942, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1943, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1944, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1945, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1946, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1947, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1948, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1949, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1950, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1951, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(tselect, 1952, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(tdata1, 1953, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(tdata2, 1954, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(tdata3, 1955, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1956, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1957, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1958, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1959, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mcontext, 1960, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1961, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1962, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1963, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1964, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1965, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1966, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1967, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(dcsr, 1968, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(dpc, 1969, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(dscratch0, 1970, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(dscratch1, 1971, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1972, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1973, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1974, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1975, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1976, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1977, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1978, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1979, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1980, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1981, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1982, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1983, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1984, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1985, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1986, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1987, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1988, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1989, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1990, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1991, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1992, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1993, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1994, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1995, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1996, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1997, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1998, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(1999, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2000, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2001, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2002, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2003, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2004, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2005, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2006, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2007, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2008, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2009, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2010, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2011, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2012, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2013, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2014, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2015, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2016, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2017, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2018, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2019, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2020, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2021, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2022, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2023, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2024, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2025, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2026, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2027, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2028, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2029, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2030, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2031, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2032, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2033, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2034, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2035, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2036, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2037, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2038, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2039, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2040, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2041, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2042, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2043, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2044, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2045, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2046, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2047, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2048, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2049, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2050, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2051, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2052, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2053, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2054, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2055, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2056, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2057, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2058, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2059, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2060, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2061, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2062, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2063, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2064, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2065, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2066, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2067, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2068, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2069, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2070, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2071, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2072, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2073, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2074, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2075, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2076, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2077, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2078, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2079, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2080, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2081, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2082, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2083, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2084, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2085, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2086, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2087, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2088, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2089, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2090, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2091, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2092, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2093, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2094, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2095, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2096, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2097, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2098, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2099, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2100, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2101, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2102, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2103, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2104, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2105, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2106, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2107, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2108, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2109, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2110, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2111, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2112, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2113, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2114, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2115, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2116, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2117, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2118, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2119, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2120, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2121, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2122, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2123, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2124, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2125, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2126, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2127, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2128, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2129, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2130, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2131, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2132, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2133, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2134, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2135, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2136, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2137, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2138, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2139, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2140, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2141, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2142, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2143, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2144, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2145, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2146, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2147, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2148, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2149, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2150, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2151, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2152, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2153, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2154, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2155, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2156, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2157, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2158, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2159, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2160, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2161, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2162, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2163, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2164, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2165, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2166, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2167, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2168, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2169, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2170, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2171, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2172, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2173, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2174, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2175, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2176, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2177, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2178, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2179, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2180, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2181, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2182, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2183, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2184, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2185, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2186, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2187, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2188, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2189, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2190, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2191, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2192, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2193, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2194, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2195, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2196, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2197, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2198, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2199, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2200, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2201, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2202, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2203, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2204, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2205, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2206, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2207, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2208, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2209, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2210, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2211, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2212, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2213, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2214, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2215, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2216, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2217, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2218, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2219, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2220, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2221, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2222, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2223, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2224, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2225, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2226, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2227, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2228, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2229, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2230, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2231, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2232, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2233, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2234, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2235, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2236, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2237, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2238, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2239, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2240, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2241, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2242, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2243, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2244, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2245, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2246, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2247, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2248, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2249, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2250, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2251, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2252, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2253, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2254, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2255, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2256, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2257, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2258, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2259, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2260, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2261, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2262, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2263, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2264, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2265, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2266, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2267, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2268, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2269, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2270, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2271, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2272, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2273, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2274, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2275, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2276, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2277, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2278, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2279, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2280, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2281, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2282, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2283, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2284, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2285, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2286, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2287, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2288, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2289, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2290, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2291, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2292, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2293, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2294, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2295, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2296, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2297, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2298, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2299, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2300, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2301, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2302, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2303, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2304, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2305, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2306, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2307, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2308, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2309, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2310, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2311, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2312, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2313, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2314, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2315, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2316, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2317, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2318, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2319, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2320, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2321, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2322, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2323, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2324, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2325, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2326, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2327, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2328, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2329, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2330, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2331, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2332, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2333, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2334, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2335, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2336, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2337, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2338, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2339, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2340, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2341, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2342, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2343, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2344, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2345, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2346, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2347, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2348, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2349, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2350, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2351, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2352, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2353, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2354, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2355, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2356, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2357, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2358, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2359, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2360, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2361, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2362, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2363, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2364, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2365, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2366, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2367, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2368, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2369, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2370, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2371, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2372, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2373, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2374, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2375, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2376, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2377, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2378, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2379, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2380, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2381, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2382, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2383, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2384, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2385, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2386, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2387, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2388, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2389, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2390, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2391, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2392, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2393, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2394, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2395, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2396, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2397, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2398, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2399, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2400, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2401, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2402, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2403, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2404, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2405, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2406, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2407, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2408, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2409, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2410, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2411, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2412, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2413, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2414, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2415, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2416, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2417, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2418, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2419, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2420, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2421, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2422, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2423, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2424, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2425, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2426, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2427, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2428, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2429, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2430, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2431, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2432, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2433, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2434, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2435, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2436, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2437, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2438, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2439, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2440, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2441, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2442, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2443, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2444, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2445, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2446, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2447, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2448, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2449, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2450, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2451, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2452, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2453, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2454, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2455, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2456, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2457, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2458, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2459, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2460, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2461, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2462, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2463, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2464, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2465, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2466, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2467, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2468, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2469, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2470, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2471, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2472, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2473, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2474, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2475, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2476, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2477, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2478, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2479, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2480, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2481, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2482, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2483, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2484, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2485, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2486, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2487, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2488, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2489, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2490, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2491, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2492, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2493, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2494, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2495, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2496, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2497, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2498, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2499, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2500, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2501, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2502, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2503, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2504, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2505, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2506, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2507, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2508, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2509, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2510, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2511, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2512, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2513, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2514, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2515, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2516, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2517, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2518, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2519, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2520, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2521, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2522, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2523, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2524, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2525, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2526, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2527, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2528, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2529, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2530, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2531, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2532, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2533, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2534, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2535, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2536, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2537, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2538, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2539, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2540, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2541, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2542, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2543, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2544, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2545, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2546, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2547, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2548, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2549, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2550, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2551, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2552, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2553, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2554, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2555, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2556, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2557, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2558, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2559, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2560, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2561, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2562, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2563, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2564, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2565, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2566, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2567, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2568, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2569, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2570, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2571, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2572, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2573, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2574, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2575, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2576, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2577, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2578, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2579, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2580, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2581, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2582, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2583, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2584, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2585, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2586, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2587, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2588, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2589, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2590, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2591, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2592, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2593, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2594, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2595, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2596, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2597, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2598, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2599, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2600, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2601, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2602, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2603, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2604, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2605, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2606, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2607, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2608, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2609, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2610, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2611, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2612, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2613, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2614, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2615, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2616, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2617, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2618, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2619, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2620, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2621, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2622, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2623, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2624, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2625, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2626, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2627, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2628, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2629, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2630, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2631, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2632, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2633, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2634, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2635, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2636, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2637, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2638, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2639, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2640, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2641, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2642, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2643, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2644, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2645, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2646, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2647, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2648, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2649, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2650, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2651, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2652, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2653, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2654, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2655, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2656, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2657, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2658, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2659, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2660, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2661, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2662, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2663, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2664, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2665, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2666, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2667, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2668, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2669, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2670, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2671, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2672, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2673, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2674, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2675, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2676, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2677, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2678, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2679, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2680, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2681, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2682, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2683, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2684, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2685, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2686, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2687, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2688, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2689, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2690, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2691, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2692, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2693, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2694, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2695, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2696, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2697, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2698, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2699, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2700, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2701, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2702, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2703, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2704, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2705, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2706, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2707, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2708, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2709, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2710, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2711, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2712, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2713, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2714, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2715, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2716, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2717, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2718, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2719, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2720, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2721, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2722, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2723, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2724, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2725, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2726, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2727, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2728, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2729, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2730, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2731, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2732, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2733, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2734, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2735, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2736, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2737, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2738, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2739, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2740, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2741, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2742, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2743, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2744, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2745, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2746, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2747, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2748, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2749, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2750, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2751, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2752, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2753, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2754, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2755, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2756, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2757, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2758, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2759, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2760, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2761, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2762, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2763, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2764, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2765, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2766, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2767, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2768, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2769, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2770, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2771, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2772, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2773, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2774, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2775, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2776, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2777, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2778, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2779, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2780, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2781, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2782, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2783, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2784, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2785, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2786, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2787, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2788, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2789, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2790, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2791, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2792, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2793, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2794, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2795, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2796, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2797, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2798, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2799, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2800, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2801, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2802, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2803, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2804, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2805, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2806, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2807, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2808, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2809, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2810, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2811, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2812, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2813, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2814, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2815, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mcycle, 2816, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2817, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(minstret, 2818, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter3, 2819, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter4, 2820, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter5, 2821, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter6, 2822, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter7, 2823, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter8, 2824, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter9, 2825, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter10, 2826, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter11, 2827, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter12, 2828, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter13, 2829, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter14, 2830, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter15, 2831, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter16, 2832, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter17, 2833, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter18, 2834, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter19, 2835, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter20, 2836, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter21, 2837, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter22, 2838, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter23, 2839, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter24, 2840, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter25, 2841, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter26, 2842, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter27, 2843, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter28, 2844, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter29, 2845, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter30, 2846, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter31, 2847, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2848, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2849, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2850, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2851, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2852, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2853, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2854, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2855, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2856, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2857, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2858, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2859, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2860, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2861, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2862, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2863, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2864, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2865, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2866, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2867, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2868, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2869, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2870, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2871, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2872, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2873, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2874, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2875, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2876, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2877, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2878, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2879, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2880, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2881, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2882, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2883, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2884, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2885, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2886, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2887, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2888, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2889, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2890, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2891, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2892, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2893, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2894, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2895, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2896, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2897, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2898, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2899, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2900, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2901, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2902, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2903, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2904, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2905, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2906, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2907, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2908, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2909, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2910, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2911, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2912, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2913, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2914, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2915, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2916, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2917, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2918, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2919, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2920, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2921, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2922, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2923, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2924, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2925, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2926, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2927, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2928, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2929, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2930, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2931, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2932, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2933, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2934, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2935, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2936, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2937, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2938, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2939, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2940, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2941, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2942, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2943, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mcycleh, 2944, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2945, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(minstreth, 2946, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter3h, 2947, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter4h, 2948, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter5h, 2949, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter6h, 2950, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter7h, 2951, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter8h, 2952, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter9h, 2953, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter10h, 2954, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter11h, 2955, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter12h, 2956, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter13h, 2957, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter14h, 2958, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter15h, 2959, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter16h, 2960, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter17h, 2961, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter18h, 2962, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter19h, 2963, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter20h, 2964, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter21h, 2965, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter22h, 2966, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter23h, 2967, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter24h, 2968, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter25h, 2969, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter26h, 2970, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter27h, 2971, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter28h, 2972, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter29h, 2973, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter30h, 2974, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhpmcounter31h, 2975, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2976, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2977, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2978, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2979, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2980, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2981, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2982, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2983, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2984, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2985, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2986, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2987, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2988, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2989, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2990, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2991, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2992, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2993, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2994, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2995, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2996, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2997, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2998, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(2999, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3000, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3001, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3002, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3003, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3004, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3005, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3006, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3007, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3008, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3009, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3010, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3011, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3012, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3013, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3014, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3015, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3016, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3017, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3018, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3019, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3020, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3021, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3022, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3023, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3024, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3025, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3026, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3027, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3028, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3029, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3030, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3031, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3032, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3033, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3034, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3035, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3036, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3037, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3038, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3039, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3040, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3041, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3042, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3043, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3044, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3045, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3046, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3047, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3048, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3049, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3050, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3051, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3052, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3053, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3054, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3055, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3056, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3057, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3058, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3059, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3060, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3061, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3062, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3063, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3064, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3065, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3066, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3067, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3068, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3069, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3070, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3071, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(cycle, 3072, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(time, 3073, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(instret, 3074, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter3, 3075, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter4, 3076, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter5, 3077, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter6, 3078, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter7, 3079, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter8, 3080, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter9, 3081, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter10, 3082, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter11, 3083, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter12, 3084, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter13, 3085, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter14, 3086, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter15, 3087, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter16, 3088, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter17, 3089, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter18, 3090, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter19, 3091, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter20, 3092, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter21, 3093, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter22, 3094, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter23, 3095, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter24, 3096, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter25, 3097, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter26, 3098, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter27, 3099, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter28, 3100, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter29, 3101, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter30, 3102, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter31, 3103, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(vl, 3104, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(vtype, 3105, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(vlenb, 3106, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3107, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3108, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3109, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3110, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3111, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3112, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3113, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3114, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3115, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3116, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3117, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3118, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3119, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3120, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3121, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3122, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3123, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3124, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3125, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3126, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3127, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3128, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3129, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3130, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3131, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3132, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3133, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3134, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3135, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3136, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3137, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3138, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3139, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3140, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3141, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3142, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3143, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3144, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3145, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3146, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3147, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3148, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3149, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3150, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3151, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3152, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3153, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3154, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3155, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3156, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3157, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3158, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3159, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3160, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3161, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3162, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3163, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3164, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3165, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3166, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3167, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3168, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3169, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3170, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3171, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3172, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3173, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3174, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3175, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3176, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3177, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3178, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3179, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3180, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3181, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3182, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3183, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3184, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3185, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3186, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3187, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3188, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3189, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3190, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3191, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3192, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3193, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3194, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3195, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3196, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3197, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3198, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3199, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(cycleh, 3200, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(timeh, 3201, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(instreth, 3202, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter3h, 3203, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter4h, 3204, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter5h, 3205, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter6h, 3206, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter7h, 3207, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter8h, 3208, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter9h, 3209, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter10h, 3210, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter11h, 3211, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter12h, 3212, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter13h, 3213, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter14h, 3214, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter15h, 3215, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter16h, 3216, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter17h, 3217, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter18h, 3218, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter19h, 3219, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter20h, 3220, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter21h, 3221, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter22h, 3222, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter23h, 3223, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter24h, 3224, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter25h, 3225, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter26h, 3226, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter27h, 3227, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter28h, 3228, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter29h, 3229, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter30h, 3230, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hpmcounter31h, 3231, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3232, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3233, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3234, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3235, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3236, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3237, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3238, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3239, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3240, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3241, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3242, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3243, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3244, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3245, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3246, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3247, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3248, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3249, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3250, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3251, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3252, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3253, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3254, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3255, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3256, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3257, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3258, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3259, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3260, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3261, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3262, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3263, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3264, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3265, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3266, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3267, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3268, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3269, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3270, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3271, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3272, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3273, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3274, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3275, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3276, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3277, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3278, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3279, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3280, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3281, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3282, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3283, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3284, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3285, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3286, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3287, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3288, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3289, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3290, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3291, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3292, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3293, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3294, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3295, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3296, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3297, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3298, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3299, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3300, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3301, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3302, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3303, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3304, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3305, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3306, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3307, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3308, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3309, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3310, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3311, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3312, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3313, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3314, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3315, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3316, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3317, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3318, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3319, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3320, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3321, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3322, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3323, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3324, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3325, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3326, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3327, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3328, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3329, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3330, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3331, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3332, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3333, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3334, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3335, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3336, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3337, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3338, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3339, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3340, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3341, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3342, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3343, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3344, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3345, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3346, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3347, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3348, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3349, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3350, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3351, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3352, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3353, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3354, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3355, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3356, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3357, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3358, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3359, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3360, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3361, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3362, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3363, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3364, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3365, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3366, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3367, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3368, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3369, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3370, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3371, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3372, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3373, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3374, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3375, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3376, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3377, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3378, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3379, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3380, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3381, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3382, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3383, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3384, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3385, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3386, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3387, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3388, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3389, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3390, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3391, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3392, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3393, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3394, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3395, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3396, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3397, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3398, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3399, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3400, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3401, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3402, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3403, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3404, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3405, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3406, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3407, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3408, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3409, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3410, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3411, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3412, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3413, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3414, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3415, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3416, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3417, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3418, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3419, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3420, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3421, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3422, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3423, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3424, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3425, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3426, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3427, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3428, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3429, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3430, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3431, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3432, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3433, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3434, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3435, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3436, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3437, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3438, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3439, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3440, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3441, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3442, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3443, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3444, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3445, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3446, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3447, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3448, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3449, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3450, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3451, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3452, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3453, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3454, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3455, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3456, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3457, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3458, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3459, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3460, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3461, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3462, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3463, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3464, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3465, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3466, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3467, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3468, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3469, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3470, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3471, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3472, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3473, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3474, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3475, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3476, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3477, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3478, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3479, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3480, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3481, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3482, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3483, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3484, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3485, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3486, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3487, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(scountovf, 3488, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3489, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3490, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3491, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3492, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3493, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3494, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3495, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3496, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3497, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3498, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3499, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3500, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3501, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3502, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3503, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3504, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3505, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3506, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3507, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3508, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3509, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3510, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3511, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3512, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3513, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3514, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3515, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3516, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3517, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3518, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3519, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3520, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3521, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3522, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3523, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3524, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3525, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3526, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3527, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3528, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3529, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3530, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3531, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3532, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3533, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3534, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3535, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3536, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3537, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3538, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3539, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3540, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3541, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3542, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3543, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3544, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3545, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3546, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3547, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3548, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3549, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3550, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3551, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3552, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3553, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3554, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3555, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3556, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3557, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3558, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3559, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3560, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3561, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3562, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3563, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3564, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3565, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3566, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3567, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3568, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3569, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3570, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3571, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3572, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3573, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3574, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3575, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3576, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3577, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3578, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3579, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3580, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3581, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3582, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3583, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3584, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3585, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3586, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3587, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3588, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3589, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3590, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3591, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3592, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3593, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3594, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3595, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3596, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3597, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3598, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3599, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3600, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3601, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(hgeip, 3602, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3603, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3604, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3605, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3606, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3607, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3608, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3609, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3610, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3611, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3612, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3613, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3614, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3615, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3616, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3617, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3618, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3619, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3620, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3621, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3622, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3623, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3624, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3625, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3626, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3627, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3628, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3629, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3630, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3631, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3632, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3633, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3634, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3635, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3636, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3637, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3638, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3639, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3640, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3641, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3642, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3643, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3644, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3645, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3646, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3647, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3648, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3649, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3650, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3651, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3652, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3653, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3654, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3655, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3656, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3657, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3658, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3659, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3660, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3661, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3662, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3663, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3664, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3665, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3666, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3667, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3668, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3669, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3670, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3671, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3672, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3673, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3674, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3675, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3676, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3677, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3678, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3679, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3680, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3681, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3682, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3683, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3684, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3685, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3686, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3687, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3688, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3689, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3690, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3691, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3692, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3693, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3694, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3695, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3696, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3697, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3698, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3699, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3700, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3701, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3702, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3703, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3704, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3705, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3706, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3707, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3708, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3709, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3710, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3711, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3712, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3713, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3714, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3715, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3716, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3717, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3718, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3719, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3720, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3721, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3722, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3723, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3724, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3725, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3726, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3727, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3728, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3729, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3730, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3731, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3732, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3733, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3734, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3735, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3736, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3737, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3738, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3739, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3740, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3741, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3742, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3743, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3744, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3745, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3746, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3747, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3748, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3749, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3750, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3751, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3752, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3753, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3754, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3755, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3756, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3757, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3758, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3759, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3760, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3761, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3762, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3763, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3764, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3765, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3766, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3767, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3768, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3769, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3770, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3771, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3772, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3773, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3774, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3775, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3776, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3777, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3778, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3779, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3780, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3781, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3782, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3783, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3784, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3785, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3786, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3787, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3788, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3789, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3790, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3791, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3792, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3793, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3794, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3795, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3796, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3797, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3798, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3799, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3800, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3801, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3802, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3803, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3804, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3805, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3806, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3807, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3808, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3809, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3810, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3811, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3812, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3813, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3814, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3815, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3816, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3817, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3818, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3819, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3820, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3821, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3822, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3823, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3824, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3825, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3826, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3827, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3828, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3829, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3830, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3831, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3832, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3833, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3834, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3835, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3836, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3837, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3838, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3839, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3840, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3841, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3842, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3843, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3844, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3845, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3846, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3847, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3848, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3849, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3850, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3851, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3852, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3853, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3854, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3855, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3856, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mvendorid, 3857, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(marchid, 3858, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mimpid, 3859, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mhartid, 3860, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32_ALT(mconfigptr, 3861, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3862, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3863, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3864, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3865, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3866, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3867, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3868, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3869, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3870, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3871, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3872, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3873, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3874, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3875, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3876, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3877, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3878, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3879, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3880, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3881, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3882, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3883, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3884, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3885, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3886, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3887, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3888, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3889, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3890, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3891, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3892, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3893, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3894, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3895, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3896, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3897, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3898, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3899, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3900, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3901, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3902, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3903, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3904, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3905, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3906, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3907, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3908, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3909, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3910, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3911, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3912, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3913, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3914, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3915, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3916, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3917, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3918, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3919, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3920, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3921, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3922, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3923, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3924, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3925, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3926, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3927, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3928, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3929, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3930, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3931, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3932, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3933, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3934, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3935, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3936, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3937, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3938, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3939, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3940, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3941, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3942, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3943, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3944, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3945, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3946, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3947, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3948, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3949, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3950, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3951, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3952, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3953, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3954, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3955, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3956, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3957, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3958, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3959, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3960, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3961, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3962, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3963, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3964, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3965, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3966, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3967, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3968, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3969, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3970, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3971, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3972, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3973, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3974, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3975, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3976, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3977, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3978, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3979, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3980, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3981, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3982, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3983, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3984, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3985, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3986, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3987, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3988, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3989, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3990, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3991, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3992, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3993, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3994, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3995, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3996, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3997, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3998, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(3999, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4000, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4001, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4002, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4003, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4004, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4005, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4006, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4007, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4008, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4009, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4010, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4011, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4012, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4013, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4014, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4015, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4016, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4017, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4018, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4019, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4020, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4021, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4022, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4023, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4024, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4025, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4026, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4027, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4028, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4029, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4030, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4031, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4032, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4033, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4034, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4035, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4036, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4037, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4038, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4039, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4040, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4041, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4042, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4043, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4044, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4045, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4046, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4047, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4048, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4049, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4050, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4051, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4052, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4053, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4054, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4055, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4056, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4057, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4058, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4059, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4060, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4061, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4062, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4063, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4064, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4065, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4066, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4067, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4068, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4069, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4070, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4071, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4072, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4073, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4074, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4075, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4076, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4077, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4078, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4079, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4080, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4081, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4082, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4083, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4084, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4085, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4086, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4087, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4088, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4089, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4090, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4091, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4092, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4093, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4094, LLDB_INVALID_REGNUM),
+ DEFINE_CSR32(4095, LLDB_INVALID_REGNUM),
+};
+
#endif // DECLARE_REGISTER_INFOS_RISCV32_STRUCT
diff --git a/lldb/source/Plugins/Process/Utility/lldb-riscv-register-enums.h b/lldb/source/Plugins/Process/Utility/lldb-riscv-register-enums.h
index caec313750abb..37d1753575110 100644
--- a/lldb/source/Plugins/Process/Utility/lldb-riscv-register-enums.h
+++ b/lldb/source/Plugins/Process/Utility/lldb-riscv-register-enums.h
@@ -187,6 +187,4479 @@ enum {
vpr_v31_riscv,
vpr_last_riscv = vpr_v31_riscv,
+ csr_first_riscv = 98,
+ csr_0_riscv = csr_first_riscv,
+ csr_1_riscv,
+ csr_2_riscv,
+ csr_3_riscv,
+ csr_4_riscv,
+ csr_5_riscv,
+ csr_6_riscv,
+ csr_7_riscv,
+ csr_8_riscv,
+ csr_9_riscv,
+ csr_10_riscv,
+ csr_11_riscv,
+ csr_12_riscv,
+ csr_13_riscv,
+ csr_14_riscv,
+ csr_15_riscv,
+ csr_16_riscv,
+ csr_17_riscv,
+ csr_18_riscv,
+ csr_19_riscv,
+ csr_20_riscv,
+ csr_21_riscv,
+ csr_22_riscv,
+ csr_23_riscv,
+ csr_24_riscv,
+ csr_25_riscv,
+ csr_26_riscv,
+ csr_27_riscv,
+ csr_28_riscv,
+ csr_29_riscv,
+ csr_30_riscv,
+ csr_31_riscv,
+ csr_32_riscv,
+ csr_33_riscv,
+ csr_34_riscv,
+ csr_35_riscv,
+ csr_36_riscv,
+ csr_37_riscv,
+ csr_38_riscv,
+ csr_39_riscv,
+ csr_40_riscv,
+ csr_41_riscv,
+ csr_42_riscv,
+ csr_43_riscv,
+ csr_44_riscv,
+ csr_45_riscv,
+ csr_46_riscv,
+ csr_47_riscv,
+ csr_48_riscv,
+ csr_49_riscv,
+ csr_50_riscv,
+ csr_51_riscv,
+ csr_52_riscv,
+ csr_53_riscv,
+ csr_54_riscv,
+ csr_55_riscv,
+ csr_56_riscv,
+ csr_57_riscv,
+ csr_58_riscv,
+ csr_59_riscv,
+ csr_60_riscv,
+ csr_61_riscv,
+ csr_62_riscv,
+ csr_63_riscv,
+ csr_64_riscv,
+ csr_65_riscv,
+ csr_66_riscv,
+ csr_67_riscv,
+ csr_68_riscv,
+ csr_69_riscv,
+ csr_70_riscv,
+ csr_71_riscv,
+ csr_72_riscv,
+ csr_73_riscv,
+ csr_74_riscv,
+ csr_75_riscv,
+ csr_76_riscv,
+ csr_77_riscv,
+ csr_78_riscv,
+ csr_79_riscv,
+ csr_80_riscv,
+ csr_81_riscv,
+ csr_82_riscv,
+ csr_83_riscv,
+ csr_84_riscv,
+ csr_85_riscv,
+ csr_86_riscv,
+ csr_87_riscv,
+ csr_88_riscv,
+ csr_89_riscv,
+ csr_90_riscv,
+ csr_91_riscv,
+ csr_92_riscv,
+ csr_93_riscv,
+ csr_94_riscv,
+ csr_95_riscv,
+ csr_96_riscv,
+ csr_97_riscv,
+ csr_98_riscv,
+ csr_99_riscv,
+ csr_100_riscv,
+ csr_101_riscv,
+ csr_102_riscv,
+ csr_103_riscv,
+ csr_104_riscv,
+ csr_105_riscv,
+ csr_106_riscv,
+ csr_107_riscv,
+ csr_108_riscv,
+ csr_109_riscv,
+ csr_110_riscv,
+ csr_111_riscv,
+ csr_112_riscv,
+ csr_113_riscv,
+ csr_114_riscv,
+ csr_115_riscv,
+ csr_116_riscv,
+ csr_117_riscv,
+ csr_118_riscv,
+ csr_119_riscv,
+ csr_120_riscv,
+ csr_121_riscv,
+ csr_122_riscv,
+ csr_123_riscv,
+ csr_124_riscv,
+ csr_125_riscv,
+ csr_126_riscv,
+ csr_127_riscv,
+ csr_128_riscv,
+ csr_129_riscv,
+ csr_130_riscv,
+ csr_131_riscv,
+ csr_132_riscv,
+ csr_133_riscv,
+ csr_134_riscv,
+ csr_135_riscv,
+ csr_136_riscv,
+ csr_137_riscv,
+ csr_138_riscv,
+ csr_139_riscv,
+ csr_140_riscv,
+ csr_141_riscv,
+ csr_142_riscv,
+ csr_143_riscv,
+ csr_144_riscv,
+ csr_145_riscv,
+ csr_146_riscv,
+ csr_147_riscv,
+ csr_148_riscv,
+ csr_149_riscv,
+ csr_150_riscv,
+ csr_151_riscv,
+ csr_152_riscv,
+ csr_153_riscv,
+ csr_154_riscv,
+ csr_155_riscv,
+ csr_156_riscv,
+ csr_157_riscv,
+ csr_158_riscv,
+ csr_159_riscv,
+ csr_160_riscv,
+ csr_161_riscv,
+ csr_162_riscv,
+ csr_163_riscv,
+ csr_164_riscv,
+ csr_165_riscv,
+ csr_166_riscv,
+ csr_167_riscv,
+ csr_168_riscv,
+ csr_169_riscv,
+ csr_170_riscv,
+ csr_171_riscv,
+ csr_172_riscv,
+ csr_173_riscv,
+ csr_174_riscv,
+ csr_175_riscv,
+ csr_176_riscv,
+ csr_177_riscv,
+ csr_178_riscv,
+ csr_179_riscv,
+ csr_180_riscv,
+ csr_181_riscv,
+ csr_182_riscv,
+ csr_183_riscv,
+ csr_184_riscv,
+ csr_185_riscv,
+ csr_186_riscv,
+ csr_187_riscv,
+ csr_188_riscv,
+ csr_189_riscv,
+ csr_190_riscv,
+ csr_191_riscv,
+ csr_192_riscv,
+ csr_193_riscv,
+ csr_194_riscv,
+ csr_195_riscv,
+ csr_196_riscv,
+ csr_197_riscv,
+ csr_198_riscv,
+ csr_199_riscv,
+ csr_200_riscv,
+ csr_201_riscv,
+ csr_202_riscv,
+ csr_203_riscv,
+ csr_204_riscv,
+ csr_205_riscv,
+ csr_206_riscv,
+ csr_207_riscv,
+ csr_208_riscv,
+ csr_209_riscv,
+ csr_210_riscv,
+ csr_211_riscv,
+ csr_212_riscv,
+ csr_213_riscv,
+ csr_214_riscv,
+ csr_215_riscv,
+ csr_216_riscv,
+ csr_217_riscv,
+ csr_218_riscv,
+ csr_219_riscv,
+ csr_220_riscv,
+ csr_221_riscv,
+ csr_222_riscv,
+ csr_223_riscv,
+ csr_224_riscv,
+ csr_225_riscv,
+ csr_226_riscv,
+ csr_227_riscv,
+ csr_228_riscv,
+ csr_229_riscv,
+ csr_230_riscv,
+ csr_231_riscv,
+ csr_232_riscv,
+ csr_233_riscv,
+ csr_234_riscv,
+ csr_235_riscv,
+ csr_236_riscv,
+ csr_237_riscv,
+ csr_238_riscv,
+ csr_239_riscv,
+ csr_240_riscv,
+ csr_241_riscv,
+ csr_242_riscv,
+ csr_243_riscv,
+ csr_244_riscv,
+ csr_245_riscv,
+ csr_246_riscv,
+ csr_247_riscv,
+ csr_248_riscv,
+ csr_249_riscv,
+ csr_250_riscv,
+ csr_251_riscv,
+ csr_252_riscv,
+ csr_253_riscv,
+ csr_254_riscv,
+ csr_255_riscv,
+ csr_256_riscv,
+ csr_257_riscv,
+ csr_258_riscv,
+ csr_259_riscv,
+ csr_260_riscv,
+ csr_261_riscv,
+ csr_262_riscv,
+ csr_263_riscv,
+ csr_264_riscv,
+ csr_265_riscv,
+ csr_266_riscv,
+ csr_267_riscv,
+ csr_268_riscv,
+ csr_269_riscv,
+ csr_270_riscv,
+ csr_271_riscv,
+ csr_272_riscv,
+ csr_273_riscv,
+ csr_274_riscv,
+ csr_275_riscv,
+ csr_276_riscv,
+ csr_277_riscv,
+ csr_278_riscv,
+ csr_279_riscv,
+ csr_280_riscv,
+ csr_281_riscv,
+ csr_282_riscv,
+ csr_283_riscv,
+ csr_284_riscv,
+ csr_285_riscv,
+ csr_286_riscv,
+ csr_287_riscv,
+ csr_288_riscv,
+ csr_289_riscv,
+ csr_290_riscv,
+ csr_291_riscv,
+ csr_292_riscv,
+ csr_293_riscv,
+ csr_294_riscv,
+ csr_295_riscv,
+ csr_296_riscv,
+ csr_297_riscv,
+ csr_298_riscv,
+ csr_299_riscv,
+ csr_300_riscv,
+ csr_301_riscv,
+ csr_302_riscv,
+ csr_303_riscv,
+ csr_304_riscv,
+ csr_305_riscv,
+ csr_306_riscv,
+ csr_307_riscv,
+ csr_308_riscv,
+ csr_309_riscv,
+ csr_310_riscv,
+ csr_311_riscv,
+ csr_312_riscv,
+ csr_313_riscv,
+ csr_314_riscv,
+ csr_315_riscv,
+ csr_316_riscv,
+ csr_317_riscv,
+ csr_318_riscv,
+ csr_319_riscv,
+ csr_320_riscv,
+ csr_321_riscv,
+ csr_322_riscv,
+ csr_323_riscv,
+ csr_324_riscv,
+ csr_325_riscv,
+ csr_326_riscv,
+ csr_327_riscv,
+ csr_328_riscv,
+ csr_329_riscv,
+ csr_330_riscv,
+ csr_331_riscv,
+ csr_332_riscv,
+ csr_333_riscv,
+ csr_334_riscv,
+ csr_335_riscv,
+ csr_336_riscv,
+ csr_337_riscv,
+ csr_338_riscv,
+ csr_339_riscv,
+ csr_340_riscv,
+ csr_341_riscv,
+ csr_342_riscv,
+ csr_343_riscv,
+ csr_344_riscv,
+ csr_345_riscv,
+ csr_346_riscv,
+ csr_347_riscv,
+ csr_348_riscv,
+ csr_349_riscv,
+ csr_350_riscv,
+ csr_351_riscv,
+ csr_352_riscv,
+ csr_353_riscv,
+ csr_354_riscv,
+ csr_355_riscv,
+ csr_356_riscv,
+ csr_357_riscv,
+ csr_358_riscv,
+ csr_359_riscv,
+ csr_360_riscv,
+ csr_361_riscv,
+ csr_362_riscv,
+ csr_363_riscv,
+ csr_364_riscv,
+ csr_365_riscv,
+ csr_366_riscv,
+ csr_367_riscv,
+ csr_368_riscv,
+ csr_369_riscv,
+ csr_370_riscv,
+ csr_371_riscv,
+ csr_372_riscv,
+ csr_373_riscv,
+ csr_374_riscv,
+ csr_375_riscv,
+ csr_376_riscv,
+ csr_377_riscv,
+ csr_378_riscv,
+ csr_379_riscv,
+ csr_380_riscv,
+ csr_381_riscv,
+ csr_382_riscv,
+ csr_383_riscv,
+ csr_384_riscv,
+ csr_385_riscv,
+ csr_386_riscv,
+ csr_387_riscv,
+ csr_388_riscv,
+ csr_389_riscv,
+ csr_390_riscv,
+ csr_391_riscv,
+ csr_392_riscv,
+ csr_393_riscv,
+ csr_394_riscv,
+ csr_395_riscv,
+ csr_396_riscv,
+ csr_397_riscv,
+ csr_398_riscv,
+ csr_399_riscv,
+ csr_400_riscv,
+ csr_401_riscv,
+ csr_402_riscv,
+ csr_403_riscv,
+ csr_404_riscv,
+ csr_405_riscv,
+ csr_406_riscv,
+ csr_407_riscv,
+ csr_408_riscv,
+ csr_409_riscv,
+ csr_410_riscv,
+ csr_411_riscv,
+ csr_412_riscv,
+ csr_413_riscv,
+ csr_414_riscv,
+ csr_415_riscv,
+ csr_416_riscv,
+ csr_417_riscv,
+ csr_418_riscv,
+ csr_419_riscv,
+ csr_420_riscv,
+ csr_421_riscv,
+ csr_422_riscv,
+ csr_423_riscv,
+ csr_424_riscv,
+ csr_425_riscv,
+ csr_426_riscv,
+ csr_427_riscv,
+ csr_428_riscv,
+ csr_429_riscv,
+ csr_430_riscv,
+ csr_431_riscv,
+ csr_432_riscv,
+ csr_433_riscv,
+ csr_434_riscv,
+ csr_435_riscv,
+ csr_436_riscv,
+ csr_437_riscv,
+ csr_438_riscv,
+ csr_439_riscv,
+ csr_440_riscv,
+ csr_441_riscv,
+ csr_442_riscv,
+ csr_443_riscv,
+ csr_444_riscv,
+ csr_445_riscv,
+ csr_446_riscv,
+ csr_447_riscv,
+ csr_448_riscv,
+ csr_449_riscv,
+ csr_450_riscv,
+ csr_451_riscv,
+ csr_452_riscv,
+ csr_453_riscv,
+ csr_454_riscv,
+ csr_455_riscv,
+ csr_456_riscv,
+ csr_457_riscv,
+ csr_458_riscv,
+ csr_459_riscv,
+ csr_460_riscv,
+ csr_461_riscv,
+ csr_462_riscv,
+ csr_463_riscv,
+ csr_464_riscv,
+ csr_465_riscv,
+ csr_466_riscv,
+ csr_467_riscv,
+ csr_468_riscv,
+ csr_469_riscv,
+ csr_470_riscv,
+ csr_471_riscv,
+ csr_472_riscv,
+ csr_473_riscv,
+ csr_474_riscv,
+ csr_475_riscv,
+ csr_476_riscv,
+ csr_477_riscv,
+ csr_478_riscv,
+ csr_479_riscv,
+ csr_480_riscv,
+ csr_481_riscv,
+ csr_482_riscv,
+ csr_483_riscv,
+ csr_484_riscv,
+ csr_485_riscv,
+ csr_486_riscv,
+ csr_487_riscv,
+ csr_488_riscv,
+ csr_489_riscv,
+ csr_490_riscv,
+ csr_491_riscv,
+ csr_492_riscv,
+ csr_493_riscv,
+ csr_494_riscv,
+ csr_495_riscv,
+ csr_496_riscv,
+ csr_497_riscv,
+ csr_498_riscv,
+ csr_499_riscv,
+ csr_500_riscv,
+ csr_501_riscv,
+ csr_502_riscv,
+ csr_503_riscv,
+ csr_504_riscv,
+ csr_505_riscv,
+ csr_506_riscv,
+ csr_507_riscv,
+ csr_508_riscv,
+ csr_509_riscv,
+ csr_510_riscv,
+ csr_511_riscv,
+ csr_512_riscv,
+ csr_513_riscv,
+ csr_514_riscv,
+ csr_515_riscv,
+ csr_516_riscv,
+ csr_517_riscv,
+ csr_518_riscv,
+ csr_519_riscv,
+ csr_520_riscv,
+ csr_521_riscv,
+ csr_522_riscv,
+ csr_523_riscv,
+ csr_524_riscv,
+ csr_525_riscv,
+ csr_526_riscv,
+ csr_527_riscv,
+ csr_528_riscv,
+ csr_529_riscv,
+ csr_530_riscv,
+ csr_531_riscv,
+ csr_532_riscv,
+ csr_533_riscv,
+ csr_534_riscv,
+ csr_535_riscv,
+ csr_536_riscv,
+ csr_537_riscv,
+ csr_538_riscv,
+ csr_539_riscv,
+ csr_540_riscv,
+ csr_541_riscv,
+ csr_542_riscv,
+ csr_543_riscv,
+ csr_544_riscv,
+ csr_545_riscv,
+ csr_546_riscv,
+ csr_547_riscv,
+ csr_548_riscv,
+ csr_549_riscv,
+ csr_550_riscv,
+ csr_551_riscv,
+ csr_552_riscv,
+ csr_553_riscv,
+ csr_554_riscv,
+ csr_555_riscv,
+ csr_556_riscv,
+ csr_557_riscv,
+ csr_558_riscv,
+ csr_559_riscv,
+ csr_560_riscv,
+ csr_561_riscv,
+ csr_562_riscv,
+ csr_563_riscv,
+ csr_564_riscv,
+ csr_565_riscv,
+ csr_566_riscv,
+ csr_567_riscv,
+ csr_568_riscv,
+ csr_569_riscv,
+ csr_570_riscv,
+ csr_571_riscv,
+ csr_572_riscv,
+ csr_573_riscv,
+ csr_574_riscv,
+ csr_575_riscv,
+ csr_576_riscv,
+ csr_577_riscv,
+ csr_578_riscv,
+ csr_579_riscv,
+ csr_580_riscv,
+ csr_581_riscv,
+ csr_582_riscv,
+ csr_583_riscv,
+ csr_584_riscv,
+ csr_585_riscv,
+ csr_586_riscv,
+ csr_587_riscv,
+ csr_588_riscv,
+ csr_589_riscv,
+ csr_590_riscv,
+ csr_591_riscv,
+ csr_592_riscv,
+ csr_593_riscv,
+ csr_594_riscv,
+ csr_595_riscv,
+ csr_596_riscv,
+ csr_597_riscv,
+ csr_598_riscv,
+ csr_599_riscv,
+ csr_600_riscv,
+ csr_601_riscv,
+ csr_602_riscv,
+ csr_603_riscv,
+ csr_604_riscv,
+ csr_605_riscv,
+ csr_606_riscv,
+ csr_607_riscv,
+ csr_608_riscv,
+ csr_609_riscv,
+ csr_610_riscv,
+ csr_611_riscv,
+ csr_612_riscv,
+ csr_613_riscv,
+ csr_614_riscv,
+ csr_615_riscv,
+ csr_616_riscv,
+ csr_617_riscv,
+ csr_618_riscv,
+ csr_619_riscv,
+ csr_620_riscv,
+ csr_621_riscv,
+ csr_622_riscv,
+ csr_623_riscv,
+ csr_624_riscv,
+ csr_625_riscv,
+ csr_626_riscv,
+ csr_627_riscv,
+ csr_628_riscv,
+ csr_629_riscv,
+ csr_630_riscv,
+ csr_631_riscv,
+ csr_632_riscv,
+ csr_633_riscv,
+ csr_634_riscv,
+ csr_635_riscv,
+ csr_636_riscv,
+ csr_637_riscv,
+ csr_638_riscv,
+ csr_639_riscv,
+ csr_640_riscv,
+ csr_641_riscv,
+ csr_642_riscv,
+ csr_643_riscv,
+ csr_644_riscv,
+ csr_645_riscv,
+ csr_646_riscv,
+ csr_647_riscv,
+ csr_648_riscv,
+ csr_649_riscv,
+ csr_650_riscv,
+ csr_651_riscv,
+ csr_652_riscv,
+ csr_653_riscv,
+ csr_654_riscv,
+ csr_655_riscv,
+ csr_656_riscv,
+ csr_657_riscv,
+ csr_658_riscv,
+ csr_659_riscv,
+ csr_660_riscv,
+ csr_661_riscv,
+ csr_662_riscv,
+ csr_663_riscv,
+ csr_664_riscv,
+ csr_665_riscv,
+ csr_666_riscv,
+ csr_667_riscv,
+ csr_668_riscv,
+ csr_669_riscv,
+ csr_670_riscv,
+ csr_671_riscv,
+ csr_672_riscv,
+ csr_673_riscv,
+ csr_674_riscv,
+ csr_675_riscv,
+ csr_676_riscv,
+ csr_677_riscv,
+ csr_678_riscv,
+ csr_679_riscv,
+ csr_680_riscv,
+ csr_681_riscv,
+ csr_682_riscv,
+ csr_683_riscv,
+ csr_684_riscv,
+ csr_685_riscv,
+ csr_686_riscv,
+ csr_687_riscv,
+ csr_688_riscv,
+ csr_689_riscv,
+ csr_690_riscv,
+ csr_691_riscv,
+ csr_692_riscv,
+ csr_693_riscv,
+ csr_694_riscv,
+ csr_695_riscv,
+ csr_696_riscv,
+ csr_697_riscv,
+ csr_698_riscv,
+ csr_699_riscv,
+ csr_700_riscv,
+ csr_701_riscv,
+ csr_702_riscv,
+ csr_703_riscv,
+ csr_704_riscv,
+ csr_705_riscv,
+ csr_706_riscv,
+ csr_707_riscv,
+ csr_708_riscv,
+ csr_709_riscv,
+ csr_710_riscv,
+ csr_711_riscv,
+ csr_712_riscv,
+ csr_713_riscv,
+ csr_714_riscv,
+ csr_715_riscv,
+ csr_716_riscv,
+ csr_717_riscv,
+ csr_718_riscv,
+ csr_719_riscv,
+ csr_720_riscv,
+ csr_721_riscv,
+ csr_722_riscv,
+ csr_723_riscv,
+ csr_724_riscv,
+ csr_725_riscv,
+ csr_726_riscv,
+ csr_727_riscv,
+ csr_728_riscv,
+ csr_729_riscv,
+ csr_730_riscv,
+ csr_731_riscv,
+ csr_732_riscv,
+ csr_733_riscv,
+ csr_734_riscv,
+ csr_735_riscv,
+ csr_736_riscv,
+ csr_737_riscv,
+ csr_738_riscv,
+ csr_739_riscv,
+ csr_740_riscv,
+ csr_741_riscv,
+ csr_742_riscv,
+ csr_743_riscv,
+ csr_744_riscv,
+ csr_745_riscv,
+ csr_746_riscv,
+ csr_747_riscv,
+ csr_748_riscv,
+ csr_749_riscv,
+ csr_750_riscv,
+ csr_751_riscv,
+ csr_752_riscv,
+ csr_753_riscv,
+ csr_754_riscv,
+ csr_755_riscv,
+ csr_756_riscv,
+ csr_757_riscv,
+ csr_758_riscv,
+ csr_759_riscv,
+ csr_760_riscv,
+ csr_761_riscv,
+ csr_762_riscv,
+ csr_763_riscv,
+ csr_764_riscv,
+ csr_765_riscv,
+ csr_766_riscv,
+ csr_767_riscv,
+ csr_768_riscv,
+ csr_769_riscv,
+ csr_770_riscv,
+ csr_771_riscv,
+ csr_772_riscv,
+ csr_773_riscv,
+ csr_774_riscv,
+ csr_775_riscv,
+ csr_776_riscv,
+ csr_777_riscv,
+ csr_778_riscv,
+ csr_779_riscv,
+ csr_780_riscv,
+ csr_781_riscv,
+ csr_782_riscv,
+ csr_783_riscv,
+ csr_784_riscv,
+ csr_785_riscv,
+ csr_786_riscv,
+ csr_787_riscv,
+ csr_788_riscv,
+ csr_789_riscv,
+ csr_790_riscv,
+ csr_791_riscv,
+ csr_792_riscv,
+ csr_793_riscv,
+ csr_794_riscv,
+ csr_795_riscv,
+ csr_796_riscv,
+ csr_797_riscv,
+ csr_798_riscv,
+ csr_799_riscv,
+ csr_800_riscv,
+ csr_801_riscv,
+ csr_802_riscv,
+ csr_803_riscv,
+ csr_804_riscv,
+ csr_805_riscv,
+ csr_806_riscv,
+ csr_807_riscv,
+ csr_808_riscv,
+ csr_809_riscv,
+ csr_810_riscv,
+ csr_811_riscv,
+ csr_812_riscv,
+ csr_813_riscv,
+ csr_814_riscv,
+ csr_815_riscv,
+ csr_816_riscv,
+ csr_817_riscv,
+ csr_818_riscv,
+ csr_819_riscv,
+ csr_820_riscv,
+ csr_821_riscv,
+ csr_822_riscv,
+ csr_823_riscv,
+ csr_824_riscv,
+ csr_825_riscv,
+ csr_826_riscv,
+ csr_827_riscv,
+ csr_828_riscv,
+ csr_829_riscv,
+ csr_830_riscv,
+ csr_831_riscv,
+ csr_832_riscv,
+ csr_833_riscv,
+ csr_834_riscv,
+ csr_835_riscv,
+ csr_836_riscv,
+ csr_837_riscv,
+ csr_838_riscv,
+ csr_839_riscv,
+ csr_840_riscv,
+ csr_841_riscv,
+ csr_842_riscv,
+ csr_843_riscv,
+ csr_844_riscv,
+ csr_845_riscv,
+ csr_846_riscv,
+ csr_847_riscv,
+ csr_848_riscv,
+ csr_849_riscv,
+ csr_850_riscv,
+ csr_851_riscv,
+ csr_852_riscv,
+ csr_853_riscv,
+ csr_854_riscv,
+ csr_855_riscv,
+ csr_856_riscv,
+ csr_857_riscv,
+ csr_858_riscv,
+ csr_859_riscv,
+ csr_860_riscv,
+ csr_861_riscv,
+ csr_862_riscv,
+ csr_863_riscv,
+ csr_864_riscv,
+ csr_865_riscv,
+ csr_866_riscv,
+ csr_867_riscv,
+ csr_868_riscv,
+ csr_869_riscv,
+ csr_870_riscv,
+ csr_871_riscv,
+ csr_872_riscv,
+ csr_873_riscv,
+ csr_874_riscv,
+ csr_875_riscv,
+ csr_876_riscv,
+ csr_877_riscv,
+ csr_878_riscv,
+ csr_879_riscv,
+ csr_880_riscv,
+ csr_881_riscv,
+ csr_882_riscv,
+ csr_883_riscv,
+ csr_884_riscv,
+ csr_885_riscv,
+ csr_886_riscv,
+ csr_887_riscv,
+ csr_888_riscv,
+ csr_889_riscv,
+ csr_890_riscv,
+ csr_891_riscv,
+ csr_892_riscv,
+ csr_893_riscv,
+ csr_894_riscv,
+ csr_895_riscv,
+ csr_896_riscv,
+ csr_897_riscv,
+ csr_898_riscv,
+ csr_899_riscv,
+ csr_900_riscv,
+ csr_901_riscv,
+ csr_902_riscv,
+ csr_903_riscv,
+ csr_904_riscv,
+ csr_905_riscv,
+ csr_906_riscv,
+ csr_907_riscv,
+ csr_908_riscv,
+ csr_909_riscv,
+ csr_910_riscv,
+ csr_911_riscv,
+ csr_912_riscv,
+ csr_913_riscv,
+ csr_914_riscv,
+ csr_915_riscv,
+ csr_916_riscv,
+ csr_917_riscv,
+ csr_918_riscv,
+ csr_919_riscv,
+ csr_920_riscv,
+ csr_921_riscv,
+ csr_922_riscv,
+ csr_923_riscv,
+ csr_924_riscv,
+ csr_925_riscv,
+ csr_926_riscv,
+ csr_927_riscv,
+ csr_928_riscv,
+ csr_929_riscv,
+ csr_930_riscv,
+ csr_931_riscv,
+ csr_932_riscv,
+ csr_933_riscv,
+ csr_934_riscv,
+ csr_935_riscv,
+ csr_936_riscv,
+ csr_937_riscv,
+ csr_938_riscv,
+ csr_939_riscv,
+ csr_940_riscv,
+ csr_941_riscv,
+ csr_942_riscv,
+ csr_943_riscv,
+ csr_944_riscv,
+ csr_945_riscv,
+ csr_946_riscv,
+ csr_947_riscv,
+ csr_948_riscv,
+ csr_949_riscv,
+ csr_950_riscv,
+ csr_951_riscv,
+ csr_952_riscv,
+ csr_953_riscv,
+ csr_954_riscv,
+ csr_955_riscv,
+ csr_956_riscv,
+ csr_957_riscv,
+ csr_958_riscv,
+ csr_959_riscv,
+ csr_960_riscv,
+ csr_961_riscv,
+ csr_962_riscv,
+ csr_963_riscv,
+ csr_964_riscv,
+ csr_965_riscv,
+ csr_966_riscv,
+ csr_967_riscv,
+ csr_968_riscv,
+ csr_969_riscv,
+ csr_970_riscv,
+ csr_971_riscv,
+ csr_972_riscv,
+ csr_973_riscv,
+ csr_974_riscv,
+ csr_975_riscv,
+ csr_976_riscv,
+ csr_977_riscv,
+ csr_978_riscv,
+ csr_979_riscv,
+ csr_980_riscv,
+ csr_981_riscv,
+ csr_982_riscv,
+ csr_983_riscv,
+ csr_984_riscv,
+ csr_985_riscv,
+ csr_986_riscv,
+ csr_987_riscv,
+ csr_988_riscv,
+ csr_989_riscv,
+ csr_990_riscv,
+ csr_991_riscv,
+ csr_992_riscv,
+ csr_993_riscv,
+ csr_994_riscv,
+ csr_995_riscv,
+ csr_996_riscv,
+ csr_997_riscv,
+ csr_998_riscv,
+ csr_999_riscv,
+ csr_1000_riscv,
+ csr_1001_riscv,
+ csr_1002_riscv,
+ csr_1003_riscv,
+ csr_1004_riscv,
+ csr_1005_riscv,
+ csr_1006_riscv,
+ csr_1007_riscv,
+ csr_1008_riscv,
+ csr_1009_riscv,
+ csr_1010_riscv,
+ csr_1011_riscv,
+ csr_1012_riscv,
+ csr_1013_riscv,
+ csr_1014_riscv,
+ csr_1015_riscv,
+ csr_1016_riscv,
+ csr_1017_riscv,
+ csr_1018_riscv,
+ csr_1019_riscv,
+ csr_1020_riscv,
+ csr_1021_riscv,
+ csr_1022_riscv,
+ csr_1023_riscv,
+ csr_1024_riscv,
+ csr_1025_riscv,
+ csr_1026_riscv,
+ csr_1027_riscv,
+ csr_1028_riscv,
+ csr_1029_riscv,
+ csr_1030_riscv,
+ csr_1031_riscv,
+ csr_1032_riscv,
+ csr_1033_riscv,
+ csr_1034_riscv,
+ csr_1035_riscv,
+ csr_1036_riscv,
+ csr_1037_riscv,
+ csr_1038_riscv,
+ csr_1039_riscv,
+ csr_1040_riscv,
+ csr_1041_riscv,
+ csr_1042_riscv,
+ csr_1043_riscv,
+ csr_1044_riscv,
+ csr_1045_riscv,
+ csr_1046_riscv,
+ csr_1047_riscv,
+ csr_1048_riscv,
+ csr_1049_riscv,
+ csr_1050_riscv,
+ csr_1051_riscv,
+ csr_1052_riscv,
+ csr_1053_riscv,
+ csr_1054_riscv,
+ csr_1055_riscv,
+ csr_1056_riscv,
+ csr_1057_riscv,
+ csr_1058_riscv,
+ csr_1059_riscv,
+ csr_1060_riscv,
+ csr_1061_riscv,
+ csr_1062_riscv,
+ csr_1063_riscv,
+ csr_1064_riscv,
+ csr_1065_riscv,
+ csr_1066_riscv,
+ csr_1067_riscv,
+ csr_1068_riscv,
+ csr_1069_riscv,
+ csr_1070_riscv,
+ csr_1071_riscv,
+ csr_1072_riscv,
+ csr_1073_riscv,
+ csr_1074_riscv,
+ csr_1075_riscv,
+ csr_1076_riscv,
+ csr_1077_riscv,
+ csr_1078_riscv,
+ csr_1079_riscv,
+ csr_1080_riscv,
+ csr_1081_riscv,
+ csr_1082_riscv,
+ csr_1083_riscv,
+ csr_1084_riscv,
+ csr_1085_riscv,
+ csr_1086_riscv,
+ csr_1087_riscv,
+ csr_1088_riscv,
+ csr_1089_riscv,
+ csr_1090_riscv,
+ csr_1091_riscv,
+ csr_1092_riscv,
+ csr_1093_riscv,
+ csr_1094_riscv,
+ csr_1095_riscv,
+ csr_1096_riscv,
+ csr_1097_riscv,
+ csr_1098_riscv,
+ csr_1099_riscv,
+ csr_1100_riscv,
+ csr_1101_riscv,
+ csr_1102_riscv,
+ csr_1103_riscv,
+ csr_1104_riscv,
+ csr_1105_riscv,
+ csr_1106_riscv,
+ csr_1107_riscv,
+ csr_1108_riscv,
+ csr_1109_riscv,
+ csr_1110_riscv,
+ csr_1111_riscv,
+ csr_1112_riscv,
+ csr_1113_riscv,
+ csr_1114_riscv,
+ csr_1115_riscv,
+ csr_1116_riscv,
+ csr_1117_riscv,
+ csr_1118_riscv,
+ csr_1119_riscv,
+ csr_1120_riscv,
+ csr_1121_riscv,
+ csr_1122_riscv,
+ csr_1123_riscv,
+ csr_1124_riscv,
+ csr_1125_riscv,
+ csr_1126_riscv,
+ csr_1127_riscv,
+ csr_1128_riscv,
+ csr_1129_riscv,
+ csr_1130_riscv,
+ csr_1131_riscv,
+ csr_1132_riscv,
+ csr_1133_riscv,
+ csr_1134_riscv,
+ csr_1135_riscv,
+ csr_1136_riscv,
+ csr_1137_riscv,
+ csr_1138_riscv,
+ csr_1139_riscv,
+ csr_1140_riscv,
+ csr_1141_riscv,
+ csr_1142_riscv,
+ csr_1143_riscv,
+ csr_1144_riscv,
+ csr_1145_riscv,
+ csr_1146_riscv,
+ csr_1147_riscv,
+ csr_1148_riscv,
+ csr_1149_riscv,
+ csr_1150_riscv,
+ csr_1151_riscv,
+ csr_1152_riscv,
+ csr_1153_riscv,
+ csr_1154_riscv,
+ csr_1155_riscv,
+ csr_1156_riscv,
+ csr_1157_riscv,
+ csr_1158_riscv,
+ csr_1159_riscv,
+ csr_1160_riscv,
+ csr_1161_riscv,
+ csr_1162_riscv,
+ csr_1163_riscv,
+ csr_1164_riscv,
+ csr_1165_riscv,
+ csr_1166_riscv,
+ csr_1167_riscv,
+ csr_1168_riscv,
+ csr_1169_riscv,
+ csr_1170_riscv,
+ csr_1171_riscv,
+ csr_1172_riscv,
+ csr_1173_riscv,
+ csr_1174_riscv,
+ csr_1175_riscv,
+ csr_1176_riscv,
+ csr_1177_riscv,
+ csr_1178_riscv,
+ csr_1179_riscv,
+ csr_1180_riscv,
+ csr_1181_riscv,
+ csr_1182_riscv,
+ csr_1183_riscv,
+ csr_1184_riscv,
+ csr_1185_riscv,
+ csr_1186_riscv,
+ csr_1187_riscv,
+ csr_1188_riscv,
+ csr_1189_riscv,
+ csr_1190_riscv,
+ csr_1191_riscv,
+ csr_1192_riscv,
+ csr_1193_riscv,
+ csr_1194_riscv,
+ csr_1195_riscv,
+ csr_1196_riscv,
+ csr_1197_riscv,
+ csr_1198_riscv,
+ csr_1199_riscv,
+ csr_1200_riscv,
+ csr_1201_riscv,
+ csr_1202_riscv,
+ csr_1203_riscv,
+ csr_1204_riscv,
+ csr_1205_riscv,
+ csr_1206_riscv,
+ csr_1207_riscv,
+ csr_1208_riscv,
+ csr_1209_riscv,
+ csr_1210_riscv,
+ csr_1211_riscv,
+ csr_1212_riscv,
+ csr_1213_riscv,
+ csr_1214_riscv,
+ csr_1215_riscv,
+ csr_1216_riscv,
+ csr_1217_riscv,
+ csr_1218_riscv,
+ csr_1219_riscv,
+ csr_1220_riscv,
+ csr_1221_riscv,
+ csr_1222_riscv,
+ csr_1223_riscv,
+ csr_1224_riscv,
+ csr_1225_riscv,
+ csr_1226_riscv,
+ csr_1227_riscv,
+ csr_1228_riscv,
+ csr_1229_riscv,
+ csr_1230_riscv,
+ csr_1231_riscv,
+ csr_1232_riscv,
+ csr_1233_riscv,
+ csr_1234_riscv,
+ csr_1235_riscv,
+ csr_1236_riscv,
+ csr_1237_riscv,
+ csr_1238_riscv,
+ csr_1239_riscv,
+ csr_1240_riscv,
+ csr_1241_riscv,
+ csr_1242_riscv,
+ csr_1243_riscv,
+ csr_1244_riscv,
+ csr_1245_riscv,
+ csr_1246_riscv,
+ csr_1247_riscv,
+ csr_1248_riscv,
+ csr_1249_riscv,
+ csr_1250_riscv,
+ csr_1251_riscv,
+ csr_1252_riscv,
+ csr_1253_riscv,
+ csr_1254_riscv,
+ csr_1255_riscv,
+ csr_1256_riscv,
+ csr_1257_riscv,
+ csr_1258_riscv,
+ csr_1259_riscv,
+ csr_1260_riscv,
+ csr_1261_riscv,
+ csr_1262_riscv,
+ csr_1263_riscv,
+ csr_1264_riscv,
+ csr_1265_riscv,
+ csr_1266_riscv,
+ csr_1267_riscv,
+ csr_1268_riscv,
+ csr_1269_riscv,
+ csr_1270_riscv,
+ csr_1271_riscv,
+ csr_1272_riscv,
+ csr_1273_riscv,
+ csr_1274_riscv,
+ csr_1275_riscv,
+ csr_1276_riscv,
+ csr_1277_riscv,
+ csr_1278_riscv,
+ csr_1279_riscv,
+ csr_1280_riscv,
+ csr_1281_riscv,
+ csr_1282_riscv,
+ csr_1283_riscv,
+ csr_1284_riscv,
+ csr_1285_riscv,
+ csr_1286_riscv,
+ csr_1287_riscv,
+ csr_1288_riscv,
+ csr_1289_riscv,
+ csr_1290_riscv,
+ csr_1291_riscv,
+ csr_1292_riscv,
+ csr_1293_riscv,
+ csr_1294_riscv,
+ csr_1295_riscv,
+ csr_1296_riscv,
+ csr_1297_riscv,
+ csr_1298_riscv,
+ csr_1299_riscv,
+ csr_1300_riscv,
+ csr_1301_riscv,
+ csr_1302_riscv,
+ csr_1303_riscv,
+ csr_1304_riscv,
+ csr_1305_riscv,
+ csr_1306_riscv,
+ csr_1307_riscv,
+ csr_1308_riscv,
+ csr_1309_riscv,
+ csr_1310_riscv,
+ csr_1311_riscv,
+ csr_1312_riscv,
+ csr_1313_riscv,
+ csr_1314_riscv,
+ csr_1315_riscv,
+ csr_1316_riscv,
+ csr_1317_riscv,
+ csr_1318_riscv,
+ csr_1319_riscv,
+ csr_1320_riscv,
+ csr_1321_riscv,
+ csr_1322_riscv,
+ csr_1323_riscv,
+ csr_1324_riscv,
+ csr_1325_riscv,
+ csr_1326_riscv,
+ csr_1327_riscv,
+ csr_1328_riscv,
+ csr_1329_riscv,
+ csr_1330_riscv,
+ csr_1331_riscv,
+ csr_1332_riscv,
+ csr_1333_riscv,
+ csr_1334_riscv,
+ csr_1335_riscv,
+ csr_1336_riscv,
+ csr_1337_riscv,
+ csr_1338_riscv,
+ csr_1339_riscv,
+ csr_1340_riscv,
+ csr_1341_riscv,
+ csr_1342_riscv,
+ csr_1343_riscv,
+ csr_1344_riscv,
+ csr_1345_riscv,
+ csr_1346_riscv,
+ csr_1347_riscv,
+ csr_1348_riscv,
+ csr_1349_riscv,
+ csr_1350_riscv,
+ csr_1351_riscv,
+ csr_1352_riscv,
+ csr_1353_riscv,
+ csr_1354_riscv,
+ csr_1355_riscv,
+ csr_1356_riscv,
+ csr_1357_riscv,
+ csr_1358_riscv,
+ csr_1359_riscv,
+ csr_1360_riscv,
+ csr_1361_riscv,
+ csr_1362_riscv,
+ csr_1363_riscv,
+ csr_1364_riscv,
+ csr_1365_riscv,
+ csr_1366_riscv,
+ csr_1367_riscv,
+ csr_1368_riscv,
+ csr_1369_riscv,
+ csr_1370_riscv,
+ csr_1371_riscv,
+ csr_1372_riscv,
+ csr_1373_riscv,
+ csr_1374_riscv,
+ csr_1375_riscv,
+ csr_1376_riscv,
+ csr_1377_riscv,
+ csr_1378_riscv,
+ csr_1379_riscv,
+ csr_1380_riscv,
+ csr_1381_riscv,
+ csr_1382_riscv,
+ csr_1383_riscv,
+ csr_1384_riscv,
+ csr_1385_riscv,
+ csr_1386_riscv,
+ csr_1387_riscv,
+ csr_1388_riscv,
+ csr_1389_riscv,
+ csr_1390_riscv,
+ csr_1391_riscv,
+ csr_1392_riscv,
+ csr_1393_riscv,
+ csr_1394_riscv,
+ csr_1395_riscv,
+ csr_1396_riscv,
+ csr_1397_riscv,
+ csr_1398_riscv,
+ csr_1399_riscv,
+ csr_1400_riscv,
+ csr_1401_riscv,
+ csr_1402_riscv,
+ csr_1403_riscv,
+ csr_1404_riscv,
+ csr_1405_riscv,
+ csr_1406_riscv,
+ csr_1407_riscv,
+ csr_1408_riscv,
+ csr_1409_riscv,
+ csr_1410_riscv,
+ csr_1411_riscv,
+ csr_1412_riscv,
+ csr_1413_riscv,
+ csr_1414_riscv,
+ csr_1415_riscv,
+ csr_1416_riscv,
+ csr_1417_riscv,
+ csr_1418_riscv,
+ csr_1419_riscv,
+ csr_1420_riscv,
+ csr_1421_riscv,
+ csr_1422_riscv,
+ csr_1423_riscv,
+ csr_1424_riscv,
+ csr_1425_riscv,
+ csr_1426_riscv,
+ csr_1427_riscv,
+ csr_1428_riscv,
+ csr_1429_riscv,
+ csr_1430_riscv,
+ csr_1431_riscv,
+ csr_1432_riscv,
+ csr_1433_riscv,
+ csr_1434_riscv,
+ csr_1435_riscv,
+ csr_1436_riscv,
+ csr_1437_riscv,
+ csr_1438_riscv,
+ csr_1439_riscv,
+ csr_1440_riscv,
+ csr_1441_riscv,
+ csr_1442_riscv,
+ csr_1443_riscv,
+ csr_1444_riscv,
+ csr_1445_riscv,
+ csr_1446_riscv,
+ csr_1447_riscv,
+ csr_1448_riscv,
+ csr_1449_riscv,
+ csr_1450_riscv,
+ csr_1451_riscv,
+ csr_1452_riscv,
+ csr_1453_riscv,
+ csr_1454_riscv,
+ csr_1455_riscv,
+ csr_1456_riscv,
+ csr_1457_riscv,
+ csr_1458_riscv,
+ csr_1459_riscv,
+ csr_1460_riscv,
+ csr_1461_riscv,
+ csr_1462_riscv,
+ csr_1463_riscv,
+ csr_1464_riscv,
+ csr_1465_riscv,
+ csr_1466_riscv,
+ csr_1467_riscv,
+ csr_1468_riscv,
+ csr_1469_riscv,
+ csr_1470_riscv,
+ csr_1471_riscv,
+ csr_1472_riscv,
+ csr_1473_riscv,
+ csr_1474_riscv,
+ csr_1475_riscv,
+ csr_1476_riscv,
+ csr_1477_riscv,
+ csr_1478_riscv,
+ csr_1479_riscv,
+ csr_1480_riscv,
+ csr_1481_riscv,
+ csr_1482_riscv,
+ csr_1483_riscv,
+ csr_1484_riscv,
+ csr_1485_riscv,
+ csr_1486_riscv,
+ csr_1487_riscv,
+ csr_1488_riscv,
+ csr_1489_riscv,
+ csr_1490_riscv,
+ csr_1491_riscv,
+ csr_1492_riscv,
+ csr_1493_riscv,
+ csr_1494_riscv,
+ csr_1495_riscv,
+ csr_1496_riscv,
+ csr_1497_riscv,
+ csr_1498_riscv,
+ csr_1499_riscv,
+ csr_1500_riscv,
+ csr_1501_riscv,
+ csr_1502_riscv,
+ csr_1503_riscv,
+ csr_1504_riscv,
+ csr_1505_riscv,
+ csr_1506_riscv,
+ csr_1507_riscv,
+ csr_1508_riscv,
+ csr_1509_riscv,
+ csr_1510_riscv,
+ csr_1511_riscv,
+ csr_1512_riscv,
+ csr_1513_riscv,
+ csr_1514_riscv,
+ csr_1515_riscv,
+ csr_1516_riscv,
+ csr_1517_riscv,
+ csr_1518_riscv,
+ csr_1519_riscv,
+ csr_1520_riscv,
+ csr_1521_riscv,
+ csr_1522_riscv,
+ csr_1523_riscv,
+ csr_1524_riscv,
+ csr_1525_riscv,
+ csr_1526_riscv,
+ csr_1527_riscv,
+ csr_1528_riscv,
+ csr_1529_riscv,
+ csr_1530_riscv,
+ csr_1531_riscv,
+ csr_1532_riscv,
+ csr_1533_riscv,
+ csr_1534_riscv,
+ csr_1535_riscv,
+ csr_1536_riscv,
+ csr_1537_riscv,
+ csr_1538_riscv,
+ csr_1539_riscv,
+ csr_1540_riscv,
+ csr_1541_riscv,
+ csr_1542_riscv,
+ csr_1543_riscv,
+ csr_1544_riscv,
+ csr_1545_riscv,
+ csr_1546_riscv,
+ csr_1547_riscv,
+ csr_1548_riscv,
+ csr_1549_riscv,
+ csr_1550_riscv,
+ csr_1551_riscv,
+ csr_1552_riscv,
+ csr_1553_riscv,
+ csr_1554_riscv,
+ csr_1555_riscv,
+ csr_1556_riscv,
+ csr_1557_riscv,
+ csr_1558_riscv,
+ csr_1559_riscv,
+ csr_1560_riscv,
+ csr_1561_riscv,
+ csr_1562_riscv,
+ csr_1563_riscv,
+ csr_1564_riscv,
+ csr_1565_riscv,
+ csr_1566_riscv,
+ csr_1567_riscv,
+ csr_1568_riscv,
+ csr_1569_riscv,
+ csr_1570_riscv,
+ csr_1571_riscv,
+ csr_1572_riscv,
+ csr_1573_riscv,
+ csr_1574_riscv,
+ csr_1575_riscv,
+ csr_1576_riscv,
+ csr_1577_riscv,
+ csr_1578_riscv,
+ csr_1579_riscv,
+ csr_1580_riscv,
+ csr_1581_riscv,
+ csr_1582_riscv,
+ csr_1583_riscv,
+ csr_1584_riscv,
+ csr_1585_riscv,
+ csr_1586_riscv,
+ csr_1587_riscv,
+ csr_1588_riscv,
+ csr_1589_riscv,
+ csr_1590_riscv,
+ csr_1591_riscv,
+ csr_1592_riscv,
+ csr_1593_riscv,
+ csr_1594_riscv,
+ csr_1595_riscv,
+ csr_1596_riscv,
+ csr_1597_riscv,
+ csr_1598_riscv,
+ csr_1599_riscv,
+ csr_1600_riscv,
+ csr_1601_riscv,
+ csr_1602_riscv,
+ csr_1603_riscv,
+ csr_1604_riscv,
+ csr_1605_riscv,
+ csr_1606_riscv,
+ csr_1607_riscv,
+ csr_1608_riscv,
+ csr_1609_riscv,
+ csr_1610_riscv,
+ csr_1611_riscv,
+ csr_1612_riscv,
+ csr_1613_riscv,
+ csr_1614_riscv,
+ csr_1615_riscv,
+ csr_1616_riscv,
+ csr_1617_riscv,
+ csr_1618_riscv,
+ csr_1619_riscv,
+ csr_1620_riscv,
+ csr_1621_riscv,
+ csr_1622_riscv,
+ csr_1623_riscv,
+ csr_1624_riscv,
+ csr_1625_riscv,
+ csr_1626_riscv,
+ csr_1627_riscv,
+ csr_1628_riscv,
+ csr_1629_riscv,
+ csr_1630_riscv,
+ csr_1631_riscv,
+ csr_1632_riscv,
+ csr_1633_riscv,
+ csr_1634_riscv,
+ csr_1635_riscv,
+ csr_1636_riscv,
+ csr_1637_riscv,
+ csr_1638_riscv,
+ csr_1639_riscv,
+ csr_1640_riscv,
+ csr_1641_riscv,
+ csr_1642_riscv,
+ csr_1643_riscv,
+ csr_1644_riscv,
+ csr_1645_riscv,
+ csr_1646_riscv,
+ csr_1647_riscv,
+ csr_1648_riscv,
+ csr_1649_riscv,
+ csr_1650_riscv,
+ csr_1651_riscv,
+ csr_1652_riscv,
+ csr_1653_riscv,
+ csr_1654_riscv,
+ csr_1655_riscv,
+ csr_1656_riscv,
+ csr_1657_riscv,
+ csr_1658_riscv,
+ csr_1659_riscv,
+ csr_1660_riscv,
+ csr_1661_riscv,
+ csr_1662_riscv,
+ csr_1663_riscv,
+ csr_1664_riscv,
+ csr_1665_riscv,
+ csr_1666_riscv,
+ csr_1667_riscv,
+ csr_1668_riscv,
+ csr_1669_riscv,
+ csr_1670_riscv,
+ csr_1671_riscv,
+ csr_1672_riscv,
+ csr_1673_riscv,
+ csr_1674_riscv,
+ csr_1675_riscv,
+ csr_1676_riscv,
+ csr_1677_riscv,
+ csr_1678_riscv,
+ csr_1679_riscv,
+ csr_1680_riscv,
+ csr_1681_riscv,
+ csr_1682_riscv,
+ csr_1683_riscv,
+ csr_1684_riscv,
+ csr_1685_riscv,
+ csr_1686_riscv,
+ csr_1687_riscv,
+ csr_1688_riscv,
+ csr_1689_riscv,
+ csr_1690_riscv,
+ csr_1691_riscv,
+ csr_1692_riscv,
+ csr_1693_riscv,
+ csr_1694_riscv,
+ csr_1695_riscv,
+ csr_1696_riscv,
+ csr_1697_riscv,
+ csr_1698_riscv,
+ csr_1699_riscv,
+ csr_1700_riscv,
+ csr_1701_riscv,
+ csr_1702_riscv,
+ csr_1703_riscv,
+ csr_1704_riscv,
+ csr_1705_riscv,
+ csr_1706_riscv,
+ csr_1707_riscv,
+ csr_1708_riscv,
+ csr_1709_riscv,
+ csr_1710_riscv,
+ csr_1711_riscv,
+ csr_1712_riscv,
+ csr_1713_riscv,
+ csr_1714_riscv,
+ csr_1715_riscv,
+ csr_1716_riscv,
+ csr_1717_riscv,
+ csr_1718_riscv,
+ csr_1719_riscv,
+ csr_1720_riscv,
+ csr_1721_riscv,
+ csr_1722_riscv,
+ csr_1723_riscv,
+ csr_1724_riscv,
+ csr_1725_riscv,
+ csr_1726_riscv,
+ csr_1727_riscv,
+ csr_1728_riscv,
+ csr_1729_riscv,
+ csr_1730_riscv,
+ csr_1731_riscv,
+ csr_1732_riscv,
+ csr_1733_riscv,
+ csr_1734_riscv,
+ csr_1735_riscv,
+ csr_1736_riscv,
+ csr_1737_riscv,
+ csr_1738_riscv,
+ csr_1739_riscv,
+ csr_1740_riscv,
+ csr_1741_riscv,
+ csr_1742_riscv,
+ csr_1743_riscv,
+ csr_1744_riscv,
+ csr_1745_riscv,
+ csr_1746_riscv,
+ csr_1747_riscv,
+ csr_1748_riscv,
+ csr_1749_riscv,
+ csr_1750_riscv,
+ csr_1751_riscv,
+ csr_1752_riscv,
+ csr_1753_riscv,
+ csr_1754_riscv,
+ csr_1755_riscv,
+ csr_1756_riscv,
+ csr_1757_riscv,
+ csr_1758_riscv,
+ csr_1759_riscv,
+ csr_1760_riscv,
+ csr_1761_riscv,
+ csr_1762_riscv,
+ csr_1763_riscv,
+ csr_1764_riscv,
+ csr_1765_riscv,
+ csr_1766_riscv,
+ csr_1767_riscv,
+ csr_1768_riscv,
+ csr_1769_riscv,
+ csr_1770_riscv,
+ csr_1771_riscv,
+ csr_1772_riscv,
+ csr_1773_riscv,
+ csr_1774_riscv,
+ csr_1775_riscv,
+ csr_1776_riscv,
+ csr_1777_riscv,
+ csr_1778_riscv,
+ csr_1779_riscv,
+ csr_1780_riscv,
+ csr_1781_riscv,
+ csr_1782_riscv,
+ csr_1783_riscv,
+ csr_1784_riscv,
+ csr_1785_riscv,
+ csr_1786_riscv,
+ csr_1787_riscv,
+ csr_1788_riscv,
+ csr_1789_riscv,
+ csr_1790_riscv,
+ csr_1791_riscv,
+ csr_1792_riscv,
+ csr_1793_riscv,
+ csr_1794_riscv,
+ csr_1795_riscv,
+ csr_1796_riscv,
+ csr_1797_riscv,
+ csr_1798_riscv,
+ csr_1799_riscv,
+ csr_1800_riscv,
+ csr_1801_riscv,
+ csr_1802_riscv,
+ csr_1803_riscv,
+ csr_1804_riscv,
+ csr_1805_riscv,
+ csr_1806_riscv,
+ csr_1807_riscv,
+ csr_1808_riscv,
+ csr_1809_riscv,
+ csr_1810_riscv,
+ csr_1811_riscv,
+ csr_1812_riscv,
+ csr_1813_riscv,
+ csr_1814_riscv,
+ csr_1815_riscv,
+ csr_1816_riscv,
+ csr_1817_riscv,
+ csr_1818_riscv,
+ csr_1819_riscv,
+ csr_1820_riscv,
+ csr_1821_riscv,
+ csr_1822_riscv,
+ csr_1823_riscv,
+ csr_1824_riscv,
+ csr_1825_riscv,
+ csr_1826_riscv,
+ csr_1827_riscv,
+ csr_1828_riscv,
+ csr_1829_riscv,
+ csr_1830_riscv,
+ csr_1831_riscv,
+ csr_1832_riscv,
+ csr_1833_riscv,
+ csr_1834_riscv,
+ csr_1835_riscv,
+ csr_1836_riscv,
+ csr_1837_riscv,
+ csr_1838_riscv,
+ csr_1839_riscv,
+ csr_1840_riscv,
+ csr_1841_riscv,
+ csr_1842_riscv,
+ csr_1843_riscv,
+ csr_1844_riscv,
+ csr_1845_riscv,
+ csr_1846_riscv,
+ csr_1847_riscv,
+ csr_1848_riscv,
+ csr_1849_riscv,
+ csr_1850_riscv,
+ csr_1851_riscv,
+ csr_1852_riscv,
+ csr_1853_riscv,
+ csr_1854_riscv,
+ csr_1855_riscv,
+ csr_1856_riscv,
+ csr_1857_riscv,
+ csr_1858_riscv,
+ csr_1859_riscv,
+ csr_1860_riscv,
+ csr_1861_riscv,
+ csr_1862_riscv,
+ csr_1863_riscv,
+ csr_1864_riscv,
+ csr_1865_riscv,
+ csr_1866_riscv,
+ csr_1867_riscv,
+ csr_1868_riscv,
+ csr_1869_riscv,
+ csr_1870_riscv,
+ csr_1871_riscv,
+ csr_1872_riscv,
+ csr_1873_riscv,
+ csr_1874_riscv,
+ csr_1875_riscv,
+ csr_1876_riscv,
+ csr_1877_riscv,
+ csr_1878_riscv,
+ csr_1879_riscv,
+ csr_1880_riscv,
+ csr_1881_riscv,
+ csr_1882_riscv,
+ csr_1883_riscv,
+ csr_1884_riscv,
+ csr_1885_riscv,
+ csr_1886_riscv,
+ csr_1887_riscv,
+ csr_1888_riscv,
+ csr_1889_riscv,
+ csr_1890_riscv,
+ csr_1891_riscv,
+ csr_1892_riscv,
+ csr_1893_riscv,
+ csr_1894_riscv,
+ csr_1895_riscv,
+ csr_1896_riscv,
+ csr_1897_riscv,
+ csr_1898_riscv,
+ csr_1899_riscv,
+ csr_1900_riscv,
+ csr_1901_riscv,
+ csr_1902_riscv,
+ csr_1903_riscv,
+ csr_1904_riscv,
+ csr_1905_riscv,
+ csr_1906_riscv,
+ csr_1907_riscv,
+ csr_1908_riscv,
+ csr_1909_riscv,
+ csr_1910_riscv,
+ csr_1911_riscv,
+ csr_1912_riscv,
+ csr_1913_riscv,
+ csr_1914_riscv,
+ csr_1915_riscv,
+ csr_1916_riscv,
+ csr_1917_riscv,
+ csr_1918_riscv,
+ csr_1919_riscv,
+ csr_1920_riscv,
+ csr_1921_riscv,
+ csr_1922_riscv,
+ csr_1923_riscv,
+ csr_1924_riscv,
+ csr_1925_riscv,
+ csr_1926_riscv,
+ csr_1927_riscv,
+ csr_1928_riscv,
+ csr_1929_riscv,
+ csr_1930_riscv,
+ csr_1931_riscv,
+ csr_1932_riscv,
+ csr_1933_riscv,
+ csr_1934_riscv,
+ csr_1935_riscv,
+ csr_1936_riscv,
+ csr_1937_riscv,
+ csr_1938_riscv,
+ csr_1939_riscv,
+ csr_1940_riscv,
+ csr_1941_riscv,
+ csr_1942_riscv,
+ csr_1943_riscv,
+ csr_1944_riscv,
+ csr_1945_riscv,
+ csr_1946_riscv,
+ csr_1947_riscv,
+ csr_1948_riscv,
+ csr_1949_riscv,
+ csr_1950_riscv,
+ csr_1951_riscv,
+ csr_1952_riscv,
+ csr_1953_riscv,
+ csr_1954_riscv,
+ csr_1955_riscv,
+ csr_1956_riscv,
+ csr_1957_riscv,
+ csr_1958_riscv,
+ csr_1959_riscv,
+ csr_1960_riscv,
+ csr_1961_riscv,
+ csr_1962_riscv,
+ csr_1963_riscv,
+ csr_1964_riscv,
+ csr_1965_riscv,
+ csr_1966_riscv,
+ csr_1967_riscv,
+ csr_1968_riscv,
+ csr_1969_riscv,
+ csr_1970_riscv,
+ csr_1971_riscv,
+ csr_1972_riscv,
+ csr_1973_riscv,
+ csr_1974_riscv,
+ csr_1975_riscv,
+ csr_1976_riscv,
+ csr_1977_riscv,
+ csr_1978_riscv,
+ csr_1979_riscv,
+ csr_1980_riscv,
+ csr_1981_riscv,
+ csr_1982_riscv,
+ csr_1983_riscv,
+ csr_1984_riscv,
+ csr_1985_riscv,
+ csr_1986_riscv,
+ csr_1987_riscv,
+ csr_1988_riscv,
+ csr_1989_riscv,
+ csr_1990_riscv,
+ csr_1991_riscv,
+ csr_1992_riscv,
+ csr_1993_riscv,
+ csr_1994_riscv,
+ csr_1995_riscv,
+ csr_1996_riscv,
+ csr_1997_riscv,
+ csr_1998_riscv,
+ csr_1999_riscv,
+ csr_2000_riscv,
+ csr_2001_riscv,
+ csr_2002_riscv,
+ csr_2003_riscv,
+ csr_2004_riscv,
+ csr_2005_riscv,
+ csr_2006_riscv,
+ csr_2007_riscv,
+ csr_2008_riscv,
+ csr_2009_riscv,
+ csr_2010_riscv,
+ csr_2011_riscv,
+ csr_2012_riscv,
+ csr_2013_riscv,
+ csr_2014_riscv,
+ csr_2015_riscv,
+ csr_2016_riscv,
+ csr_2017_riscv,
+ csr_2018_riscv,
+ csr_2019_riscv,
+ csr_2020_riscv,
+ csr_2021_riscv,
+ csr_2022_riscv,
+ csr_2023_riscv,
+ csr_2024_riscv,
+ csr_2025_riscv,
+ csr_2026_riscv,
+ csr_2027_riscv,
+ csr_2028_riscv,
+ csr_2029_riscv,
+ csr_2030_riscv,
+ csr_2031_riscv,
+ csr_2032_riscv,
+ csr_2033_riscv,
+ csr_2034_riscv,
+ csr_2035_riscv,
+ csr_2036_riscv,
+ csr_2037_riscv,
+ csr_2038_riscv,
+ csr_2039_riscv,
+ csr_2040_riscv,
+ csr_2041_riscv,
+ csr_2042_riscv,
+ csr_2043_riscv,
+ csr_2044_riscv,
+ csr_2045_riscv,
+ csr_2046_riscv,
+ csr_2047_riscv,
+ csr_2048_riscv,
+ csr_2049_riscv,
+ csr_2050_riscv,
+ csr_2051_riscv,
+ csr_2052_riscv,
+ csr_2053_riscv,
+ csr_2054_riscv,
+ csr_2055_riscv,
+ csr_2056_riscv,
+ csr_2057_riscv,
+ csr_2058_riscv,
+ csr_2059_riscv,
+ csr_2060_riscv,
+ csr_2061_riscv,
+ csr_2062_riscv,
+ csr_2063_riscv,
+ csr_2064_riscv,
+ csr_2065_riscv,
+ csr_2066_riscv,
+ csr_2067_riscv,
+ csr_2068_riscv,
+ csr_2069_riscv,
+ csr_2070_riscv,
+ csr_2071_riscv,
+ csr_2072_riscv,
+ csr_2073_riscv,
+ csr_2074_riscv,
+ csr_2075_riscv,
+ csr_2076_riscv,
+ csr_2077_riscv,
+ csr_2078_riscv,
+ csr_2079_riscv,
+ csr_2080_riscv,
+ csr_2081_riscv,
+ csr_2082_riscv,
+ csr_2083_riscv,
+ csr_2084_riscv,
+ csr_2085_riscv,
+ csr_2086_riscv,
+ csr_2087_riscv,
+ csr_2088_riscv,
+ csr_2089_riscv,
+ csr_2090_riscv,
+ csr_2091_riscv,
+ csr_2092_riscv,
+ csr_2093_riscv,
+ csr_2094_riscv,
+ csr_2095_riscv,
+ csr_2096_riscv,
+ csr_2097_riscv,
+ csr_2098_riscv,
+ csr_2099_riscv,
+ csr_2100_riscv,
+ csr_2101_riscv,
+ csr_2102_riscv,
+ csr_2103_riscv,
+ csr_2104_riscv,
+ csr_2105_riscv,
+ csr_2106_riscv,
+ csr_2107_riscv,
+ csr_2108_riscv,
+ csr_2109_riscv,
+ csr_2110_riscv,
+ csr_2111_riscv,
+ csr_2112_riscv,
+ csr_2113_riscv,
+ csr_2114_riscv,
+ csr_2115_riscv,
+ csr_2116_riscv,
+ csr_2117_riscv,
+ csr_2118_riscv,
+ csr_2119_riscv,
+ csr_2120_riscv,
+ csr_2121_riscv,
+ csr_2122_riscv,
+ csr_2123_riscv,
+ csr_2124_riscv,
+ csr_2125_riscv,
+ csr_2126_riscv,
+ csr_2127_riscv,
+ csr_2128_riscv,
+ csr_2129_riscv,
+ csr_2130_riscv,
+ csr_2131_riscv,
+ csr_2132_riscv,
+ csr_2133_riscv,
+ csr_2134_riscv,
+ csr_2135_riscv,
+ csr_2136_riscv,
+ csr_2137_riscv,
+ csr_2138_riscv,
+ csr_2139_riscv,
+ csr_2140_riscv,
+ csr_2141_riscv,
+ csr_2142_riscv,
+ csr_2143_riscv,
+ csr_2144_riscv,
+ csr_2145_riscv,
+ csr_2146_riscv,
+ csr_2147_riscv,
+ csr_2148_riscv,
+ csr_2149_riscv,
+ csr_2150_riscv,
+ csr_2151_riscv,
+ csr_2152_riscv,
+ csr_2153_riscv,
+ csr_2154_riscv,
+ csr_2155_riscv,
+ csr_2156_riscv,
+ csr_2157_riscv,
+ csr_2158_riscv,
+ csr_2159_riscv,
+ csr_2160_riscv,
+ csr_2161_riscv,
+ csr_2162_riscv,
+ csr_2163_riscv,
+ csr_2164_riscv,
+ csr_2165_riscv,
+ csr_2166_riscv,
+ csr_2167_riscv,
+ csr_2168_riscv,
+ csr_2169_riscv,
+ csr_2170_riscv,
+ csr_2171_riscv,
+ csr_2172_riscv,
+ csr_2173_riscv,
+ csr_2174_riscv,
+ csr_2175_riscv,
+ csr_2176_riscv,
+ csr_2177_riscv,
+ csr_2178_riscv,
+ csr_2179_riscv,
+ csr_2180_riscv,
+ csr_2181_riscv,
+ csr_2182_riscv,
+ csr_2183_riscv,
+ csr_2184_riscv,
+ csr_2185_riscv,
+ csr_2186_riscv,
+ csr_2187_riscv,
+ csr_2188_riscv,
+ csr_2189_riscv,
+ csr_2190_riscv,
+ csr_2191_riscv,
+ csr_2192_riscv,
+ csr_2193_riscv,
+ csr_2194_riscv,
+ csr_2195_riscv,
+ csr_2196_riscv,
+ csr_2197_riscv,
+ csr_2198_riscv,
+ csr_2199_riscv,
+ csr_2200_riscv,
+ csr_2201_riscv,
+ csr_2202_riscv,
+ csr_2203_riscv,
+ csr_2204_riscv,
+ csr_2205_riscv,
+ csr_2206_riscv,
+ csr_2207_riscv,
+ csr_2208_riscv,
+ csr_2209_riscv,
+ csr_2210_riscv,
+ csr_2211_riscv,
+ csr_2212_riscv,
+ csr_2213_riscv,
+ csr_2214_riscv,
+ csr_2215_riscv,
+ csr_2216_riscv,
+ csr_2217_riscv,
+ csr_2218_riscv,
+ csr_2219_riscv,
+ csr_2220_riscv,
+ csr_2221_riscv,
+ csr_2222_riscv,
+ csr_2223_riscv,
+ csr_2224_riscv,
+ csr_2225_riscv,
+ csr_2226_riscv,
+ csr_2227_riscv,
+ csr_2228_riscv,
+ csr_2229_riscv,
+ csr_2230_riscv,
+ csr_2231_riscv,
+ csr_2232_riscv,
+ csr_2233_riscv,
+ csr_2234_riscv,
+ csr_2235_riscv,
+ csr_2236_riscv,
+ csr_2237_riscv,
+ csr_2238_riscv,
+ csr_2239_riscv,
+ csr_2240_riscv,
+ csr_2241_riscv,
+ csr_2242_riscv,
+ csr_2243_riscv,
+ csr_2244_riscv,
+ csr_2245_riscv,
+ csr_2246_riscv,
+ csr_2247_riscv,
+ csr_2248_riscv,
+ csr_2249_riscv,
+ csr_2250_riscv,
+ csr_2251_riscv,
+ csr_2252_riscv,
+ csr_2253_riscv,
+ csr_2254_riscv,
+ csr_2255_riscv,
+ csr_2256_riscv,
+ csr_2257_riscv,
+ csr_2258_riscv,
+ csr_2259_riscv,
+ csr_2260_riscv,
+ csr_2261_riscv,
+ csr_2262_riscv,
+ csr_2263_riscv,
+ csr_2264_riscv,
+ csr_2265_riscv,
+ csr_2266_riscv,
+ csr_2267_riscv,
+ csr_2268_riscv,
+ csr_2269_riscv,
+ csr_2270_riscv,
+ csr_2271_riscv,
+ csr_2272_riscv,
+ csr_2273_riscv,
+ csr_2274_riscv,
+ csr_2275_riscv,
+ csr_2276_riscv,
+ csr_2277_riscv,
+ csr_2278_riscv,
+ csr_2279_riscv,
+ csr_2280_riscv,
+ csr_2281_riscv,
+ csr_2282_riscv,
+ csr_2283_riscv,
+ csr_2284_riscv,
+ csr_2285_riscv,
+ csr_2286_riscv,
+ csr_2287_riscv,
+ csr_2288_riscv,
+ csr_2289_riscv,
+ csr_2290_riscv,
+ csr_2291_riscv,
+ csr_2292_riscv,
+ csr_2293_riscv,
+ csr_2294_riscv,
+ csr_2295_riscv,
+ csr_2296_riscv,
+ csr_2297_riscv,
+ csr_2298_riscv,
+ csr_2299_riscv,
+ csr_2300_riscv,
+ csr_2301_riscv,
+ csr_2302_riscv,
+ csr_2303_riscv,
+ csr_2304_riscv,
+ csr_2305_riscv,
+ csr_2306_riscv,
+ csr_2307_riscv,
+ csr_2308_riscv,
+ csr_2309_riscv,
+ csr_2310_riscv,
+ csr_2311_riscv,
+ csr_2312_riscv,
+ csr_2313_riscv,
+ csr_2314_riscv,
+ csr_2315_riscv,
+ csr_2316_riscv,
+ csr_2317_riscv,
+ csr_2318_riscv,
+ csr_2319_riscv,
+ csr_2320_riscv,
+ csr_2321_riscv,
+ csr_2322_riscv,
+ csr_2323_riscv,
+ csr_2324_riscv,
+ csr_2325_riscv,
+ csr_2326_riscv,
+ csr_2327_riscv,
+ csr_2328_riscv,
+ csr_2329_riscv,
+ csr_2330_riscv,
+ csr_2331_riscv,
+ csr_2332_riscv,
+ csr_2333_riscv,
+ csr_2334_riscv,
+ csr_2335_riscv,
+ csr_2336_riscv,
+ csr_2337_riscv,
+ csr_2338_riscv,
+ csr_2339_riscv,
+ csr_2340_riscv,
+ csr_2341_riscv,
+ csr_2342_riscv,
+ csr_2343_riscv,
+ csr_2344_riscv,
+ csr_2345_riscv,
+ csr_2346_riscv,
+ csr_2347_riscv,
+ csr_2348_riscv,
+ csr_2349_riscv,
+ csr_2350_riscv,
+ csr_2351_riscv,
+ csr_2352_riscv,
+ csr_2353_riscv,
+ csr_2354_riscv,
+ csr_2355_riscv,
+ csr_2356_riscv,
+ csr_2357_riscv,
+ csr_2358_riscv,
+ csr_2359_riscv,
+ csr_2360_riscv,
+ csr_2361_riscv,
+ csr_2362_riscv,
+ csr_2363_riscv,
+ csr_2364_riscv,
+ csr_2365_riscv,
+ csr_2366_riscv,
+ csr_2367_riscv,
+ csr_2368_riscv,
+ csr_2369_riscv,
+ csr_2370_riscv,
+ csr_2371_riscv,
+ csr_2372_riscv,
+ csr_2373_riscv,
+ csr_2374_riscv,
+ csr_2375_riscv,
+ csr_2376_riscv,
+ csr_2377_riscv,
+ csr_2378_riscv,
+ csr_2379_riscv,
+ csr_2380_riscv,
+ csr_2381_riscv,
+ csr_2382_riscv,
+ csr_2383_riscv,
+ csr_2384_riscv,
+ csr_2385_riscv,
+ csr_2386_riscv,
+ csr_2387_riscv,
+ csr_2388_riscv,
+ csr_2389_riscv,
+ csr_2390_riscv,
+ csr_2391_riscv,
+ csr_2392_riscv,
+ csr_2393_riscv,
+ csr_2394_riscv,
+ csr_2395_riscv,
+ csr_2396_riscv,
+ csr_2397_riscv,
+ csr_2398_riscv,
+ csr_2399_riscv,
+ csr_2400_riscv,
+ csr_2401_riscv,
+ csr_2402_riscv,
+ csr_2403_riscv,
+ csr_2404_riscv,
+ csr_2405_riscv,
+ csr_2406_riscv,
+ csr_2407_riscv,
+ csr_2408_riscv,
+ csr_2409_riscv,
+ csr_2410_riscv,
+ csr_2411_riscv,
+ csr_2412_riscv,
+ csr_2413_riscv,
+ csr_2414_riscv,
+ csr_2415_riscv,
+ csr_2416_riscv,
+ csr_2417_riscv,
+ csr_2418_riscv,
+ csr_2419_riscv,
+ csr_2420_riscv,
+ csr_2421_riscv,
+ csr_2422_riscv,
+ csr_2423_riscv,
+ csr_2424_riscv,
+ csr_2425_riscv,
+ csr_2426_riscv,
+ csr_2427_riscv,
+ csr_2428_riscv,
+ csr_2429_riscv,
+ csr_2430_riscv,
+ csr_2431_riscv,
+ csr_2432_riscv,
+ csr_2433_riscv,
+ csr_2434_riscv,
+ csr_2435_riscv,
+ csr_2436_riscv,
+ csr_2437_riscv,
+ csr_2438_riscv,
+ csr_2439_riscv,
+ csr_2440_riscv,
+ csr_2441_riscv,
+ csr_2442_riscv,
+ csr_2443_riscv,
+ csr_2444_riscv,
+ csr_2445_riscv,
+ csr_2446_riscv,
+ csr_2447_riscv,
+ csr_2448_riscv,
+ csr_2449_riscv,
+ csr_2450_riscv,
+ csr_2451_riscv,
+ csr_2452_riscv,
+ csr_2453_riscv,
+ csr_2454_riscv,
+ csr_2455_riscv,
+ csr_2456_riscv,
+ csr_2457_riscv,
+ csr_2458_riscv,
+ csr_2459_riscv,
+ csr_2460_riscv,
+ csr_2461_riscv,
+ csr_2462_riscv,
+ csr_2463_riscv,
+ csr_2464_riscv,
+ csr_2465_riscv,
+ csr_2466_riscv,
+ csr_2467_riscv,
+ csr_2468_riscv,
+ csr_2469_riscv,
+ csr_2470_riscv,
+ csr_2471_riscv,
+ csr_2472_riscv,
+ csr_2473_riscv,
+ csr_2474_riscv,
+ csr_2475_riscv,
+ csr_2476_riscv,
+ csr_2477_riscv,
+ csr_2478_riscv,
+ csr_2479_riscv,
+ csr_2480_riscv,
+ csr_2481_riscv,
+ csr_2482_riscv,
+ csr_2483_riscv,
+ csr_2484_riscv,
+ csr_2485_riscv,
+ csr_2486_riscv,
+ csr_2487_riscv,
+ csr_2488_riscv,
+ csr_2489_riscv,
+ csr_2490_riscv,
+ csr_2491_riscv,
+ csr_2492_riscv,
+ csr_2493_riscv,
+ csr_2494_riscv,
+ csr_2495_riscv,
+ csr_2496_riscv,
+ csr_2497_riscv,
+ csr_2498_riscv,
+ csr_2499_riscv,
+ csr_2500_riscv,
+ csr_2501_riscv,
+ csr_2502_riscv,
+ csr_2503_riscv,
+ csr_2504_riscv,
+ csr_2505_riscv,
+ csr_2506_riscv,
+ csr_2507_riscv,
+ csr_2508_riscv,
+ csr_2509_riscv,
+ csr_2510_riscv,
+ csr_2511_riscv,
+ csr_2512_riscv,
+ csr_2513_riscv,
+ csr_2514_riscv,
+ csr_2515_riscv,
+ csr_2516_riscv,
+ csr_2517_riscv,
+ csr_2518_riscv,
+ csr_2519_riscv,
+ csr_2520_riscv,
+ csr_2521_riscv,
+ csr_2522_riscv,
+ csr_2523_riscv,
+ csr_2524_riscv,
+ csr_2525_riscv,
+ csr_2526_riscv,
+ csr_2527_riscv,
+ csr_2528_riscv,
+ csr_2529_riscv,
+ csr_2530_riscv,
+ csr_2531_riscv,
+ csr_2532_riscv,
+ csr_2533_riscv,
+ csr_2534_riscv,
+ csr_2535_riscv,
+ csr_2536_riscv,
+ csr_2537_riscv,
+ csr_2538_riscv,
+ csr_2539_riscv,
+ csr_2540_riscv,
+ csr_2541_riscv,
+ csr_2542_riscv,
+ csr_2543_riscv,
+ csr_2544_riscv,
+ csr_2545_riscv,
+ csr_2546_riscv,
+ csr_2547_riscv,
+ csr_2548_riscv,
+ csr_2549_riscv,
+ csr_2550_riscv,
+ csr_2551_riscv,
+ csr_2552_riscv,
+ csr_2553_riscv,
+ csr_2554_riscv,
+ csr_2555_riscv,
+ csr_2556_riscv,
+ csr_2557_riscv,
+ csr_2558_riscv,
+ csr_2559_riscv,
+ csr_2560_riscv,
+ csr_2561_riscv,
+ csr_2562_riscv,
+ csr_2563_riscv,
+ csr_2564_riscv,
+ csr_2565_riscv,
+ csr_2566_riscv,
+ csr_2567_riscv,
+ csr_2568_riscv,
+ csr_2569_riscv,
+ csr_2570_riscv,
+ csr_2571_riscv,
+ csr_2572_riscv,
+ csr_2573_riscv,
+ csr_2574_riscv,
+ csr_2575_riscv,
+ csr_2576_riscv,
+ csr_2577_riscv,
+ csr_2578_riscv,
+ csr_2579_riscv,
+ csr_2580_riscv,
+ csr_2581_riscv,
+ csr_2582_riscv,
+ csr_2583_riscv,
+ csr_2584_riscv,
+ csr_2585_riscv,
+ csr_2586_riscv,
+ csr_2587_riscv,
+ csr_2588_riscv,
+ csr_2589_riscv,
+ csr_2590_riscv,
+ csr_2591_riscv,
+ csr_2592_riscv,
+ csr_2593_riscv,
+ csr_2594_riscv,
+ csr_2595_riscv,
+ csr_2596_riscv,
+ csr_2597_riscv,
+ csr_2598_riscv,
+ csr_2599_riscv,
+ csr_2600_riscv,
+ csr_2601_riscv,
+ csr_2602_riscv,
+ csr_2603_riscv,
+ csr_2604_riscv,
+ csr_2605_riscv,
+ csr_2606_riscv,
+ csr_2607_riscv,
+ csr_2608_riscv,
+ csr_2609_riscv,
+ csr_2610_riscv,
+ csr_2611_riscv,
+ csr_2612_riscv,
+ csr_2613_riscv,
+ csr_2614_riscv,
+ csr_2615_riscv,
+ csr_2616_riscv,
+ csr_2617_riscv,
+ csr_2618_riscv,
+ csr_2619_riscv,
+ csr_2620_riscv,
+ csr_2621_riscv,
+ csr_2622_riscv,
+ csr_2623_riscv,
+ csr_2624_riscv,
+ csr_2625_riscv,
+ csr_2626_riscv,
+ csr_2627_riscv,
+ csr_2628_riscv,
+ csr_2629_riscv,
+ csr_2630_riscv,
+ csr_2631_riscv,
+ csr_2632_riscv,
+ csr_2633_riscv,
+ csr_2634_riscv,
+ csr_2635_riscv,
+ csr_2636_riscv,
+ csr_2637_riscv,
+ csr_2638_riscv,
+ csr_2639_riscv,
+ csr_2640_riscv,
+ csr_2641_riscv,
+ csr_2642_riscv,
+ csr_2643_riscv,
+ csr_2644_riscv,
+ csr_2645_riscv,
+ csr_2646_riscv,
+ csr_2647_riscv,
+ csr_2648_riscv,
+ csr_2649_riscv,
+ csr_2650_riscv,
+ csr_2651_riscv,
+ csr_2652_riscv,
+ csr_2653_riscv,
+ csr_2654_riscv,
+ csr_2655_riscv,
+ csr_2656_riscv,
+ csr_2657_riscv,
+ csr_2658_riscv,
+ csr_2659_riscv,
+ csr_2660_riscv,
+ csr_2661_riscv,
+ csr_2662_riscv,
+ csr_2663_riscv,
+ csr_2664_riscv,
+ csr_2665_riscv,
+ csr_2666_riscv,
+ csr_2667_riscv,
+ csr_2668_riscv,
+ csr_2669_riscv,
+ csr_2670_riscv,
+ csr_2671_riscv,
+ csr_2672_riscv,
+ csr_2673_riscv,
+ csr_2674_riscv,
+ csr_2675_riscv,
+ csr_2676_riscv,
+ csr_2677_riscv,
+ csr_2678_riscv,
+ csr_2679_riscv,
+ csr_2680_riscv,
+ csr_2681_riscv,
+ csr_2682_riscv,
+ csr_2683_riscv,
+ csr_2684_riscv,
+ csr_2685_riscv,
+ csr_2686_riscv,
+ csr_2687_riscv,
+ csr_2688_riscv,
+ csr_2689_riscv,
+ csr_2690_riscv,
+ csr_2691_riscv,
+ csr_2692_riscv,
+ csr_2693_riscv,
+ csr_2694_riscv,
+ csr_2695_riscv,
+ csr_2696_riscv,
+ csr_2697_riscv,
+ csr_2698_riscv,
+ csr_2699_riscv,
+ csr_2700_riscv,
+ csr_2701_riscv,
+ csr_2702_riscv,
+ csr_2703_riscv,
+ csr_2704_riscv,
+ csr_2705_riscv,
+ csr_2706_riscv,
+ csr_2707_riscv,
+ csr_2708_riscv,
+ csr_2709_riscv,
+ csr_2710_riscv,
+ csr_2711_riscv,
+ csr_2712_riscv,
+ csr_2713_riscv,
+ csr_2714_riscv,
+ csr_2715_riscv,
+ csr_2716_riscv,
+ csr_2717_riscv,
+ csr_2718_riscv,
+ csr_2719_riscv,
+ csr_2720_riscv,
+ csr_2721_riscv,
+ csr_2722_riscv,
+ csr_2723_riscv,
+ csr_2724_riscv,
+ csr_2725_riscv,
+ csr_2726_riscv,
+ csr_2727_riscv,
+ csr_2728_riscv,
+ csr_2729_riscv,
+ csr_2730_riscv,
+ csr_2731_riscv,
+ csr_2732_riscv,
+ csr_2733_riscv,
+ csr_2734_riscv,
+ csr_2735_riscv,
+ csr_2736_riscv,
+ csr_2737_riscv,
+ csr_2738_riscv,
+ csr_2739_riscv,
+ csr_2740_riscv,
+ csr_2741_riscv,
+ csr_2742_riscv,
+ csr_2743_riscv,
+ csr_2744_riscv,
+ csr_2745_riscv,
+ csr_2746_riscv,
+ csr_2747_riscv,
+ csr_2748_riscv,
+ csr_2749_riscv,
+ csr_2750_riscv,
+ csr_2751_riscv,
+ csr_2752_riscv,
+ csr_2753_riscv,
+ csr_2754_riscv,
+ csr_2755_riscv,
+ csr_2756_riscv,
+ csr_2757_riscv,
+ csr_2758_riscv,
+ csr_2759_riscv,
+ csr_2760_riscv,
+ csr_2761_riscv,
+ csr_2762_riscv,
+ csr_2763_riscv,
+ csr_2764_riscv,
+ csr_2765_riscv,
+ csr_2766_riscv,
+ csr_2767_riscv,
+ csr_2768_riscv,
+ csr_2769_riscv,
+ csr_2770_riscv,
+ csr_2771_riscv,
+ csr_2772_riscv,
+ csr_2773_riscv,
+ csr_2774_riscv,
+ csr_2775_riscv,
+ csr_2776_riscv,
+ csr_2777_riscv,
+ csr_2778_riscv,
+ csr_2779_riscv,
+ csr_2780_riscv,
+ csr_2781_riscv,
+ csr_2782_riscv,
+ csr_2783_riscv,
+ csr_2784_riscv,
+ csr_2785_riscv,
+ csr_2786_riscv,
+ csr_2787_riscv,
+ csr_2788_riscv,
+ csr_2789_riscv,
+ csr_2790_riscv,
+ csr_2791_riscv,
+ csr_2792_riscv,
+ csr_2793_riscv,
+ csr_2794_riscv,
+ csr_2795_riscv,
+ csr_2796_riscv,
+ csr_2797_riscv,
+ csr_2798_riscv,
+ csr_2799_riscv,
+ csr_2800_riscv,
+ csr_2801_riscv,
+ csr_2802_riscv,
+ csr_2803_riscv,
+ csr_2804_riscv,
+ csr_2805_riscv,
+ csr_2806_riscv,
+ csr_2807_riscv,
+ csr_2808_riscv,
+ csr_2809_riscv,
+ csr_2810_riscv,
+ csr_2811_riscv,
+ csr_2812_riscv,
+ csr_2813_riscv,
+ csr_2814_riscv,
+ csr_2815_riscv,
+ csr_2816_riscv,
+ csr_2817_riscv,
+ csr_2818_riscv,
+ csr_2819_riscv,
+ csr_2820_riscv,
+ csr_2821_riscv,
+ csr_2822_riscv,
+ csr_2823_riscv,
+ csr_2824_riscv,
+ csr_2825_riscv,
+ csr_2826_riscv,
+ csr_2827_riscv,
+ csr_2828_riscv,
+ csr_2829_riscv,
+ csr_2830_riscv,
+ csr_2831_riscv,
+ csr_2832_riscv,
+ csr_2833_riscv,
+ csr_2834_riscv,
+ csr_2835_riscv,
+ csr_2836_riscv,
+ csr_2837_riscv,
+ csr_2838_riscv,
+ csr_2839_riscv,
+ csr_2840_riscv,
+ csr_2841_riscv,
+ csr_2842_riscv,
+ csr_2843_riscv,
+ csr_2844_riscv,
+ csr_2845_riscv,
+ csr_2846_riscv,
+ csr_2847_riscv,
+ csr_2848_riscv,
+ csr_2849_riscv,
+ csr_2850_riscv,
+ csr_2851_riscv,
+ csr_2852_riscv,
+ csr_2853_riscv,
+ csr_2854_riscv,
+ csr_2855_riscv,
+ csr_2856_riscv,
+ csr_2857_riscv,
+ csr_2858_riscv,
+ csr_2859_riscv,
+ csr_2860_riscv,
+ csr_2861_riscv,
+ csr_2862_riscv,
+ csr_2863_riscv,
+ csr_2864_riscv,
+ csr_2865_riscv,
+ csr_2866_riscv,
+ csr_2867_riscv,
+ csr_2868_riscv,
+ csr_2869_riscv,
+ csr_2870_riscv,
+ csr_2871_riscv,
+ csr_2872_riscv,
+ csr_2873_riscv,
+ csr_2874_riscv,
+ csr_2875_riscv,
+ csr_2876_riscv,
+ csr_2877_riscv,
+ csr_2878_riscv,
+ csr_2879_riscv,
+ csr_2880_riscv,
+ csr_2881_riscv,
+ csr_2882_riscv,
+ csr_2883_riscv,
+ csr_2884_riscv,
+ csr_2885_riscv,
+ csr_2886_riscv,
+ csr_2887_riscv,
+ csr_2888_riscv,
+ csr_2889_riscv,
+ csr_2890_riscv,
+ csr_2891_riscv,
+ csr_2892_riscv,
+ csr_2893_riscv,
+ csr_2894_riscv,
+ csr_2895_riscv,
+ csr_2896_riscv,
+ csr_2897_riscv,
+ csr_2898_riscv,
+ csr_2899_riscv,
+ csr_2900_riscv,
+ csr_2901_riscv,
+ csr_2902_riscv,
+ csr_2903_riscv,
+ csr_2904_riscv,
+ csr_2905_riscv,
+ csr_2906_riscv,
+ csr_2907_riscv,
+ csr_2908_riscv,
+ csr_2909_riscv,
+ csr_2910_riscv,
+ csr_2911_riscv,
+ csr_2912_riscv,
+ csr_2913_riscv,
+ csr_2914_riscv,
+ csr_2915_riscv,
+ csr_2916_riscv,
+ csr_2917_riscv,
+ csr_2918_riscv,
+ csr_2919_riscv,
+ csr_2920_riscv,
+ csr_2921_riscv,
+ csr_2922_riscv,
+ csr_2923_riscv,
+ csr_2924_riscv,
+ csr_2925_riscv,
+ csr_2926_riscv,
+ csr_2927_riscv,
+ csr_2928_riscv,
+ csr_2929_riscv,
+ csr_2930_riscv,
+ csr_2931_riscv,
+ csr_2932_riscv,
+ csr_2933_riscv,
+ csr_2934_riscv,
+ csr_2935_riscv,
+ csr_2936_riscv,
+ csr_2937_riscv,
+ csr_2938_riscv,
+ csr_2939_riscv,
+ csr_2940_riscv,
+ csr_2941_riscv,
+ csr_2942_riscv,
+ csr_2943_riscv,
+ csr_2944_riscv,
+ csr_2945_riscv,
+ csr_2946_riscv,
+ csr_2947_riscv,
+ csr_2948_riscv,
+ csr_2949_riscv,
+ csr_2950_riscv,
+ csr_2951_riscv,
+ csr_2952_riscv,
+ csr_2953_riscv,
+ csr_2954_riscv,
+ csr_2955_riscv,
+ csr_2956_riscv,
+ csr_2957_riscv,
+ csr_2958_riscv,
+ csr_2959_riscv,
+ csr_2960_riscv,
+ csr_2961_riscv,
+ csr_2962_riscv,
+ csr_2963_riscv,
+ csr_2964_riscv,
+ csr_2965_riscv,
+ csr_2966_riscv,
+ csr_2967_riscv,
+ csr_2968_riscv,
+ csr_2969_riscv,
+ csr_2970_riscv,
+ csr_2971_riscv,
+ csr_2972_riscv,
+ csr_2973_riscv,
+ csr_2974_riscv,
+ csr_2975_riscv,
+ csr_2976_riscv,
+ csr_2977_riscv,
+ csr_2978_riscv,
+ csr_2979_riscv,
+ csr_2980_riscv,
+ csr_2981_riscv,
+ csr_2982_riscv,
+ csr_2983_riscv,
+ csr_2984_riscv,
+ csr_2985_riscv,
+ csr_2986_riscv,
+ csr_2987_riscv,
+ csr_2988_riscv,
+ csr_2989_riscv,
+ csr_2990_riscv,
+ csr_2991_riscv,
+ csr_2992_riscv,
+ csr_2993_riscv,
+ csr_2994_riscv,
+ csr_2995_riscv,
+ csr_2996_riscv,
+ csr_2997_riscv,
+ csr_2998_riscv,
+ csr_2999_riscv,
+ csr_3000_riscv,
+ csr_3001_riscv,
+ csr_3002_riscv,
+ csr_3003_riscv,
+ csr_3004_riscv,
+ csr_3005_riscv,
+ csr_3006_riscv,
+ csr_3007_riscv,
+ csr_3008_riscv,
+ csr_3009_riscv,
+ csr_3010_riscv,
+ csr_3011_riscv,
+ csr_3012_riscv,
+ csr_3013_riscv,
+ csr_3014_riscv,
+ csr_3015_riscv,
+ csr_3016_riscv,
+ csr_3017_riscv,
+ csr_3018_riscv,
+ csr_3019_riscv,
+ csr_3020_riscv,
+ csr_3021_riscv,
+ csr_3022_riscv,
+ csr_3023_riscv,
+ csr_3024_riscv,
+ csr_3025_riscv,
+ csr_3026_riscv,
+ csr_3027_riscv,
+ csr_3028_riscv,
+ csr_3029_riscv,
+ csr_3030_riscv,
+ csr_3031_riscv,
+ csr_3032_riscv,
+ csr_3033_riscv,
+ csr_3034_riscv,
+ csr_3035_riscv,
+ csr_3036_riscv,
+ csr_3037_riscv,
+ csr_3038_riscv,
+ csr_3039_riscv,
+ csr_3040_riscv,
+ csr_3041_riscv,
+ csr_3042_riscv,
+ csr_3043_riscv,
+ csr_3044_riscv,
+ csr_3045_riscv,
+ csr_3046_riscv,
+ csr_3047_riscv,
+ csr_3048_riscv,
+ csr_3049_riscv,
+ csr_3050_riscv,
+ csr_3051_riscv,
+ csr_3052_riscv,
+ csr_3053_riscv,
+ csr_3054_riscv,
+ csr_3055_riscv,
+ csr_3056_riscv,
+ csr_3057_riscv,
+ csr_3058_riscv,
+ csr_3059_riscv,
+ csr_3060_riscv,
+ csr_3061_riscv,
+ csr_3062_riscv,
+ csr_3063_riscv,
+ csr_3064_riscv,
+ csr_3065_riscv,
+ csr_3066_riscv,
+ csr_3067_riscv,
+ csr_3068_riscv,
+ csr_3069_riscv,
+ csr_3070_riscv,
+ csr_3071_riscv,
+ csr_3072_riscv,
+ csr_3073_riscv,
+ csr_3074_riscv,
+ csr_3075_riscv,
+ csr_3076_riscv,
+ csr_3077_riscv,
+ csr_3078_riscv,
+ csr_3079_riscv,
+ csr_3080_riscv,
+ csr_3081_riscv,
+ csr_3082_riscv,
+ csr_3083_riscv,
+ csr_3084_riscv,
+ csr_3085_riscv,
+ csr_3086_riscv,
+ csr_3087_riscv,
+ csr_3088_riscv,
+ csr_3089_riscv,
+ csr_3090_riscv,
+ csr_3091_riscv,
+ csr_3092_riscv,
+ csr_3093_riscv,
+ csr_3094_riscv,
+ csr_3095_riscv,
+ csr_3096_riscv,
+ csr_3097_riscv,
+ csr_3098_riscv,
+ csr_3099_riscv,
+ csr_3100_riscv,
+ csr_3101_riscv,
+ csr_3102_riscv,
+ csr_3103_riscv,
+ csr_3104_riscv,
+ csr_3105_riscv,
+ csr_3106_riscv,
+ csr_3107_riscv,
+ csr_3108_riscv,
+ csr_3109_riscv,
+ csr_3110_riscv,
+ csr_3111_riscv,
+ csr_3112_riscv,
+ csr_3113_riscv,
+ csr_3114_riscv,
+ csr_3115_riscv,
+ csr_3116_riscv,
+ csr_3117_riscv,
+ csr_3118_riscv,
+ csr_3119_riscv,
+ csr_3120_riscv,
+ csr_3121_riscv,
+ csr_3122_riscv,
+ csr_3123_riscv,
+ csr_3124_riscv,
+ csr_3125_riscv,
+ csr_3126_riscv,
+ csr_3127_riscv,
+ csr_3128_riscv,
+ csr_3129_riscv,
+ csr_3130_riscv,
+ csr_3131_riscv,
+ csr_3132_riscv,
+ csr_3133_riscv,
+ csr_3134_riscv,
+ csr_3135_riscv,
+ csr_3136_riscv,
+ csr_3137_riscv,
+ csr_3138_riscv,
+ csr_3139_riscv,
+ csr_3140_riscv,
+ csr_3141_riscv,
+ csr_3142_riscv,
+ csr_3143_riscv,
+ csr_3144_riscv,
+ csr_3145_riscv,
+ csr_3146_riscv,
+ csr_3147_riscv,
+ csr_3148_riscv,
+ csr_3149_riscv,
+ csr_3150_riscv,
+ csr_3151_riscv,
+ csr_3152_riscv,
+ csr_3153_riscv,
+ csr_3154_riscv,
+ csr_3155_riscv,
+ csr_3156_riscv,
+ csr_3157_riscv,
+ csr_3158_riscv,
+ csr_3159_riscv,
+ csr_3160_riscv,
+ csr_3161_riscv,
+ csr_3162_riscv,
+ csr_3163_riscv,
+ csr_3164_riscv,
+ csr_3165_riscv,
+ csr_3166_riscv,
+ csr_3167_riscv,
+ csr_3168_riscv,
+ csr_3169_riscv,
+ csr_3170_riscv,
+ csr_3171_riscv,
+ csr_3172_riscv,
+ csr_3173_riscv,
+ csr_3174_riscv,
+ csr_3175_riscv,
+ csr_3176_riscv,
+ csr_3177_riscv,
+ csr_3178_riscv,
+ csr_3179_riscv,
+ csr_3180_riscv,
+ csr_3181_riscv,
+ csr_3182_riscv,
+ csr_3183_riscv,
+ csr_3184_riscv,
+ csr_3185_riscv,
+ csr_3186_riscv,
+ csr_3187_riscv,
+ csr_3188_riscv,
+ csr_3189_riscv,
+ csr_3190_riscv,
+ csr_3191_riscv,
+ csr_3192_riscv,
+ csr_3193_riscv,
+ csr_3194_riscv,
+ csr_3195_riscv,
+ csr_3196_riscv,
+ csr_3197_riscv,
+ csr_3198_riscv,
+ csr_3199_riscv,
+ csr_3200_riscv,
+ csr_3201_riscv,
+ csr_3202_riscv,
+ csr_3203_riscv,
+ csr_3204_riscv,
+ csr_3205_riscv,
+ csr_3206_riscv,
+ csr_3207_riscv,
+ csr_3208_riscv,
+ csr_3209_riscv,
+ csr_3210_riscv,
+ csr_3211_riscv,
+ csr_3212_riscv,
+ csr_3213_riscv,
+ csr_3214_riscv,
+ csr_3215_riscv,
+ csr_3216_riscv,
+ csr_3217_riscv,
+ csr_3218_riscv,
+ csr_3219_riscv,
+ csr_3220_riscv,
+ csr_3221_riscv,
+ csr_3222_riscv,
+ csr_3223_riscv,
+ csr_3224_riscv,
+ csr_3225_riscv,
+ csr_3226_riscv,
+ csr_3227_riscv,
+ csr_3228_riscv,
+ csr_3229_riscv,
+ csr_3230_riscv,
+ csr_3231_riscv,
+ csr_3232_riscv,
+ csr_3233_riscv,
+ csr_3234_riscv,
+ csr_3235_riscv,
+ csr_3236_riscv,
+ csr_3237_riscv,
+ csr_3238_riscv,
+ csr_3239_riscv,
+ csr_3240_riscv,
+ csr_3241_riscv,
+ csr_3242_riscv,
+ csr_3243_riscv,
+ csr_3244_riscv,
+ csr_3245_riscv,
+ csr_3246_riscv,
+ csr_3247_riscv,
+ csr_3248_riscv,
+ csr_3249_riscv,
+ csr_3250_riscv,
+ csr_3251_riscv,
+ csr_3252_riscv,
+ csr_3253_riscv,
+ csr_3254_riscv,
+ csr_3255_riscv,
+ csr_3256_riscv,
+ csr_3257_riscv,
+ csr_3258_riscv,
+ csr_3259_riscv,
+ csr_3260_riscv,
+ csr_3261_riscv,
+ csr_3262_riscv,
+ csr_3263_riscv,
+ csr_3264_riscv,
+ csr_3265_riscv,
+ csr_3266_riscv,
+ csr_3267_riscv,
+ csr_3268_riscv,
+ csr_3269_riscv,
+ csr_3270_riscv,
+ csr_3271_riscv,
+ csr_3272_riscv,
+ csr_3273_riscv,
+ csr_3274_riscv,
+ csr_3275_riscv,
+ csr_3276_riscv,
+ csr_3277_riscv,
+ csr_3278_riscv,
+ csr_3279_riscv,
+ csr_3280_riscv,
+ csr_3281_riscv,
+ csr_3282_riscv,
+ csr_3283_riscv,
+ csr_3284_riscv,
+ csr_3285_riscv,
+ csr_3286_riscv,
+ csr_3287_riscv,
+ csr_3288_riscv,
+ csr_3289_riscv,
+ csr_3290_riscv,
+ csr_3291_riscv,
+ csr_3292_riscv,
+ csr_3293_riscv,
+ csr_3294_riscv,
+ csr_3295_riscv,
+ csr_3296_riscv,
+ csr_3297_riscv,
+ csr_3298_riscv,
+ csr_3299_riscv,
+ csr_3300_riscv,
+ csr_3301_riscv,
+ csr_3302_riscv,
+ csr_3303_riscv,
+ csr_3304_riscv,
+ csr_3305_riscv,
+ csr_3306_riscv,
+ csr_3307_riscv,
+ csr_3308_riscv,
+ csr_3309_riscv,
+ csr_3310_riscv,
+ csr_3311_riscv,
+ csr_3312_riscv,
+ csr_3313_riscv,
+ csr_3314_riscv,
+ csr_3315_riscv,
+ csr_3316_riscv,
+ csr_3317_riscv,
+ csr_3318_riscv,
+ csr_3319_riscv,
+ csr_3320_riscv,
+ csr_3321_riscv,
+ csr_3322_riscv,
+ csr_3323_riscv,
+ csr_3324_riscv,
+ csr_3325_riscv,
+ csr_3326_riscv,
+ csr_3327_riscv,
+ csr_3328_riscv,
+ csr_3329_riscv,
+ csr_3330_riscv,
+ csr_3331_riscv,
+ csr_3332_riscv,
+ csr_3333_riscv,
+ csr_3334_riscv,
+ csr_3335_riscv,
+ csr_3336_riscv,
+ csr_3337_riscv,
+ csr_3338_riscv,
+ csr_3339_riscv,
+ csr_3340_riscv,
+ csr_3341_riscv,
+ csr_3342_riscv,
+ csr_3343_riscv,
+ csr_3344_riscv,
+ csr_3345_riscv,
+ csr_3346_riscv,
+ csr_3347_riscv,
+ csr_3348_riscv,
+ csr_3349_riscv,
+ csr_3350_riscv,
+ csr_3351_riscv,
+ csr_3352_riscv,
+ csr_3353_riscv,
+ csr_3354_riscv,
+ csr_3355_riscv,
+ csr_3356_riscv,
+ csr_3357_riscv,
+ csr_3358_riscv,
+ csr_3359_riscv,
+ csr_3360_riscv,
+ csr_3361_riscv,
+ csr_3362_riscv,
+ csr_3363_riscv,
+ csr_3364_riscv,
+ csr_3365_riscv,
+ csr_3366_riscv,
+ csr_3367_riscv,
+ csr_3368_riscv,
+ csr_3369_riscv,
+ csr_3370_riscv,
+ csr_3371_riscv,
+ csr_3372_riscv,
+ csr_3373_riscv,
+ csr_3374_riscv,
+ csr_3375_riscv,
+ csr_3376_riscv,
+ csr_3377_riscv,
+ csr_3378_riscv,
+ csr_3379_riscv,
+ csr_3380_riscv,
+ csr_3381_riscv,
+ csr_3382_riscv,
+ csr_3383_riscv,
+ csr_3384_riscv,
+ csr_3385_riscv,
+ csr_3386_riscv,
+ csr_3387_riscv,
+ csr_3388_riscv,
+ csr_3389_riscv,
+ csr_3390_riscv,
+ csr_3391_riscv,
+ csr_3392_riscv,
+ csr_3393_riscv,
+ csr_3394_riscv,
+ csr_3395_riscv,
+ csr_3396_riscv,
+ csr_3397_riscv,
+ csr_3398_riscv,
+ csr_3399_riscv,
+ csr_3400_riscv,
+ csr_3401_riscv,
+ csr_3402_riscv,
+ csr_3403_riscv,
+ csr_3404_riscv,
+ csr_3405_riscv,
+ csr_3406_riscv,
+ csr_3407_riscv,
+ csr_3408_riscv,
+ csr_3409_riscv,
+ csr_3410_riscv,
+ csr_3411_riscv,
+ csr_3412_riscv,
+ csr_3413_riscv,
+ csr_3414_riscv,
+ csr_3415_riscv,
+ csr_3416_riscv,
+ csr_3417_riscv,
+ csr_3418_riscv,
+ csr_3419_riscv,
+ csr_3420_riscv,
+ csr_3421_riscv,
+ csr_3422_riscv,
+ csr_3423_riscv,
+ csr_3424_riscv,
+ csr_3425_riscv,
+ csr_3426_riscv,
+ csr_3427_riscv,
+ csr_3428_riscv,
+ csr_3429_riscv,
+ csr_3430_riscv,
+ csr_3431_riscv,
+ csr_3432_riscv,
+ csr_3433_riscv,
+ csr_3434_riscv,
+ csr_3435_riscv,
+ csr_3436_riscv,
+ csr_3437_riscv,
+ csr_3438_riscv,
+ csr_3439_riscv,
+ csr_3440_riscv,
+ csr_3441_riscv,
+ csr_3442_riscv,
+ csr_3443_riscv,
+ csr_3444_riscv,
+ csr_3445_riscv,
+ csr_3446_riscv,
+ csr_3447_riscv,
+ csr_3448_riscv,
+ csr_3449_riscv,
+ csr_3450_riscv,
+ csr_3451_riscv,
+ csr_3452_riscv,
+ csr_3453_riscv,
+ csr_3454_riscv,
+ csr_3455_riscv,
+ csr_3456_riscv,
+ csr_3457_riscv,
+ csr_3458_riscv,
+ csr_3459_riscv,
+ csr_3460_riscv,
+ csr_3461_riscv,
+ csr_3462_riscv,
+ csr_3463_riscv,
+ csr_3464_riscv,
+ csr_3465_riscv,
+ csr_3466_riscv,
+ csr_3467_riscv,
+ csr_3468_riscv,
+ csr_3469_riscv,
+ csr_3470_riscv,
+ csr_3471_riscv,
+ csr_3472_riscv,
+ csr_3473_riscv,
+ csr_3474_riscv,
+ csr_3475_riscv,
+ csr_3476_riscv,
+ csr_3477_riscv,
+ csr_3478_riscv,
+ csr_3479_riscv,
+ csr_3480_riscv,
+ csr_3481_riscv,
+ csr_3482_riscv,
+ csr_3483_riscv,
+ csr_3484_riscv,
+ csr_3485_riscv,
+ csr_3486_riscv,
+ csr_3487_riscv,
+ csr_3488_riscv,
+ csr_3489_riscv,
+ csr_3490_riscv,
+ csr_3491_riscv,
+ csr_3492_riscv,
+ csr_3493_riscv,
+ csr_3494_riscv,
+ csr_3495_riscv,
+ csr_3496_riscv,
+ csr_3497_riscv,
+ csr_3498_riscv,
+ csr_3499_riscv,
+ csr_3500_riscv,
+ csr_3501_riscv,
+ csr_3502_riscv,
+ csr_3503_riscv,
+ csr_3504_riscv,
+ csr_3505_riscv,
+ csr_3506_riscv,
+ csr_3507_riscv,
+ csr_3508_riscv,
+ csr_3509_riscv,
+ csr_3510_riscv,
+ csr_3511_riscv,
+ csr_3512_riscv,
+ csr_3513_riscv,
+ csr_3514_riscv,
+ csr_3515_riscv,
+ csr_3516_riscv,
+ csr_3517_riscv,
+ csr_3518_riscv,
+ csr_3519_riscv,
+ csr_3520_riscv,
+ csr_3521_riscv,
+ csr_3522_riscv,
+ csr_3523_riscv,
+ csr_3524_riscv,
+ csr_3525_riscv,
+ csr_3526_riscv,
+ csr_3527_riscv,
+ csr_3528_riscv,
+ csr_3529_riscv,
+ csr_3530_riscv,
+ csr_3531_riscv,
+ csr_3532_riscv,
+ csr_3533_riscv,
+ csr_3534_riscv,
+ csr_3535_riscv,
+ csr_3536_riscv,
+ csr_3537_riscv,
+ csr_3538_riscv,
+ csr_3539_riscv,
+ csr_3540_riscv,
+ csr_3541_riscv,
+ csr_3542_riscv,
+ csr_3543_riscv,
+ csr_3544_riscv,
+ csr_3545_riscv,
+ csr_3546_riscv,
+ csr_3547_riscv,
+ csr_3548_riscv,
+ csr_3549_riscv,
+ csr_3550_riscv,
+ csr_3551_riscv,
+ csr_3552_riscv,
+ csr_3553_riscv,
+ csr_3554_riscv,
+ csr_3555_riscv,
+ csr_3556_riscv,
+ csr_3557_riscv,
+ csr_3558_riscv,
+ csr_3559_riscv,
+ csr_3560_riscv,
+ csr_3561_riscv,
+ csr_3562_riscv,
+ csr_3563_riscv,
+ csr_3564_riscv,
+ csr_3565_riscv,
+ csr_3566_riscv,
+ csr_3567_riscv,
+ csr_3568_riscv,
+ csr_3569_riscv,
+ csr_3570_riscv,
+ csr_3571_riscv,
+ csr_3572_riscv,
+ csr_3573_riscv,
+ csr_3574_riscv,
+ csr_3575_riscv,
+ csr_3576_riscv,
+ csr_3577_riscv,
+ csr_3578_riscv,
+ csr_3579_riscv,
+ csr_3580_riscv,
+ csr_3581_riscv,
+ csr_3582_riscv,
+ csr_3583_riscv,
+ csr_3584_riscv,
+ csr_3585_riscv,
+ csr_3586_riscv,
+ csr_3587_riscv,
+ csr_3588_riscv,
+ csr_3589_riscv,
+ csr_3590_riscv,
+ csr_3591_riscv,
+ csr_3592_riscv,
+ csr_3593_riscv,
+ csr_3594_riscv,
+ csr_3595_riscv,
+ csr_3596_riscv,
+ csr_3597_riscv,
+ csr_3598_riscv,
+ csr_3599_riscv,
+ csr_3600_riscv,
+ csr_3601_riscv,
+ csr_3602_riscv,
+ csr_3603_riscv,
+ csr_3604_riscv,
+ csr_3605_riscv,
+ csr_3606_riscv,
+ csr_3607_riscv,
+ csr_3608_riscv,
+ csr_3609_riscv,
+ csr_3610_riscv,
+ csr_3611_riscv,
+ csr_3612_riscv,
+ csr_3613_riscv,
+ csr_3614_riscv,
+ csr_3615_riscv,
+ csr_3616_riscv,
+ csr_3617_riscv,
+ csr_3618_riscv,
+ csr_3619_riscv,
+ csr_3620_riscv,
+ csr_3621_riscv,
+ csr_3622_riscv,
+ csr_3623_riscv,
+ csr_3624_riscv,
+ csr_3625_riscv,
+ csr_3626_riscv,
+ csr_3627_riscv,
+ csr_3628_riscv,
+ csr_3629_riscv,
+ csr_3630_riscv,
+ csr_3631_riscv,
+ csr_3632_riscv,
+ csr_3633_riscv,
+ csr_3634_riscv,
+ csr_3635_riscv,
+ csr_3636_riscv,
+ csr_3637_riscv,
+ csr_3638_riscv,
+ csr_3639_riscv,
+ csr_3640_riscv,
+ csr_3641_riscv,
+ csr_3642_riscv,
+ csr_3643_riscv,
+ csr_3644_riscv,
+ csr_3645_riscv,
+ csr_3646_riscv,
+ csr_3647_riscv,
+ csr_3648_riscv,
+ csr_3649_riscv,
+ csr_3650_riscv,
+ csr_3651_riscv,
+ csr_3652_riscv,
+ csr_3653_riscv,
+ csr_3654_riscv,
+ csr_3655_riscv,
+ csr_3656_riscv,
+ csr_3657_riscv,
+ csr_3658_riscv,
+ csr_3659_riscv,
+ csr_3660_riscv,
+ csr_3661_riscv,
+ csr_3662_riscv,
+ csr_3663_riscv,
+ csr_3664_riscv,
+ csr_3665_riscv,
+ csr_3666_riscv,
+ csr_3667_riscv,
+ csr_3668_riscv,
+ csr_3669_riscv,
+ csr_3670_riscv,
+ csr_3671_riscv,
+ csr_3672_riscv,
+ csr_3673_riscv,
+ csr_3674_riscv,
+ csr_3675_riscv,
+ csr_3676_riscv,
+ csr_3677_riscv,
+ csr_3678_riscv,
+ csr_3679_riscv,
+ csr_3680_riscv,
+ csr_3681_riscv,
+ csr_3682_riscv,
+ csr_3683_riscv,
+ csr_3684_riscv,
+ csr_3685_riscv,
+ csr_3686_riscv,
+ csr_3687_riscv,
+ csr_3688_riscv,
+ csr_3689_riscv,
+ csr_3690_riscv,
+ csr_3691_riscv,
+ csr_3692_riscv,
+ csr_3693_riscv,
+ csr_3694_riscv,
+ csr_3695_riscv,
+ csr_3696_riscv,
+ csr_3697_riscv,
+ csr_3698_riscv,
+ csr_3699_riscv,
+ csr_3700_riscv,
+ csr_3701_riscv,
+ csr_3702_riscv,
+ csr_3703_riscv,
+ csr_3704_riscv,
+ csr_3705_riscv,
+ csr_3706_riscv,
+ csr_3707_riscv,
+ csr_3708_riscv,
+ csr_3709_riscv,
+ csr_3710_riscv,
+ csr_3711_riscv,
+ csr_3712_riscv,
+ csr_3713_riscv,
+ csr_3714_riscv,
+ csr_3715_riscv,
+ csr_3716_riscv,
+ csr_3717_riscv,
+ csr_3718_riscv,
+ csr_3719_riscv,
+ csr_3720_riscv,
+ csr_3721_riscv,
+ csr_3722_riscv,
+ csr_3723_riscv,
+ csr_3724_riscv,
+ csr_3725_riscv,
+ csr_3726_riscv,
+ csr_3727_riscv,
+ csr_3728_riscv,
+ csr_3729_riscv,
+ csr_3730_riscv,
+ csr_3731_riscv,
+ csr_3732_riscv,
+ csr_3733_riscv,
+ csr_3734_riscv,
+ csr_3735_riscv,
+ csr_3736_riscv,
+ csr_3737_riscv,
+ csr_3738_riscv,
+ csr_3739_riscv,
+ csr_3740_riscv,
+ csr_3741_riscv,
+ csr_3742_riscv,
+ csr_3743_riscv,
+ csr_3744_riscv,
+ csr_3745_riscv,
+ csr_3746_riscv,
+ csr_3747_riscv,
+ csr_3748_riscv,
+ csr_3749_riscv,
+ csr_3750_riscv,
+ csr_3751_riscv,
+ csr_3752_riscv,
+ csr_3753_riscv,
+ csr_3754_riscv,
+ csr_3755_riscv,
+ csr_3756_riscv,
+ csr_3757_riscv,
+ csr_3758_riscv,
+ csr_3759_riscv,
+ csr_3760_riscv,
+ csr_3761_riscv,
+ csr_3762_riscv,
+ csr_3763_riscv,
+ csr_3764_riscv,
+ csr_3765_riscv,
+ csr_3766_riscv,
+ csr_3767_riscv,
+ csr_3768_riscv,
+ csr_3769_riscv,
+ csr_3770_riscv,
+ csr_3771_riscv,
+ csr_3772_riscv,
+ csr_3773_riscv,
+ csr_3774_riscv,
+ csr_3775_riscv,
+ csr_3776_riscv,
+ csr_3777_riscv,
+ csr_3778_riscv,
+ csr_3779_riscv,
+ csr_3780_riscv,
+ csr_3781_riscv,
+ csr_3782_riscv,
+ csr_3783_riscv,
+ csr_3784_riscv,
+ csr_3785_riscv,
+ csr_3786_riscv,
+ csr_3787_riscv,
+ csr_3788_riscv,
+ csr_3789_riscv,
+ csr_3790_riscv,
+ csr_3791_riscv,
+ csr_3792_riscv,
+ csr_3793_riscv,
+ csr_3794_riscv,
+ csr_3795_riscv,
+ csr_3796_riscv,
+ csr_3797_riscv,
+ csr_3798_riscv,
+ csr_3799_riscv,
+ csr_3800_riscv,
+ csr_3801_riscv,
+ csr_3802_riscv,
+ csr_3803_riscv,
+ csr_3804_riscv,
+ csr_3805_riscv,
+ csr_3806_riscv,
+ csr_3807_riscv,
+ csr_3808_riscv,
+ csr_3809_riscv,
+ csr_3810_riscv,
+ csr_3811_riscv,
+ csr_3812_riscv,
+ csr_3813_riscv,
+ csr_3814_riscv,
+ csr_3815_riscv,
+ csr_3816_riscv,
+ csr_3817_riscv,
+ csr_3818_riscv,
+ csr_3819_riscv,
+ csr_3820_riscv,
+ csr_3821_riscv,
+ csr_3822_riscv,
+ csr_3823_riscv,
+ csr_3824_riscv,
+ csr_3825_riscv,
+ csr_3826_riscv,
+ csr_3827_riscv,
+ csr_3828_riscv,
+ csr_3829_riscv,
+ csr_3830_riscv,
+ csr_3831_riscv,
+ csr_3832_riscv,
+ csr_3833_riscv,
+ csr_3834_riscv,
+ csr_3835_riscv,
+ csr_3836_riscv,
+ csr_3837_riscv,
+ csr_3838_riscv,
+ csr_3839_riscv,
+ csr_3840_riscv,
+ csr_3841_riscv,
+ csr_3842_riscv,
+ csr_3843_riscv,
+ csr_3844_riscv,
+ csr_3845_riscv,
+ csr_3846_riscv,
+ csr_3847_riscv,
+ csr_3848_riscv,
+ csr_3849_riscv,
+ csr_3850_riscv,
+ csr_3851_riscv,
+ csr_3852_riscv,
+ csr_3853_riscv,
+ csr_3854_riscv,
+ csr_3855_riscv,
+ csr_3856_riscv,
+ csr_3857_riscv,
+ csr_3858_riscv,
+ csr_3859_riscv,
+ csr_3860_riscv,
+ csr_3861_riscv,
+ csr_3862_riscv,
+ csr_3863_riscv,
+ csr_3864_riscv,
+ csr_3865_riscv,
+ csr_3866_riscv,
+ csr_3867_riscv,
+ csr_3868_riscv,
+ csr_3869_riscv,
+ csr_3870_riscv,
+ csr_3871_riscv,
+ csr_3872_riscv,
+ csr_3873_riscv,
+ csr_3874_riscv,
+ csr_3875_riscv,
+ csr_3876_riscv,
+ csr_3877_riscv,
+ csr_3878_riscv,
+ csr_3879_riscv,
+ csr_3880_riscv,
+ csr_3881_riscv,
+ csr_3882_riscv,
+ csr_3883_riscv,
+ csr_3884_riscv,
+ csr_3885_riscv,
+ csr_3886_riscv,
+ csr_3887_riscv,
+ csr_3888_riscv,
+ csr_3889_riscv,
+ csr_3890_riscv,
+ csr_3891_riscv,
+ csr_3892_riscv,
+ csr_3893_riscv,
+ csr_3894_riscv,
+ csr_3895_riscv,
+ csr_3896_riscv,
+ csr_3897_riscv,
+ csr_3898_riscv,
+ csr_3899_riscv,
+ csr_3900_riscv,
+ csr_3901_riscv,
+ csr_3902_riscv,
+ csr_3903_riscv,
+ csr_3904_riscv,
+ csr_3905_riscv,
+ csr_3906_riscv,
+ csr_3907_riscv,
+ csr_3908_riscv,
+ csr_3909_riscv,
+ csr_3910_riscv,
+ csr_3911_riscv,
+ csr_3912_riscv,
+ csr_3913_riscv,
+ csr_3914_riscv,
+ csr_3915_riscv,
+ csr_3916_riscv,
+ csr_3917_riscv,
+ csr_3918_riscv,
+ csr_3919_riscv,
+ csr_3920_riscv,
+ csr_3921_riscv,
+ csr_3922_riscv,
+ csr_3923_riscv,
+ csr_3924_riscv,
+ csr_3925_riscv,
+ csr_3926_riscv,
+ csr_3927_riscv,
+ csr_3928_riscv,
+ csr_3929_riscv,
+ csr_3930_riscv,
+ csr_3931_riscv,
+ csr_3932_riscv,
+ csr_3933_riscv,
+ csr_3934_riscv,
+ csr_3935_riscv,
+ csr_3936_riscv,
+ csr_3937_riscv,
+ csr_3938_riscv,
+ csr_3939_riscv,
+ csr_3940_riscv,
+ csr_3941_riscv,
+ csr_3942_riscv,
+ csr_3943_riscv,
+ csr_3944_riscv,
+ csr_3945_riscv,
+ csr_3946_riscv,
+ csr_3947_riscv,
+ csr_3948_riscv,
+ csr_3949_riscv,
+ csr_3950_riscv,
+ csr_3951_riscv,
+ csr_3952_riscv,
+ csr_3953_riscv,
+ csr_3954_riscv,
+ csr_3955_riscv,
+ csr_3956_riscv,
+ csr_3957_riscv,
+ csr_3958_riscv,
+ csr_3959_riscv,
+ csr_3960_riscv,
+ csr_3961_riscv,
+ csr_3962_riscv,
+ csr_3963_riscv,
+ csr_3964_riscv,
+ csr_3965_riscv,
+ csr_3966_riscv,
+ csr_3967_riscv,
+ csr_3968_riscv,
+ csr_3969_riscv,
+ csr_3970_riscv,
+ csr_3971_riscv,
+ csr_3972_riscv,
+ csr_3973_riscv,
+ csr_3974_riscv,
+ csr_3975_riscv,
+ csr_3976_riscv,
+ csr_3977_riscv,
+ csr_3978_riscv,
+ csr_3979_riscv,
+ csr_3980_riscv,
+ csr_3981_riscv,
+ csr_3982_riscv,
+ csr_3983_riscv,
+ csr_3984_riscv,
+ csr_3985_riscv,
+ csr_3986_riscv,
+ csr_3987_riscv,
+ csr_3988_riscv,
+ csr_3989_riscv,
+ csr_3990_riscv,
+ csr_3991_riscv,
+ csr_3992_riscv,
+ csr_3993_riscv,
+ csr_3994_riscv,
+ csr_3995_riscv,
+ csr_3996_riscv,
+ csr_3997_riscv,
+ csr_3998_riscv,
+ csr_3999_riscv,
+ csr_4000_riscv,
+ csr_4001_riscv,
+ csr_4002_riscv,
+ csr_4003_riscv,
+ csr_4004_riscv,
+ csr_4005_riscv,
+ csr_4006_riscv,
+ csr_4007_riscv,
+ csr_4008_riscv,
+ csr_4009_riscv,
+ csr_4010_riscv,
+ csr_4011_riscv,
+ csr_4012_riscv,
+ csr_4013_riscv,
+ csr_4014_riscv,
+ csr_4015_riscv,
+ csr_4016_riscv,
+ csr_4017_riscv,
+ csr_4018_riscv,
+ csr_4019_riscv,
+ csr_4020_riscv,
+ csr_4021_riscv,
+ csr_4022_riscv,
+ csr_4023_riscv,
+ csr_4024_riscv,
+ csr_4025_riscv,
+ csr_4026_riscv,
+ csr_4027_riscv,
+ csr_4028_riscv,
+ csr_4029_riscv,
+ csr_4030_riscv,
+ csr_4031_riscv,
+ csr_4032_riscv,
+ csr_4033_riscv,
+ csr_4034_riscv,
+ csr_4035_riscv,
+ csr_4036_riscv,
+ csr_4037_riscv,
+ csr_4038_riscv,
+ csr_4039_riscv,
+ csr_4040_riscv,
+ csr_4041_riscv,
+ csr_4042_riscv,
+ csr_4043_riscv,
+ csr_4044_riscv,
+ csr_4045_riscv,
+ csr_4046_riscv,
+ csr_4047_riscv,
+ csr_4048_riscv,
+ csr_4049_riscv,
+ csr_4050_riscv,
+ csr_4051_riscv,
+ csr_4052_riscv,
+ csr_4053_riscv,
+ csr_4054_riscv,
+ csr_4055_riscv,
+ csr_4056_riscv,
+ csr_4057_riscv,
+ csr_4058_riscv,
+ csr_4059_riscv,
+ csr_4060_riscv,
+ csr_4061_riscv,
+ csr_4062_riscv,
+ csr_4063_riscv,
+ csr_4064_riscv,
+ csr_4065_riscv,
+ csr_4066_riscv,
+ csr_4067_riscv,
+ csr_4068_riscv,
+ csr_4069_riscv,
+ csr_4070_riscv,
+ csr_4071_riscv,
+ csr_4072_riscv,
+ csr_4073_riscv,
+ csr_4074_riscv,
+ csr_4075_riscv,
+ csr_4076_riscv,
+ csr_4077_riscv,
+ csr_4078_riscv,
+ csr_4079_riscv,
+ csr_4080_riscv,
+ csr_4081_riscv,
+ csr_4082_riscv,
+ csr_4083_riscv,
+ csr_4084_riscv,
+ csr_4085_riscv,
+ csr_4086_riscv,
+ csr_4087_riscv,
+ csr_4088_riscv,
+ csr_4089_riscv,
+ csr_4090_riscv,
+ csr_4091_riscv,
+ csr_4092_riscv,
+ csr_4093_riscv,
+ csr_4094_riscv,
+ csr_4095_riscv,
+ csr_fflags_riscv = csr_1_riscv,
+ csr_frm_riscv = csr_2_riscv,
+ csr_fcsr_riscv = csr_3_riscv,
+ csr_vstart_riscv = csr_8_riscv,
+ csr_vxsat_riscv = csr_9_riscv,
+ csr_vxrm_riscv = csr_10_riscv,
+ csr_vcsr_riscv = csr_15_riscv,
+ csr_sstatus_riscv = csr_256_riscv,
+ csr_sie_riscv = csr_260_riscv,
+ csr_stvec_riscv = csr_261_riscv,
+ csr_scounteren_riscv = csr_262_riscv,
+ csr_senvcfg_riscv = csr_266_riscv,
+ csr_sstateen0_riscv = csr_268_riscv,
+ csr_sstateen1_riscv = csr_269_riscv,
+ csr_sstateen2_riscv = csr_270_riscv,
+ csr_sstateen3_riscv = csr_271_riscv,
+ csr_scountinhibit_riscv = csr_288_riscv,
+ csr_sscratch_riscv = csr_320_riscv,
+ csr_sepc_riscv = csr_321_riscv,
+ csr_scause_riscv = csr_322_riscv,
+ csr_stval_riscv = csr_323_riscv,
+ csr_sip_riscv = csr_324_riscv,
+ csr_satp_riscv = csr_384_riscv,
+ csr_vsstatus_riscv = csr_512_riscv,
+ csr_vsie_riscv = csr_516_riscv,
+ csr_vstvec_riscv = csr_517_riscv,
+ csr_vsscratch_riscv = csr_576_riscv,
+ csr_vsepc_riscv = csr_577_riscv,
+ csr_vscause_riscv = csr_578_riscv,
+ csr_vstval_riscv = csr_579_riscv,
+ csr_vsip_riscv = csr_580_riscv,
+ csr_vsatp_riscv = csr_640_riscv,
+ csr_mstatus_riscv = csr_768_riscv,
+ csr_misa_riscv = csr_769_riscv,
+ csr_medeleg_riscv = csr_770_riscv,
+ csr_mideleg_riscv = csr_771_riscv,
+ csr_mie_riscv = csr_772_riscv,
+ csr_mtvec_riscv = csr_773_riscv,
+ csr_mcounteren_riscv = csr_774_riscv,
+ csr_menvcfg_riscv = csr_778_riscv,
+ csr_mstateen0_riscv = csr_780_riscv,
+ csr_mstateen1_riscv = csr_781_riscv,
+ csr_mstateen2_riscv = csr_782_riscv,
+ csr_mstateen3_riscv = csr_783_riscv,
+ csr_mstatush_riscv = csr_784_riscv,
+ csr_medelegh_riscv = csr_786_riscv,
+ csr_menvcfgh_riscv = csr_794_riscv,
+ csr_mstateen0h_riscv = csr_796_riscv,
+ csr_mstateen1h_riscv = csr_797_riscv,
+ csr_mstateen2h_riscv = csr_798_riscv,
+ csr_mstateen3h_riscv = csr_799_riscv,
+ csr_mcountinhibit_riscv = csr_800_riscv,
+ csr_mhpmevent3_riscv = csr_803_riscv,
+ csr_mhpmevent4_riscv = csr_804_riscv,
+ csr_mhpmevent5_riscv = csr_805_riscv,
+ csr_mhpmevent6_riscv = csr_806_riscv,
+ csr_mhpmevent7_riscv = csr_807_riscv,
+ csr_mhpmevent8_riscv = csr_808_riscv,
+ csr_mhpmevent9_riscv = csr_809_riscv,
+ csr_mhpmevent10_riscv = csr_810_riscv,
+ csr_mhpmevent11_riscv = csr_811_riscv,
+ csr_mhpmevent12_riscv = csr_812_riscv,
+ csr_mhpmevent13_riscv = csr_813_riscv,
+ csr_mhpmevent14_riscv = csr_814_riscv,
+ csr_mhpmevent15_riscv = csr_815_riscv,
+ csr_mhpmevent16_riscv = csr_816_riscv,
+ csr_mhpmevent17_riscv = csr_817_riscv,
+ csr_mhpmevent18_riscv = csr_818_riscv,
+ csr_mhpmevent19_riscv = csr_819_riscv,
+ csr_mhpmevent20_riscv = csr_820_riscv,
+ csr_mhpmevent21_riscv = csr_821_riscv,
+ csr_mhpmevent22_riscv = csr_822_riscv,
+ csr_mhpmevent23_riscv = csr_823_riscv,
+ csr_mhpmevent24_riscv = csr_824_riscv,
+ csr_mhpmevent25_riscv = csr_825_riscv,
+ csr_mhpmevent26_riscv = csr_826_riscv,
+ csr_mhpmevent27_riscv = csr_827_riscv,
+ csr_mhpmevent28_riscv = csr_828_riscv,
+ csr_mhpmevent29_riscv = csr_829_riscv,
+ csr_mhpmevent30_riscv = csr_830_riscv,
+ csr_mhpmevent31_riscv = csr_831_riscv,
+ csr_mscratch_riscv = csr_832_riscv,
+ csr_mepc_riscv = csr_833_riscv,
+ csr_mcause_riscv = csr_834_riscv,
+ csr_mtval_riscv = csr_835_riscv,
+ csr_mip_riscv = csr_836_riscv,
+ csr_mtinst_riscv = csr_842_riscv,
+ csr_mtval2_riscv = csr_843_riscv,
+ csr_pmpcfg0_riscv = csr_928_riscv,
+ csr_pmpcfg1_riscv = csr_929_riscv,
+ csr_pmpcfg2_riscv = csr_930_riscv,
+ csr_pmpcfg3_riscv = csr_931_riscv,
+ csr_pmpcfg4_riscv = csr_932_riscv,
+ csr_pmpcfg5_riscv = csr_933_riscv,
+ csr_pmpcfg6_riscv = csr_934_riscv,
+ csr_pmpcfg7_riscv = csr_935_riscv,
+ csr_pmpcfg8_riscv = csr_936_riscv,
+ csr_pmpcfg9_riscv = csr_937_riscv,
+ csr_pmpcfg10_riscv = csr_938_riscv,
+ csr_pmpcfg11_riscv = csr_939_riscv,
+ csr_pmpcfg12_riscv = csr_940_riscv,
+ csr_pmpcfg13_riscv = csr_941_riscv,
+ csr_pmpcfg14_riscv = csr_942_riscv,
+ csr_pmpcfg15_riscv = csr_943_riscv,
+ csr_pmpaddr0_riscv = csr_944_riscv,
+ csr_pmpaddr1_riscv = csr_945_riscv,
+ csr_pmpaddr2_riscv = csr_946_riscv,
+ csr_pmpaddr3_riscv = csr_947_riscv,
+ csr_pmpaddr4_riscv = csr_948_riscv,
+ csr_pmpaddr5_riscv = csr_949_riscv,
+ csr_pmpaddr6_riscv = csr_950_riscv,
+ csr_pmpaddr7_riscv = csr_951_riscv,
+ csr_pmpaddr8_riscv = csr_952_riscv,
+ csr_pmpaddr9_riscv = csr_953_riscv,
+ csr_pmpaddr10_riscv = csr_954_riscv,
+ csr_pmpaddr11_riscv = csr_955_riscv,
+ csr_pmpaddr12_riscv = csr_956_riscv,
+ csr_pmpaddr13_riscv = csr_957_riscv,
+ csr_pmpaddr14_riscv = csr_958_riscv,
+ csr_pmpaddr15_riscv = csr_959_riscv,
+ csr_pmpaddr16_riscv = csr_960_riscv,
+ csr_pmpaddr17_riscv = csr_961_riscv,
+ csr_pmpaddr18_riscv = csr_962_riscv,
+ csr_pmpaddr19_riscv = csr_963_riscv,
+ csr_pmpaddr20_riscv = csr_964_riscv,
+ csr_pmpaddr21_riscv = csr_965_riscv,
+ csr_pmpaddr22_riscv = csr_966_riscv,
+ csr_pmpaddr23_riscv = csr_967_riscv,
+ csr_pmpaddr24_riscv = csr_968_riscv,
+ csr_pmpaddr25_riscv = csr_969_riscv,
+ csr_pmpaddr26_riscv = csr_970_riscv,
+ csr_pmpaddr27_riscv = csr_971_riscv,
+ csr_pmpaddr28_riscv = csr_972_riscv,
+ csr_pmpaddr29_riscv = csr_973_riscv,
+ csr_pmpaddr30_riscv = csr_974_riscv,
+ csr_pmpaddr31_riscv = csr_975_riscv,
+ csr_pmpaddr32_riscv = csr_976_riscv,
+ csr_pmpaddr33_riscv = csr_977_riscv,
+ csr_pmpaddr34_riscv = csr_978_riscv,
+ csr_pmpaddr35_riscv = csr_979_riscv,
+ csr_pmpaddr36_riscv = csr_980_riscv,
+ csr_pmpaddr37_riscv = csr_981_riscv,
+ csr_pmpaddr38_riscv = csr_982_riscv,
+ csr_pmpaddr39_riscv = csr_983_riscv,
+ csr_pmpaddr40_riscv = csr_984_riscv,
+ csr_pmpaddr41_riscv = csr_985_riscv,
+ csr_pmpaddr42_riscv = csr_986_riscv,
+ csr_pmpaddr43_riscv = csr_987_riscv,
+ csr_pmpaddr44_riscv = csr_988_riscv,
+ csr_pmpaddr45_riscv = csr_989_riscv,
+ csr_pmpaddr46_riscv = csr_990_riscv,
+ csr_pmpaddr47_riscv = csr_991_riscv,
+ csr_pmpaddr48_riscv = csr_992_riscv,
+ csr_pmpaddr49_riscv = csr_993_riscv,
+ csr_pmpaddr50_riscv = csr_994_riscv,
+ csr_pmpaddr51_riscv = csr_995_riscv,
+ csr_pmpaddr52_riscv = csr_996_riscv,
+ csr_pmpaddr53_riscv = csr_997_riscv,
+ csr_pmpaddr54_riscv = csr_998_riscv,
+ csr_pmpaddr55_riscv = csr_999_riscv,
+ csr_pmpaddr56_riscv = csr_1000_riscv,
+ csr_pmpaddr57_riscv = csr_1001_riscv,
+ csr_pmpaddr58_riscv = csr_1002_riscv,
+ csr_pmpaddr59_riscv = csr_1003_riscv,
+ csr_pmpaddr60_riscv = csr_1004_riscv,
+ csr_pmpaddr61_riscv = csr_1005_riscv,
+ csr_pmpaddr62_riscv = csr_1006_riscv,
+ csr_pmpaddr63_riscv = csr_1007_riscv,
+ csr_scontext_riscv = csr_1448_riscv,
+ csr_hstatus_riscv = csr_1536_riscv,
+ csr_hedeleg_riscv = csr_1538_riscv,
+ csr_hideleg_riscv = csr_1539_riscv,
+ csr_hie_riscv = csr_1540_riscv,
+ csr_htimedelta_riscv = csr_1541_riscv,
+ csr_hcounteren_riscv = csr_1542_riscv,
+ csr_hgeie_riscv = csr_1543_riscv,
+ csr_henvcfg_riscv = csr_1546_riscv,
+ csr_hstateen0_riscv = csr_1548_riscv,
+ csr_hstateen1_riscv = csr_1549_riscv,
+ csr_hstateen2_riscv = csr_1550_riscv,
+ csr_hstateen3_riscv = csr_1551_riscv,
+ csr_hedelegh_riscv = csr_1554_riscv,
+ csr_htimedeltah_riscv = csr_1557_riscv,
+ csr_henvcfgh_riscv = csr_1562_riscv,
+ csr_hstateen0h_riscv = csr_1564_riscv,
+ csr_hstateen1h_riscv = csr_1565_riscv,
+ csr_hstateen2h_riscv = csr_1566_riscv,
+ csr_hstateen3h_riscv = csr_1567_riscv,
+ csr_htval_riscv = csr_1603_riscv,
+ csr_hip_riscv = csr_1604_riscv,
+ csr_hvip_riscv = csr_1605_riscv,
+ csr_htinst_riscv = csr_1610_riscv,
+ csr_hgatp_riscv = csr_1664_riscv,
+ csr_hcontext_riscv = csr_1704_riscv,
+ csr_mhpmevent3h_riscv = csr_1827_riscv,
+ csr_mhpmevent4h_riscv = csr_1828_riscv,
+ csr_mhpmevent5h_riscv = csr_1829_riscv,
+ csr_mhpmevent6h_riscv = csr_1830_riscv,
+ csr_mhpmevent7h_riscv = csr_1831_riscv,
+ csr_mhpmevent8h_riscv = csr_1832_riscv,
+ csr_mhpmevent9h_riscv = csr_1833_riscv,
+ csr_mhpmevent10h_riscv = csr_1834_riscv,
+ csr_mhpmevent11h_riscv = csr_1835_riscv,
+ csr_mhpmevent12h_riscv = csr_1836_riscv,
+ csr_mhpmevent13h_riscv = csr_1837_riscv,
+ csr_mhpmevent14h_riscv = csr_1838_riscv,
+ csr_mhpmevent15h_riscv = csr_1839_riscv,
+ csr_mhpmevent16h_riscv = csr_1840_riscv,
+ csr_mhpmevent17h_riscv = csr_1841_riscv,
+ csr_mhpmevent18h_riscv = csr_1842_riscv,
+ csr_mhpmevent19h_riscv = csr_1843_riscv,
+ csr_mhpmevent20h_riscv = csr_1844_riscv,
+ csr_mhpmevent21h_riscv = csr_1845_riscv,
+ csr_mhpmevent22h_riscv = csr_1846_riscv,
+ csr_mhpmevent23h_riscv = csr_1847_riscv,
+ csr_mhpmevent24h_riscv = csr_1848_riscv,
+ csr_mhpmevent25h_riscv = csr_1849_riscv,
+ csr_mhpmevent26h_riscv = csr_1850_riscv,
+ csr_mhpmevent27h_riscv = csr_1851_riscv,
+ csr_mhpmevent28h_riscv = csr_1852_riscv,
+ csr_mhpmevent29h_riscv = csr_1853_riscv,
+ csr_mhpmevent30h_riscv = csr_1854_riscv,
+ csr_mhpmevent31h_riscv = csr_1855_riscv,
+ csr_mnscratch_riscv = csr_1856_riscv,
+ csr_mnepc_riscv = csr_1857_riscv,
+ csr_mncause_riscv = csr_1858_riscv,
+ csr_mnstatus_riscv = csr_1860_riscv,
+ csr_mseccfg_riscv = csr_1863_riscv,
+ csr_mseccfgh_riscv = csr_1879_riscv,
+ csr_tselect_riscv = csr_1952_riscv,
+ csr_tdata1_riscv = csr_1953_riscv,
+ csr_tdata2_riscv = csr_1954_riscv,
+ csr_tdata3_riscv = csr_1955_riscv,
+ csr_mcontext_riscv = csr_1960_riscv,
+ csr_dcsr_riscv = csr_1968_riscv,
+ csr_dpc_riscv = csr_1969_riscv,
+ csr_dscratch0_riscv = csr_1970_riscv,
+ csr_dscratch1_riscv = csr_1971_riscv,
+ csr_mcycle_riscv = csr_2816_riscv,
+ csr_minstret_riscv = csr_2818_riscv,
+ csr_mhpmcounter3_riscv = csr_2819_riscv,
+ csr_mhpmcounter4_riscv = csr_2820_riscv,
+ csr_mhpmcounter5_riscv = csr_2821_riscv,
+ csr_mhpmcounter6_riscv = csr_2822_riscv,
+ csr_mhpmcounter7_riscv = csr_2823_riscv,
+ csr_mhpmcounter8_riscv = csr_2824_riscv,
+ csr_mhpmcounter9_riscv = csr_2825_riscv,
+ csr_mhpmcounter10_riscv = csr_2826_riscv,
+ csr_mhpmcounter11_riscv = csr_2827_riscv,
+ csr_mhpmcounter12_riscv = csr_2828_riscv,
+ csr_mhpmcounter13_riscv = csr_2829_riscv,
+ csr_mhpmcounter14_riscv = csr_2830_riscv,
+ csr_mhpmcounter15_riscv = csr_2831_riscv,
+ csr_mhpmcounter16_riscv = csr_2832_riscv,
+ csr_mhpmcounter17_riscv = csr_2833_riscv,
+ csr_mhpmcounter18_riscv = csr_2834_riscv,
+ csr_mhpmcounter19_riscv = csr_2835_riscv,
+ csr_mhpmcounter20_riscv = csr_2836_riscv,
+ csr_mhpmcounter21_riscv = csr_2837_riscv,
+ csr_mhpmcounter22_riscv = csr_2838_riscv,
+ csr_mhpmcounter23_riscv = csr_2839_riscv,
+ csr_mhpmcounter24_riscv = csr_2840_riscv,
+ csr_mhpmcounter25_riscv = csr_2841_riscv,
+ csr_mhpmcounter26_riscv = csr_2842_riscv,
+ csr_mhpmcounter27_riscv = csr_2843_riscv,
+ csr_mhpmcounter28_riscv = csr_2844_riscv,
+ csr_mhpmcounter29_riscv = csr_2845_riscv,
+ csr_mhpmcounter30_riscv = csr_2846_riscv,
+ csr_mhpmcounter31_riscv = csr_2847_riscv,
+ csr_mcycleh_riscv = csr_2944_riscv,
+ csr_minstreth_riscv = csr_2946_riscv,
+ csr_mhpmcounter3h_riscv = csr_2947_riscv,
+ csr_mhpmcounter4h_riscv = csr_2948_riscv,
+ csr_mhpmcounter5h_riscv = csr_2949_riscv,
+ csr_mhpmcounter6h_riscv = csr_2950_riscv,
+ csr_mhpmcounter7h_riscv = csr_2951_riscv,
+ csr_mhpmcounter8h_riscv = csr_2952_riscv,
+ csr_mhpmcounter9h_riscv = csr_2953_riscv,
+ csr_mhpmcounter10h_riscv = csr_2954_riscv,
+ csr_mhpmcounter11h_riscv = csr_2955_riscv,
+ csr_mhpmcounter12h_riscv = csr_2956_riscv,
+ csr_mhpmcounter13h_riscv = csr_2957_riscv,
+ csr_mhpmcounter14h_riscv = csr_2958_riscv,
+ csr_mhpmcounter15h_riscv = csr_2959_riscv,
+ csr_mhpmcounter16h_riscv = csr_2960_riscv,
+ csr_mhpmcounter17h_riscv = csr_2961_riscv,
+ csr_mhpmcounter18h_riscv = csr_2962_riscv,
+ csr_mhpmcounter19h_riscv = csr_2963_riscv,
+ csr_mhpmcounter20h_riscv = csr_2964_riscv,
+ csr_mhpmcounter21h_riscv = csr_2965_riscv,
+ csr_mhpmcounter22h_riscv = csr_2966_riscv,
+ csr_mhpmcounter23h_riscv = csr_2967_riscv,
+ csr_mhpmcounter24h_riscv = csr_2968_riscv,
+ csr_mhpmcounter25h_riscv = csr_2969_riscv,
+ csr_mhpmcounter26h_riscv = csr_2970_riscv,
+ csr_mhpmcounter27h_riscv = csr_2971_riscv,
+ csr_mhpmcounter28h_riscv = csr_2972_riscv,
+ csr_mhpmcounter29h_riscv = csr_2973_riscv,
+ csr_mhpmcounter30h_riscv = csr_2974_riscv,
+ csr_mhpmcounter31h_riscv = csr_2975_riscv,
+ csr_cycle_riscv = csr_3072_riscv,
+ csr_time_riscv = csr_3073_riscv,
+ csr_instret_riscv = csr_3074_riscv,
+ csr_hpmcounter3_riscv = csr_3075_riscv,
+ csr_hpmcounter4_riscv = csr_3076_riscv,
+ csr_hpmcounter5_riscv = csr_3077_riscv,
+ csr_hpmcounter6_riscv = csr_3078_riscv,
+ csr_hpmcounter7_riscv = csr_3079_riscv,
+ csr_hpmcounter8_riscv = csr_3080_riscv,
+ csr_hpmcounter9_riscv = csr_3081_riscv,
+ csr_hpmcounter10_riscv = csr_3082_riscv,
+ csr_hpmcounter11_riscv = csr_3083_riscv,
+ csr_hpmcounter12_riscv = csr_3084_riscv,
+ csr_hpmcounter13_riscv = csr_3085_riscv,
+ csr_hpmcounter14_riscv = csr_3086_riscv,
+ csr_hpmcounter15_riscv = csr_3087_riscv,
+ csr_hpmcounter16_riscv = csr_3088_riscv,
+ csr_hpmcounter17_riscv = csr_3089_riscv,
+ csr_hpmcounter18_riscv = csr_3090_riscv,
+ csr_hpmcounter19_riscv = csr_3091_riscv,
+ csr_hpmcounter20_riscv = csr_3092_riscv,
+ csr_hpmcounter21_riscv = csr_3093_riscv,
+ csr_hpmcounter22_riscv = csr_3094_riscv,
+ csr_hpmcounter23_riscv = csr_3095_riscv,
+ csr_hpmcounter24_riscv = csr_3096_riscv,
+ csr_hpmcounter25_riscv = csr_3097_riscv,
+ csr_hpmcounter26_riscv = csr_3098_riscv,
+ csr_hpmcounter27_riscv = csr_3099_riscv,
+ csr_hpmcounter28_riscv = csr_3100_riscv,
+ csr_hpmcounter29_riscv = csr_3101_riscv,
+ csr_hpmcounter30_riscv = csr_3102_riscv,
+ csr_hpmcounter31_riscv = csr_3103_riscv,
+ csr_vl_riscv = csr_3104_riscv,
+ csr_vtype_riscv = csr_3105_riscv,
+ csr_vlenb_riscv = csr_3106_riscv,
+ csr_cycleh_riscv = csr_3200_riscv,
+ csr_timeh_riscv = csr_3201_riscv,
+ csr_instreth_riscv = csr_3202_riscv,
+ csr_hpmcounter3h_riscv = csr_3203_riscv,
+ csr_hpmcounter4h_riscv = csr_3204_riscv,
+ csr_hpmcounter5h_riscv = csr_3205_riscv,
+ csr_hpmcounter6h_riscv = csr_3206_riscv,
+ csr_hpmcounter7h_riscv = csr_3207_riscv,
+ csr_hpmcounter8h_riscv = csr_3208_riscv,
+ csr_hpmcounter9h_riscv = csr_3209_riscv,
+ csr_hpmcounter10h_riscv = csr_3210_riscv,
+ csr_hpmcounter11h_riscv = csr_3211_riscv,
+ csr_hpmcounter12h_riscv = csr_3212_riscv,
+ csr_hpmcounter13h_riscv = csr_3213_riscv,
+ csr_hpmcounter14h_riscv = csr_3214_riscv,
+ csr_hpmcounter15h_riscv = csr_3215_riscv,
+ csr_hpmcounter16h_riscv = csr_3216_riscv,
+ csr_hpmcounter17h_riscv = csr_3217_riscv,
+ csr_hpmcounter18h_riscv = csr_3218_riscv,
+ csr_hpmcounter19h_riscv = csr_3219_riscv,
+ csr_hpmcounter20h_riscv = csr_3220_riscv,
+ csr_hpmcounter21h_riscv = csr_3221_riscv,
+ csr_hpmcounter22h_riscv = csr_3222_riscv,
+ csr_hpmcounter23h_riscv = csr_3223_riscv,
+ csr_hpmcounter24h_riscv = csr_3224_riscv,
+ csr_hpmcounter25h_riscv = csr_3225_riscv,
+ csr_hpmcounter26h_riscv = csr_3226_riscv,
+ csr_hpmcounter27h_riscv = csr_3227_riscv,
+ csr_hpmcounter28h_riscv = csr_3228_riscv,
+ csr_hpmcounter29h_riscv = csr_3229_riscv,
+ csr_hpmcounter30h_riscv = csr_3230_riscv,
+ csr_hpmcounter31h_riscv = csr_3231_riscv,
+ csr_scountovf_riscv = csr_3488_riscv,
+ csr_hgeip_riscv = csr_3602_riscv,
+ csr_mvendorid_riscv = csr_3857_riscv,
+ csr_marchid_riscv = csr_3858_riscv,
+ csr_mimpid_riscv = csr_3859_riscv,
+ csr_mhartid_riscv = csr_3860_riscv,
+ csr_mconfigptr_riscv = csr_3861_riscv,
+ csr_last_riscv = csr_4095_riscv,
+
k_num_registers_riscv
};
diff --git a/lldb/source/Plugins/Process/elf-core/ProcessElfCore.cpp b/lldb/source/Plugins/Process/elf-core/ProcessElfCore.cpp
index 88eeddf178788..254433e367848 100644
--- a/lldb/source/Plugins/Process/elf-core/ProcessElfCore.cpp
+++ b/lldb/source/Plugins/Process/elf-core/ProcessElfCore.cpp
@@ -999,9 +999,13 @@ llvm::Error ProcessElfCore::ParseThreadContextsFromNoteSegment(
case llvm::Triple::OpenBSD:
return parseOpenBSDNotes(*notes_or_error);
default:
- return llvm::make_error<llvm::StringError>(
- "Don't know how to parse core file. Unsupported OS.",
- llvm::inconvertibleErrorCode());
+ // Treat bare-metal 32-bit RISC-V like Linux.
+ if (GetArchitecture().GetTriple().getArch() == llvm::Triple::riscv32)
+ return parseLinuxNotes(*notes_or_error);
+ else
+ return llvm::make_error<llvm::StringError>(
+ "Don't know how to parse core file. Unsupported OS.",
+ llvm::inconvertibleErrorCode());
}
}
diff --git a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv32.cpp b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv32.cpp
index 79f546eda66f2..e77dfe365aecc 100644
--- a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv32.cpp
+++ b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv32.cpp
@@ -7,75 +7,372 @@
//===----------------------------------------------------------------------===//
#include "RegisterContextPOSIXCore_riscv32.h"
+
#include "lldb/Utility/DataBufferHeap.h"
+#define GPR_OFFSET(idx) ((idx) * sizeof(uint32_t))
+#define FPR_OFFSET(idx) ((idx) * sizeof(uint32_t))
+#define CSR_OFFSET(idx) ((idx) * sizeof(uint32_t))
+
+#define DECLARE_REGISTER_INFOS_RISCV32_STRUCT
+#include "Plugins/Process/Utility/RegisterInfos_riscv32.h"
+#undef DECLARE_REGISTER_INFOS_RISCV32_STRUCT
+
using namespace lldb_private;
std::unique_ptr<RegisterContextCorePOSIX_riscv32>
RegisterContextCorePOSIX_riscv32::Create(Thread &thread, const ArchSpec &arch,
const DataExtractor &gpregset,
llvm::ArrayRef<CoreNote> notes) {
- Flags opt_regsets = RegisterInfoPOSIX_riscv32::eRegsetMaskDefault;
-
return std::unique_ptr<RegisterContextCorePOSIX_riscv32>(
new RegisterContextCorePOSIX_riscv32(
- thread,
- std::make_unique<RegisterInfoPOSIX_riscv32>(arch, opt_regsets),
+ thread, std::make_unique<RegisterInfoPOSIXDynamic_riscv32>(arch),
gpregset, notes));
}
RegisterContextCorePOSIX_riscv32::RegisterContextCorePOSIX_riscv32(
- Thread &thread, std::unique_ptr<RegisterInfoPOSIX_riscv32> register_info,
+ Thread &thread,
+ std::unique_ptr<RegisterInfoPOSIXDynamic_riscv32> register_info,
const DataExtractor &gpregset, llvm::ArrayRef<CoreNote> notes)
- : RegisterContextPOSIX_riscv32(thread, std::move(register_info)) {
+ : RegisterContext(thread, 0), m_reg_infos_up(std::move(register_info)) {
+ // Compute the maximum register counts for GPR, FPR, and CSR.
+ uint32_t k_num_gpr_registers = (sizeof(g_register_infos_riscv32_gpr) /
+ sizeof(g_register_infos_riscv32_gpr[0]));
+ uint32_t k_num_fpr_registers = (sizeof(g_register_infos_riscv32_fpr) /
+ sizeof(g_register_infos_riscv32_fpr[0]));
+ uint32_t k_num_csr_registers = (sizeof(g_register_infos_riscv32_csr) /
+ sizeof(g_register_infos_riscv32_csr[0]));
- m_gpr.SetData(std::make_shared<DataBufferHeap>(gpregset.GetDataStart(),
- gpregset.GetByteSize()));
- m_gpr.SetByteOrder(gpregset.GetByteOrder());
+ std::vector<DynamicRegisterInfo::Register> registers;
+ uint32_t byte_offset = 0;
- if (m_register_info_up->IsFPPresent()) {
- ArchSpec arch = m_register_info_up->GetTargetArchitecture();
- m_fpr = getRegset(notes, arch.GetTriple(), FPR_Desc);
+ // Build dynamic register information for GPR.
+ m_gpregset.SetData(std::make_shared<DataBufferHeap>(gpregset.GetDataStart(),
+ gpregset.GetByteSize()));
+ if (m_gpregset.GetByteSize() >= g_register_infos_riscv32_gpr[0].byte_size) {
+ // GPR is available.
+ assert((m_gpregset.GetByteSize() /
+ g_register_infos_riscv32_gpr[0].byte_size) == k_num_gpr_registers &&
+ "GPR has the wrong number of registers!");
+ m_gpregset.SetByteOrder(gpregset.GetByteOrder());
+ for (auto gpr : g_register_infos_riscv32_gpr) {
+ std::vector<uint32_t> value_regs;
+ std::vector<uint32_t> invalidate_regs;
+ if (gpr.value_regs)
+ for (int idx = 0; gpr.value_regs[idx] != LLDB_INVALID_REGNUM; ++idx)
+ value_regs.push_back(gpr.value_regs[idx]);
+ if (gpr.invalidate_regs)
+ for (int idx = 0; gpr.invalidate_regs[idx] != LLDB_INVALID_REGNUM;
+ ++idx)
+ invalidate_regs.push_back(gpr.invalidate_regs[idx]);
+ DynamicRegisterInfo::Register reg{
+ lldb_private::ConstString(gpr.name),
+ lldb_private::ConstString(gpr.alt_name),
+ lldb_private::ConstString("GPR"),
+ gpr.byte_size,
+ byte_offset,
+ gpr.encoding,
+ gpr.format,
+ gpr.kinds[lldb::eRegisterKindDWARF],
+ gpr.kinds[lldb::eRegisterKindEHFrame],
+ gpr.kinds[lldb::eRegisterKindGeneric],
+ gpr.kinds[lldb::eRegisterKindProcessPlugin],
+ value_regs,
+ invalidate_regs,
+ /* value_reg_offset */ 0,
+ gpr.flags_type};
+
+ registers.push_back(reg);
+ byte_offset += gpr.byte_size;
+ }
}
+
+ // Build dynamic register information for FPR.
+ m_fpregset = getRegset(
+ notes, m_reg_infos_up->GetTargetArchitecture().GetTriple(), FPR_Desc);
+ if (m_fpregset.GetByteSize() >= g_register_infos_riscv32_fpr[0].byte_size) {
+ // GPR is available.
+ assert((m_fpregset.GetByteSize() /
+ g_register_infos_riscv32_fpr[0].byte_size) == k_num_fpr_registers &&
+ "FPR has the wrong number of registers!");
+ m_fpregset.SetByteOrder(lldb::eByteOrderLittle);
+ for (auto fpr : g_register_infos_riscv32_fpr) {
+ std::vector<uint32_t> value_regs;
+ std::vector<uint32_t> invalidate_regs;
+ if (fpr.value_regs)
+ for (int idx = 0; fpr.value_regs[idx] != LLDB_INVALID_REGNUM; ++idx)
+ value_regs.push_back(fpr.value_regs[idx]);
+ if (fpr.invalidate_regs)
+ for (int idx = 0; fpr.invalidate_regs[idx] != LLDB_INVALID_REGNUM;
+ ++idx)
+ invalidate_regs.push_back(fpr.invalidate_regs[idx]);
+ DynamicRegisterInfo::Register reg{
+ lldb_private::ConstString(fpr.name),
+ lldb_private::ConstString(fpr.alt_name),
+ lldb_private::ConstString("FPR"),
+ fpr.byte_size,
+ byte_offset,
+ fpr.encoding,
+ fpr.format,
+ fpr.kinds[lldb::eRegisterKindDWARF],
+ fpr.kinds[lldb::eRegisterKindEHFrame],
+ fpr.kinds[lldb::eRegisterKindGeneric],
+ fpr.kinds[lldb::eRegisterKindProcessPlugin],
+ value_regs,
+ invalidate_regs,
+ /* value_reg_offset */ 0,
+ fpr.flags_type};
+
+ registers.push_back(reg);
+ byte_offset += fpr.byte_size;
+ }
+ }
+
+ // Build dynamic register information for CSR.
+ m_csregset =
+ getRegset(notes, m_reg_infos_up->GetTargetArchitecture().GetTriple(),
+ RISCV32_CSREGMAP_Desc);
+ if (m_csregset.GetByteSize() >=
+ (sizeof(csr_kv_t::addr) + sizeof(csr_kv_t::val))) {
+ // CSR is available.
+ m_csregset.SetByteOrder(lldb::eByteOrderLittle);
+ lldb::offset_t offset = 0;
+ while (m_csregset.BytesLeft(offset)) {
+ RegisterInfo csr;
+ uint32_t csr_addr = m_csregset.GetU32(&offset);
+ if (m_csregset_regnums.size() == k_num_csr_registers) {
+ printf("Parsed the permissible number of CSRs (%d) but NT_CSREGMAP has "
+ "more! Skipping the remaining CSRs!\n",
+ k_num_csr_registers);
+ break;
+ }
+ if (llvm::is_contained(m_csregset_regnums, csr_addr)) {
+ printf("Encountered a duplicate CSR while parsing NT_CSREGMAP: %s! "
+ "Skipping!\n",
+ g_register_infos_riscv32_csr[csr_addr].name);
+ } else {
+ m_csregset_regnums.push_back(csr_addr);
+ csr = g_register_infos_riscv32_csr[csr_addr];
+ std::vector<uint32_t> value_regs;
+ std::vector<uint32_t> invalidate_regs;
+ if (csr.value_regs)
+ for (int idx = 0; csr.value_regs[idx] != LLDB_INVALID_REGNUM; ++idx)
+ value_regs.push_back(csr.value_regs[idx]);
+ if (csr.invalidate_regs)
+ for (int idx = 0; csr.invalidate_regs[idx] != LLDB_INVALID_REGNUM;
+ ++idx)
+ invalidate_regs.push_back(csr.invalidate_regs[idx]);
+ DynamicRegisterInfo::Register reg{
+ lldb_private::ConstString(csr.name),
+ lldb_private::ConstString(csr.alt_name),
+ lldb_private::ConstString("CSR"),
+ csr.byte_size,
+ byte_offset,
+ csr.encoding,
+ csr.format,
+ csr.kinds[lldb::eRegisterKindDWARF],
+ csr.kinds[lldb::eRegisterKindEHFrame],
+ csr.kinds[lldb::eRegisterKindGeneric],
+ csr.kinds[lldb::eRegisterKindProcessPlugin],
+ value_regs,
+ invalidate_regs,
+ /* value_reg_offset */ 0,
+ csr.flags_type};
+ registers.push_back(reg);
+ }
+ byte_offset += csr.byte_size;
+ (void)m_csregset.GetU32(&offset);
+ }
+ }
+
+ m_reg_infos_up->SetRegisterInfo(std::move(registers));
}
RegisterContextCorePOSIX_riscv32::~RegisterContextCorePOSIX_riscv32() = default;
-bool RegisterContextCorePOSIX_riscv32::ReadGPR() { return true; }
+void RegisterContextCorePOSIX_riscv32::InvalidateAllRegisters() {}
-bool RegisterContextCorePOSIX_riscv32::ReadFPR() { return true; }
+size_t RegisterContextCorePOSIX_riscv32::GetRegisterCount() {
+ return m_reg_infos_up->GetRegisterCount();
+}
-bool RegisterContextCorePOSIX_riscv32::WriteGPR() {
- assert(false && "Writing registers is not allowed for core dumps");
- return false;
+const lldb_private::RegisterInfo *
+RegisterContextCorePOSIX_riscv32::GetRegisterInfoAtIndex(size_t reg) {
+ if (reg < GetRegisterCount())
+ return &m_reg_infos_up->GetRegisterInfo()[static_cast<uint32_t>(reg)];
+ return nullptr;
}
-bool RegisterContextCorePOSIX_riscv32::WriteFPR() {
- assert(false && "Writing registers is not allowed for core dumps");
- return false;
+size_t RegisterContextCorePOSIX_riscv32::GetRegisterSetCount() {
+ return m_reg_infos_up->GetRegisterSetCount();
+}
+
+const lldb_private::RegisterSet *
+RegisterContextCorePOSIX_riscv32::GetRegisterSet(size_t set) {
+ return m_reg_infos_up->GetRegisterSet(static_cast<uint32_t>(set));
}
bool RegisterContextCorePOSIX_riscv32::ReadRegister(
const RegisterInfo *reg_info, RegisterValue &value) {
+ const lldb_private::RegisterInfo *dyn_reg_info;
const uint8_t *src = nullptr;
- lldb::offset_t offset = reg_info->byte_offset;
+ if ((dyn_reg_info = m_reg_infos_up->GetRegisterInfo(reg_info->name))) {
+ lldb::offset_t offset = dyn_reg_info->byte_offset;
+ if (IsGPR(dyn_reg_info->kinds[lldb::eRegisterKindLLDB])) {
+ // clang-format off
+ //
+ // |____| |_______________|
+ // | | src -> | |
+ // | pc | <- dyn_reg_info->byte_offset = 0 | m_gpregset[0] | uint32_t
+ // |____| offset = 0 -> |_______________|
+ // | | | |
+ // | x1 | | m_gpregset[4] | uint32_t
+ // |____| |_______________|
+ // .. ..
+ // |____| |_______________|
+ // | | | |
+ // | xn | <- dyn_reg_info->byte_offset offset -> | m_gpregset[n] | uint32_t
+ // |____| |_______________|
+ // | | | |
+ // .. ..
+ //
+ // clang-format on
+ src = m_gpregset.GetDataStart();
+ } else if (IsFPR(dyn_reg_info->kinds[lldb::eRegisterKindLLDB])) {
+ // clang-format off
+ //
+ // |____|
+ // | |
+ // | pc | <- dyn_reg_info->byte_offset = 0
+ // |____|
+ // | |
+ // | x1 |
+ // |____|
+ // ..
+ // |____|
+ // | |
+ // | x0 |
+ // |____| |_______________|
+ // | | src -> | |
+ // | f0 | | m_fpregset[0] | uint32_t
+ // |____| offset = 0 -> |_______________|
+ // | | | |
+ // | f1 | | m_fpregset[4] | uint32_t
+ // |____| |_______________|
+ // .. ..
+ // |____| |_______________|
+ // | | | |
+ // | fn | <- dyn_reg_info->byte_offset offset -> | m_fpregset[n] | uint32_t
+ // |____| |_______________|
+ // | | | |
+ // .. ..
+ //
+ // clang-format on
+ src = m_fpregset.GetDataStart();
+ offset -= (g_register_infos_riscv32_gpr[0].byte_size *
+ m_reg_infos_up->GetGPRSize());
+ } else if (IsCSR(dyn_reg_info->kinds[lldb::eRegisterKindLLDB])) {
+ // clang-format off
+ //
+ // |______|
+ // | |
+ // | pc | <- dyn_reg_info->byte_offset = 0
+ // |______|
+ // | |
+ // | x1 |
+ // |______|
+ // ..
+ // |______|
+ // | |
+ // | x0 |
+ // |______|
+ // | |
+ // | f0 |
+ // |______|
+ // | |
+ // | f1 |
+ // |______|
+ // ..
+ // |______|
+ // | |
+ // | f31 |
+ // |______| |________________|
+ // | | src -> | |
+ // | | csr0::addr -> | m_csregset[00] | uint32_t
+ // | | offset = 0 -> | |
+ // | csr0 | |----------------|
+ // | | | |
+ // | | csr0::val -> | m_csregset[04] | uint32_t
+ // |______| |________________|
+ // | | | |
+ // | | csr1::addr -> | m_csregset[08] | uint32_t
+ // | | | |
+ // | csr1 | |----------------|
+ // | | | |
+ // | | csr1::val -> | m_csregset[12] | uint32_t
+ // |______| |________________|
+ // .. ..
+ // |______| |________________|
+ // | | | |
+ // | | csrn::addr -> | m_csregset[..] | uint32_t
+ // | | | |
+ // | csrn | |----------------|
+ // | | csrn::val -> | |
+ // | | | m_csregset[..] | uint32_t
+ // |______| offset -> |________________|
+ // | | | |
+ // .. ..
+ //
+ // clang-format on
+ src = m_csregset.GetDataStart();
+ offset -= ((g_register_infos_riscv32_gpr[0].byte_size *
+ m_reg_infos_up->GetGPRSize()) +
+ (g_register_infos_riscv32_fpr[0].byte_size *
+ m_reg_infos_up->GetFPRSize()));
+ offset *= 2;
+ offset += dyn_reg_info->byte_size;
+ } else {
+ return false;
+ }
- if (IsGPR(reg_info->kinds[lldb::eRegisterKindLLDB])) {
- src = m_gpr.GetDataStart();
- } else if (IsFPR(reg_info->kinds[lldb::eRegisterKindLLDB])) {
- src = m_fpr.GetDataStart();
- offset -= GetGPRSize();
+ Status error;
+ value.SetFromMemoryData(*dyn_reg_info, src + offset,
+ dyn_reg_info->byte_size, lldb::eByteOrderLittle,
+ error);
+ return error.Success();
} else {
return false;
}
-
- Status error;
- value.SetFromMemoryData(*reg_info, src + offset, reg_info->byte_size,
- lldb::eByteOrderLittle, error);
- return error.Success();
}
bool RegisterContextCorePOSIX_riscv32::WriteRegister(
const RegisterInfo *reg_info, const RegisterValue &value) {
return false;
}
+
+bool RegisterContextCorePOSIX_riscv32::IsGPR(unsigned reg) {
+ if (llvm::StringRef(
+ GetRegisterSet(m_reg_infos_up->GetRegisterSetFromRegisterIndex(reg))
+ ->name)
+ .equals_insensitive(llvm::StringRef("GPR")))
+ return true;
+ return false;
+}
+
+bool RegisterContextCorePOSIX_riscv32::IsFPR(unsigned reg) {
+ if (llvm::StringRef(
+ GetRegisterSet(m_reg_infos_up->GetRegisterSetFromRegisterIndex(reg))
+ ->name)
+ .equals_insensitive(llvm::StringRef("FPR")))
+ return true;
+ return false;
+}
+
+bool RegisterContextCorePOSIX_riscv32::IsCSR(unsigned reg) {
+ if (llvm::StringRef(
+ GetRegisterSet(m_reg_infos_up->GetRegisterSetFromRegisterIndex(reg))
+ ->name)
+ .equals_insensitive(llvm::StringRef("CSR")))
+ return true;
+ return false;
+}
diff --git a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv32.h b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv32.h
index d2033bf011290..a84acdc122607 100644
--- a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv32.h
+++ b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv32.h
@@ -9,8 +9,9 @@
#ifndef LLDB_SOURCE_PLUGINS_PROCESS_ELF_CORE_REGISTERCONTEXTPOSIXCORE_RISCV32_H
#define LLDB_SOURCE_PLUGINS_PROCESS_ELF_CORE_REGISTERCONTEXTPOSIXCORE_RISCV32_H
-#include "Plugins/Process/Utility/RegisterContextPOSIX_riscv32.h"
-#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv32.h"
+// #include "Plugins/Process/Utility/RegisterContextPOSIX_riscv32.h"
+#include "Plugins/Process/Utility/RegisterInfoPOSIXDynamic_riscv32.h"
+
#include "Plugins/Process/elf-core/RegisterUtilities.h"
#include "lldb/Target/Thread.h"
#include "lldb/Utility/DataExtractor.h"
@@ -18,8 +19,13 @@
#include <memory>
-class RegisterContextCorePOSIX_riscv32 : public RegisterContextPOSIX_riscv32 {
+class RegisterContextCorePOSIX_riscv32 : public lldb_private::RegisterContext {
public:
+ struct csr_kv_t {
+ uint32_t addr; // CSR address/index
+ uint32_t val; // CSR value
+ };
+
static std::unique_ptr<RegisterContextCorePOSIX_riscv32>
Create(lldb_private::Thread &thread, const lldb_private::ArchSpec &arch,
const lldb_private::DataExtractor &gpregset,
@@ -27,6 +33,16 @@ class RegisterContextCorePOSIX_riscv32 : public RegisterContextPOSIX_riscv32 {
~RegisterContextCorePOSIX_riscv32() override;
+ void InvalidateAllRegisters() override;
+
+ size_t GetRegisterCount() override;
+
+ const lldb_private::RegisterInfo *GetRegisterInfoAtIndex(size_t reg) override;
+
+ size_t GetRegisterSetCount() override;
+
+ const lldb_private::RegisterSet *GetRegisterSet(size_t set) override;
+
bool ReadRegister(const lldb_private::RegisterInfo *reg_info,
lldb_private::RegisterValue &value) override;
@@ -36,21 +52,22 @@ class RegisterContextCorePOSIX_riscv32 : public RegisterContextPOSIX_riscv32 {
protected:
RegisterContextCorePOSIX_riscv32(
lldb_private::Thread &thread,
- std::unique_ptr<RegisterInfoPOSIX_riscv32> register_info,
+ std::unique_ptr<RegisterInfoPOSIXDynamic_riscv32> register_info,
const lldb_private::DataExtractor &gpregset,
llvm::ArrayRef<lldb_private::CoreNote> notes);
- bool ReadGPR() override;
-
- bool ReadFPR() override;
+ bool IsGPR(unsigned reg);
- bool WriteGPR() override;
+ bool IsFPR(unsigned reg);
- bool WriteFPR() override;
+ bool IsCSR(unsigned reg);
private:
- lldb_private::DataExtractor m_gpr;
- lldb_private::DataExtractor m_fpr;
+ std::unique_ptr<RegisterInfoPOSIXDynamic_riscv32> m_reg_infos_up;
+ lldb_private::DataExtractor m_gpregset;
+ lldb_private::DataExtractor m_fpregset;
+ lldb_private::DataExtractor m_csregset;
+ std::vector<uint32_t> m_csregset_regnums;
};
#endif // LLDB_SOURCE_PLUGINS_PROCESS_ELF_CORE_REGISTERCONTEXTPOSIXCORE_RISCV32_H
diff --git a/lldb/source/Plugins/Process/elf-core/RegisterUtilities.h b/lldb/source/Plugins/Process/elf-core/RegisterUtilities.h
index 59382a12cde0a..37030c483c7f5 100644
--- a/lldb/source/Plugins/Process/elf-core/RegisterUtilities.h
+++ b/lldb/source/Plugins/Process/elf-core/RegisterUtilities.h
@@ -70,6 +70,12 @@ enum {
};
}
+namespace RISCV32 {
+enum {
+ NT_CSREGMAP = 20,
+};
+}
+
struct CoreNote {
ELFNote info;
DataExtractor data;
@@ -113,6 +119,8 @@ constexpr RegsetDesc FPR_Desc[] = {
{llvm::Triple::NetBSD, llvm::Triple::x86, NETBSD::I386::NT_FPREGS},
{llvm::Triple::NetBSD, llvm::Triple::x86_64, NETBSD::AMD64::NT_FPREGS},
{llvm::Triple::OpenBSD, llvm::Triple::UnknownArch, OPENBSD::NT_FPREGS},
+ // Bare-metal 32-bit RISC-V debug target.
+ {llvm::Triple::UnknownOS, llvm::Triple::riscv32, llvm::ELF::NT_FPREGSET},
};
constexpr RegsetDesc AARCH64_SVE_Desc[] = {
@@ -161,6 +169,10 @@ constexpr RegsetDesc PPC_VSX_Desc[] = {
{llvm::Triple::Linux, llvm::Triple::UnknownArch, llvm::ELF::NT_PPC_VSX},
};
+constexpr RegsetDesc RISCV32_CSREGMAP_Desc[] = {
+ {llvm::Triple::UnknownOS, llvm::Triple::riscv32, RISCV32::NT_CSREGMAP},
+};
+
} // namespace lldb_private
#endif // LLDB_SOURCE_PLUGINS_PROCESS_ELF_CORE_REGISTERUTILITIES_H
diff --git a/lldb/source/Utility/RISCV_DWARF_Registers.h b/lldb/source/Utility/RISCV_DWARF_Registers.h
index 8aed3d13f9359..0e91c431e7296 100644
--- a/lldb/source/Utility/RISCV_DWARF_Registers.h
+++ b/lldb/source/Utility/RISCV_DWARF_Registers.h
@@ -115,19 +115,4120 @@ enum {
dwarf_vpr_v29,
dwarf_vpr_v30,
dwarf_vpr_v31 = 127,
- dwarf_first_csr = 4096,
- dwarf_fpr_fcsr = dwarf_first_csr + 0x003,
- // The vector extension adds seven unprivileged CSRs
- // (vstart, vxsat, vxrm, vcsr, vtype, vl, vlenb)
- // to a base scalar RISC-V ISA.
- dwarf_vpr_vstart = dwarf_first_csr + 0x008,
- dwarf_vpr_vxsat = dwarf_first_csr + 0x009,
- dwarf_vpr_vxrm = dwarf_first_csr + 0x00A,
- dwarf_vpr_vcsr = dwarf_first_csr + 0x00F,
- dwarf_vpr_vl = dwarf_first_csr + 0xC20,
- dwarf_vpr_vtype = dwarf_first_csr + 0xC21,
- dwarf_vpr_vlenb = dwarf_first_csr + 0xC22,
- dwarf_last_csr = 8191,
+
+ dwarf_csr_0 = 4096,
+ dwarf_csr_1,
+ dwarf_csr_2,
+ dwarf_csr_3,
+ dwarf_csr_4,
+ dwarf_csr_5,
+ dwarf_csr_6,
+ dwarf_csr_7,
+ dwarf_csr_8,
+ dwarf_csr_9,
+ dwarf_csr_10,
+ dwarf_csr_11,
+ dwarf_csr_12,
+ dwarf_csr_13,
+ dwarf_csr_14,
+ dwarf_csr_15,
+ dwarf_csr_16,
+ dwarf_csr_17,
+ dwarf_csr_18,
+ dwarf_csr_19,
+ dwarf_csr_20,
+ dwarf_csr_21,
+ dwarf_csr_22,
+ dwarf_csr_23,
+ dwarf_csr_24,
+ dwarf_csr_25,
+ dwarf_csr_26,
+ dwarf_csr_27,
+ dwarf_csr_28,
+ dwarf_csr_29,
+ dwarf_csr_30,
+ dwarf_csr_31,
+ dwarf_csr_32,
+ dwarf_csr_33,
+ dwarf_csr_34,
+ dwarf_csr_35,
+ dwarf_csr_36,
+ dwarf_csr_37,
+ dwarf_csr_38,
+ dwarf_csr_39,
+ dwarf_csr_40,
+ dwarf_csr_41,
+ dwarf_csr_42,
+ dwarf_csr_43,
+ dwarf_csr_44,
+ dwarf_csr_45,
+ dwarf_csr_46,
+ dwarf_csr_47,
+ dwarf_csr_48,
+ dwarf_csr_49,
+ dwarf_csr_50,
+ dwarf_csr_51,
+ dwarf_csr_52,
+ dwarf_csr_53,
+ dwarf_csr_54,
+ dwarf_csr_55,
+ dwarf_csr_56,
+ dwarf_csr_57,
+ dwarf_csr_58,
+ dwarf_csr_59,
+ dwarf_csr_60,
+ dwarf_csr_61,
+ dwarf_csr_62,
+ dwarf_csr_63,
+ dwarf_csr_64,
+ dwarf_csr_65,
+ dwarf_csr_66,
+ dwarf_csr_67,
+ dwarf_csr_68,
+ dwarf_csr_69,
+ dwarf_csr_70,
+ dwarf_csr_71,
+ dwarf_csr_72,
+ dwarf_csr_73,
+ dwarf_csr_74,
+ dwarf_csr_75,
+ dwarf_csr_76,
+ dwarf_csr_77,
+ dwarf_csr_78,
+ dwarf_csr_79,
+ dwarf_csr_80,
+ dwarf_csr_81,
+ dwarf_csr_82,
+ dwarf_csr_83,
+ dwarf_csr_84,
+ dwarf_csr_85,
+ dwarf_csr_86,
+ dwarf_csr_87,
+ dwarf_csr_88,
+ dwarf_csr_89,
+ dwarf_csr_90,
+ dwarf_csr_91,
+ dwarf_csr_92,
+ dwarf_csr_93,
+ dwarf_csr_94,
+ dwarf_csr_95,
+ dwarf_csr_96,
+ dwarf_csr_97,
+ dwarf_csr_98,
+ dwarf_csr_99,
+ dwarf_csr_100,
+ dwarf_csr_101,
+ dwarf_csr_102,
+ dwarf_csr_103,
+ dwarf_csr_104,
+ dwarf_csr_105,
+ dwarf_csr_106,
+ dwarf_csr_107,
+ dwarf_csr_108,
+ dwarf_csr_109,
+ dwarf_csr_110,
+ dwarf_csr_111,
+ dwarf_csr_112,
+ dwarf_csr_113,
+ dwarf_csr_114,
+ dwarf_csr_115,
+ dwarf_csr_116,
+ dwarf_csr_117,
+ dwarf_csr_118,
+ dwarf_csr_119,
+ dwarf_csr_120,
+ dwarf_csr_121,
+ dwarf_csr_122,
+ dwarf_csr_123,
+ dwarf_csr_124,
+ dwarf_csr_125,
+ dwarf_csr_126,
+ dwarf_csr_127,
+ dwarf_csr_128,
+ dwarf_csr_129,
+ dwarf_csr_130,
+ dwarf_csr_131,
+ dwarf_csr_132,
+ dwarf_csr_133,
+ dwarf_csr_134,
+ dwarf_csr_135,
+ dwarf_csr_136,
+ dwarf_csr_137,
+ dwarf_csr_138,
+ dwarf_csr_139,
+ dwarf_csr_140,
+ dwarf_csr_141,
+ dwarf_csr_142,
+ dwarf_csr_143,
+ dwarf_csr_144,
+ dwarf_csr_145,
+ dwarf_csr_146,
+ dwarf_csr_147,
+ dwarf_csr_148,
+ dwarf_csr_149,
+ dwarf_csr_150,
+ dwarf_csr_151,
+ dwarf_csr_152,
+ dwarf_csr_153,
+ dwarf_csr_154,
+ dwarf_csr_155,
+ dwarf_csr_156,
+ dwarf_csr_157,
+ dwarf_csr_158,
+ dwarf_csr_159,
+ dwarf_csr_160,
+ dwarf_csr_161,
+ dwarf_csr_162,
+ dwarf_csr_163,
+ dwarf_csr_164,
+ dwarf_csr_165,
+ dwarf_csr_166,
+ dwarf_csr_167,
+ dwarf_csr_168,
+ dwarf_csr_169,
+ dwarf_csr_170,
+ dwarf_csr_171,
+ dwarf_csr_172,
+ dwarf_csr_173,
+ dwarf_csr_174,
+ dwarf_csr_175,
+ dwarf_csr_176,
+ dwarf_csr_177,
+ dwarf_csr_178,
+ dwarf_csr_179,
+ dwarf_csr_180,
+ dwarf_csr_181,
+ dwarf_csr_182,
+ dwarf_csr_183,
+ dwarf_csr_184,
+ dwarf_csr_185,
+ dwarf_csr_186,
+ dwarf_csr_187,
+ dwarf_csr_188,
+ dwarf_csr_189,
+ dwarf_csr_190,
+ dwarf_csr_191,
+ dwarf_csr_192,
+ dwarf_csr_193,
+ dwarf_csr_194,
+ dwarf_csr_195,
+ dwarf_csr_196,
+ dwarf_csr_197,
+ dwarf_csr_198,
+ dwarf_csr_199,
+ dwarf_csr_200,
+ dwarf_csr_201,
+ dwarf_csr_202,
+ dwarf_csr_203,
+ dwarf_csr_204,
+ dwarf_csr_205,
+ dwarf_csr_206,
+ dwarf_csr_207,
+ dwarf_csr_208,
+ dwarf_csr_209,
+ dwarf_csr_210,
+ dwarf_csr_211,
+ dwarf_csr_212,
+ dwarf_csr_213,
+ dwarf_csr_214,
+ dwarf_csr_215,
+ dwarf_csr_216,
+ dwarf_csr_217,
+ dwarf_csr_218,
+ dwarf_csr_219,
+ dwarf_csr_220,
+ dwarf_csr_221,
+ dwarf_csr_222,
+ dwarf_csr_223,
+ dwarf_csr_224,
+ dwarf_csr_225,
+ dwarf_csr_226,
+ dwarf_csr_227,
+ dwarf_csr_228,
+ dwarf_csr_229,
+ dwarf_csr_230,
+ dwarf_csr_231,
+ dwarf_csr_232,
+ dwarf_csr_233,
+ dwarf_csr_234,
+ dwarf_csr_235,
+ dwarf_csr_236,
+ dwarf_csr_237,
+ dwarf_csr_238,
+ dwarf_csr_239,
+ dwarf_csr_240,
+ dwarf_csr_241,
+ dwarf_csr_242,
+ dwarf_csr_243,
+ dwarf_csr_244,
+ dwarf_csr_245,
+ dwarf_csr_246,
+ dwarf_csr_247,
+ dwarf_csr_248,
+ dwarf_csr_249,
+ dwarf_csr_250,
+ dwarf_csr_251,
+ dwarf_csr_252,
+ dwarf_csr_253,
+ dwarf_csr_254,
+ dwarf_csr_255,
+ dwarf_csr_256,
+ dwarf_csr_257,
+ dwarf_csr_258,
+ dwarf_csr_259,
+ dwarf_csr_260,
+ dwarf_csr_261,
+ dwarf_csr_262,
+ dwarf_csr_263,
+ dwarf_csr_264,
+ dwarf_csr_265,
+ dwarf_csr_266,
+ dwarf_csr_267,
+ dwarf_csr_268,
+ dwarf_csr_269,
+ dwarf_csr_270,
+ dwarf_csr_271,
+ dwarf_csr_272,
+ dwarf_csr_273,
+ dwarf_csr_274,
+ dwarf_csr_275,
+ dwarf_csr_276,
+ dwarf_csr_277,
+ dwarf_csr_278,
+ dwarf_csr_279,
+ dwarf_csr_280,
+ dwarf_csr_281,
+ dwarf_csr_282,
+ dwarf_csr_283,
+ dwarf_csr_284,
+ dwarf_csr_285,
+ dwarf_csr_286,
+ dwarf_csr_287,
+ dwarf_csr_288,
+ dwarf_csr_289,
+ dwarf_csr_290,
+ dwarf_csr_291,
+ dwarf_csr_292,
+ dwarf_csr_293,
+ dwarf_csr_294,
+ dwarf_csr_295,
+ dwarf_csr_296,
+ dwarf_csr_297,
+ dwarf_csr_298,
+ dwarf_csr_299,
+ dwarf_csr_300,
+ dwarf_csr_301,
+ dwarf_csr_302,
+ dwarf_csr_303,
+ dwarf_csr_304,
+ dwarf_csr_305,
+ dwarf_csr_306,
+ dwarf_csr_307,
+ dwarf_csr_308,
+ dwarf_csr_309,
+ dwarf_csr_310,
+ dwarf_csr_311,
+ dwarf_csr_312,
+ dwarf_csr_313,
+ dwarf_csr_314,
+ dwarf_csr_315,
+ dwarf_csr_316,
+ dwarf_csr_317,
+ dwarf_csr_318,
+ dwarf_csr_319,
+ dwarf_csr_320,
+ dwarf_csr_321,
+ dwarf_csr_322,
+ dwarf_csr_323,
+ dwarf_csr_324,
+ dwarf_csr_325,
+ dwarf_csr_326,
+ dwarf_csr_327,
+ dwarf_csr_328,
+ dwarf_csr_329,
+ dwarf_csr_330,
+ dwarf_csr_331,
+ dwarf_csr_332,
+ dwarf_csr_333,
+ dwarf_csr_334,
+ dwarf_csr_335,
+ dwarf_csr_336,
+ dwarf_csr_337,
+ dwarf_csr_338,
+ dwarf_csr_339,
+ dwarf_csr_340,
+ dwarf_csr_341,
+ dwarf_csr_342,
+ dwarf_csr_343,
+ dwarf_csr_344,
+ dwarf_csr_345,
+ dwarf_csr_346,
+ dwarf_csr_347,
+ dwarf_csr_348,
+ dwarf_csr_349,
+ dwarf_csr_350,
+ dwarf_csr_351,
+ dwarf_csr_352,
+ dwarf_csr_353,
+ dwarf_csr_354,
+ dwarf_csr_355,
+ dwarf_csr_356,
+ dwarf_csr_357,
+ dwarf_csr_358,
+ dwarf_csr_359,
+ dwarf_csr_360,
+ dwarf_csr_361,
+ dwarf_csr_362,
+ dwarf_csr_363,
+ dwarf_csr_364,
+ dwarf_csr_365,
+ dwarf_csr_366,
+ dwarf_csr_367,
+ dwarf_csr_368,
+ dwarf_csr_369,
+ dwarf_csr_370,
+ dwarf_csr_371,
+ dwarf_csr_372,
+ dwarf_csr_373,
+ dwarf_csr_374,
+ dwarf_csr_375,
+ dwarf_csr_376,
+ dwarf_csr_377,
+ dwarf_csr_378,
+ dwarf_csr_379,
+ dwarf_csr_380,
+ dwarf_csr_381,
+ dwarf_csr_382,
+ dwarf_csr_383,
+ dwarf_csr_384,
+ dwarf_csr_385,
+ dwarf_csr_386,
+ dwarf_csr_387,
+ dwarf_csr_388,
+ dwarf_csr_389,
+ dwarf_csr_390,
+ dwarf_csr_391,
+ dwarf_csr_392,
+ dwarf_csr_393,
+ dwarf_csr_394,
+ dwarf_csr_395,
+ dwarf_csr_396,
+ dwarf_csr_397,
+ dwarf_csr_398,
+ dwarf_csr_399,
+ dwarf_csr_400,
+ dwarf_csr_401,
+ dwarf_csr_402,
+ dwarf_csr_403,
+ dwarf_csr_404,
+ dwarf_csr_405,
+ dwarf_csr_406,
+ dwarf_csr_407,
+ dwarf_csr_408,
+ dwarf_csr_409,
+ dwarf_csr_410,
+ dwarf_csr_411,
+ dwarf_csr_412,
+ dwarf_csr_413,
+ dwarf_csr_414,
+ dwarf_csr_415,
+ dwarf_csr_416,
+ dwarf_csr_417,
+ dwarf_csr_418,
+ dwarf_csr_419,
+ dwarf_csr_420,
+ dwarf_csr_421,
+ dwarf_csr_422,
+ dwarf_csr_423,
+ dwarf_csr_424,
+ dwarf_csr_425,
+ dwarf_csr_426,
+ dwarf_csr_427,
+ dwarf_csr_428,
+ dwarf_csr_429,
+ dwarf_csr_430,
+ dwarf_csr_431,
+ dwarf_csr_432,
+ dwarf_csr_433,
+ dwarf_csr_434,
+ dwarf_csr_435,
+ dwarf_csr_436,
+ dwarf_csr_437,
+ dwarf_csr_438,
+ dwarf_csr_439,
+ dwarf_csr_440,
+ dwarf_csr_441,
+ dwarf_csr_442,
+ dwarf_csr_443,
+ dwarf_csr_444,
+ dwarf_csr_445,
+ dwarf_csr_446,
+ dwarf_csr_447,
+ dwarf_csr_448,
+ dwarf_csr_449,
+ dwarf_csr_450,
+ dwarf_csr_451,
+ dwarf_csr_452,
+ dwarf_csr_453,
+ dwarf_csr_454,
+ dwarf_csr_455,
+ dwarf_csr_456,
+ dwarf_csr_457,
+ dwarf_csr_458,
+ dwarf_csr_459,
+ dwarf_csr_460,
+ dwarf_csr_461,
+ dwarf_csr_462,
+ dwarf_csr_463,
+ dwarf_csr_464,
+ dwarf_csr_465,
+ dwarf_csr_466,
+ dwarf_csr_467,
+ dwarf_csr_468,
+ dwarf_csr_469,
+ dwarf_csr_470,
+ dwarf_csr_471,
+ dwarf_csr_472,
+ dwarf_csr_473,
+ dwarf_csr_474,
+ dwarf_csr_475,
+ dwarf_csr_476,
+ dwarf_csr_477,
+ dwarf_csr_478,
+ dwarf_csr_479,
+ dwarf_csr_480,
+ dwarf_csr_481,
+ dwarf_csr_482,
+ dwarf_csr_483,
+ dwarf_csr_484,
+ dwarf_csr_485,
+ dwarf_csr_486,
+ dwarf_csr_487,
+ dwarf_csr_488,
+ dwarf_csr_489,
+ dwarf_csr_490,
+ dwarf_csr_491,
+ dwarf_csr_492,
+ dwarf_csr_493,
+ dwarf_csr_494,
+ dwarf_csr_495,
+ dwarf_csr_496,
+ dwarf_csr_497,
+ dwarf_csr_498,
+ dwarf_csr_499,
+ dwarf_csr_500,
+ dwarf_csr_501,
+ dwarf_csr_502,
+ dwarf_csr_503,
+ dwarf_csr_504,
+ dwarf_csr_505,
+ dwarf_csr_506,
+ dwarf_csr_507,
+ dwarf_csr_508,
+ dwarf_csr_509,
+ dwarf_csr_510,
+ dwarf_csr_511,
+ dwarf_csr_512,
+ dwarf_csr_513,
+ dwarf_csr_514,
+ dwarf_csr_515,
+ dwarf_csr_516,
+ dwarf_csr_517,
+ dwarf_csr_518,
+ dwarf_csr_519,
+ dwarf_csr_520,
+ dwarf_csr_521,
+ dwarf_csr_522,
+ dwarf_csr_523,
+ dwarf_csr_524,
+ dwarf_csr_525,
+ dwarf_csr_526,
+ dwarf_csr_527,
+ dwarf_csr_528,
+ dwarf_csr_529,
+ dwarf_csr_530,
+ dwarf_csr_531,
+ dwarf_csr_532,
+ dwarf_csr_533,
+ dwarf_csr_534,
+ dwarf_csr_535,
+ dwarf_csr_536,
+ dwarf_csr_537,
+ dwarf_csr_538,
+ dwarf_csr_539,
+ dwarf_csr_540,
+ dwarf_csr_541,
+ dwarf_csr_542,
+ dwarf_csr_543,
+ dwarf_csr_544,
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+ dwarf_csr_3557,
+ dwarf_csr_3558,
+ dwarf_csr_3559,
+ dwarf_csr_3560,
+ dwarf_csr_3561,
+ dwarf_csr_3562,
+ dwarf_csr_3563,
+ dwarf_csr_3564,
+ dwarf_csr_3565,
+ dwarf_csr_3566,
+ dwarf_csr_3567,
+ dwarf_csr_3568,
+ dwarf_csr_3569,
+ dwarf_csr_3570,
+ dwarf_csr_3571,
+ dwarf_csr_3572,
+ dwarf_csr_3573,
+ dwarf_csr_3574,
+ dwarf_csr_3575,
+ dwarf_csr_3576,
+ dwarf_csr_3577,
+ dwarf_csr_3578,
+ dwarf_csr_3579,
+ dwarf_csr_3580,
+ dwarf_csr_3581,
+ dwarf_csr_3582,
+ dwarf_csr_3583,
+ dwarf_csr_3584,
+ dwarf_csr_3585,
+ dwarf_csr_3586,
+ dwarf_csr_3587,
+ dwarf_csr_3588,
+ dwarf_csr_3589,
+ dwarf_csr_3590,
+ dwarf_csr_3591,
+ dwarf_csr_3592,
+ dwarf_csr_3593,
+ dwarf_csr_3594,
+ dwarf_csr_3595,
+ dwarf_csr_3596,
+ dwarf_csr_3597,
+ dwarf_csr_3598,
+ dwarf_csr_3599,
+ dwarf_csr_3600,
+ dwarf_csr_3601,
+ dwarf_csr_3602,
+ dwarf_csr_3603,
+ dwarf_csr_3604,
+ dwarf_csr_3605,
+ dwarf_csr_3606,
+ dwarf_csr_3607,
+ dwarf_csr_3608,
+ dwarf_csr_3609,
+ dwarf_csr_3610,
+ dwarf_csr_3611,
+ dwarf_csr_3612,
+ dwarf_csr_3613,
+ dwarf_csr_3614,
+ dwarf_csr_3615,
+ dwarf_csr_3616,
+ dwarf_csr_3617,
+ dwarf_csr_3618,
+ dwarf_csr_3619,
+ dwarf_csr_3620,
+ dwarf_csr_3621,
+ dwarf_csr_3622,
+ dwarf_csr_3623,
+ dwarf_csr_3624,
+ dwarf_csr_3625,
+ dwarf_csr_3626,
+ dwarf_csr_3627,
+ dwarf_csr_3628,
+ dwarf_csr_3629,
+ dwarf_csr_3630,
+ dwarf_csr_3631,
+ dwarf_csr_3632,
+ dwarf_csr_3633,
+ dwarf_csr_3634,
+ dwarf_csr_3635,
+ dwarf_csr_3636,
+ dwarf_csr_3637,
+ dwarf_csr_3638,
+ dwarf_csr_3639,
+ dwarf_csr_3640,
+ dwarf_csr_3641,
+ dwarf_csr_3642,
+ dwarf_csr_3643,
+ dwarf_csr_3644,
+ dwarf_csr_3645,
+ dwarf_csr_3646,
+ dwarf_csr_3647,
+ dwarf_csr_3648,
+ dwarf_csr_3649,
+ dwarf_csr_3650,
+ dwarf_csr_3651,
+ dwarf_csr_3652,
+ dwarf_csr_3653,
+ dwarf_csr_3654,
+ dwarf_csr_3655,
+ dwarf_csr_3656,
+ dwarf_csr_3657,
+ dwarf_csr_3658,
+ dwarf_csr_3659,
+ dwarf_csr_3660,
+ dwarf_csr_3661,
+ dwarf_csr_3662,
+ dwarf_csr_3663,
+ dwarf_csr_3664,
+ dwarf_csr_3665,
+ dwarf_csr_3666,
+ dwarf_csr_3667,
+ dwarf_csr_3668,
+ dwarf_csr_3669,
+ dwarf_csr_3670,
+ dwarf_csr_3671,
+ dwarf_csr_3672,
+ dwarf_csr_3673,
+ dwarf_csr_3674,
+ dwarf_csr_3675,
+ dwarf_csr_3676,
+ dwarf_csr_3677,
+ dwarf_csr_3678,
+ dwarf_csr_3679,
+ dwarf_csr_3680,
+ dwarf_csr_3681,
+ dwarf_csr_3682,
+ dwarf_csr_3683,
+ dwarf_csr_3684,
+ dwarf_csr_3685,
+ dwarf_csr_3686,
+ dwarf_csr_3687,
+ dwarf_csr_3688,
+ dwarf_csr_3689,
+ dwarf_csr_3690,
+ dwarf_csr_3691,
+ dwarf_csr_3692,
+ dwarf_csr_3693,
+ dwarf_csr_3694,
+ dwarf_csr_3695,
+ dwarf_csr_3696,
+ dwarf_csr_3697,
+ dwarf_csr_3698,
+ dwarf_csr_3699,
+ dwarf_csr_3700,
+ dwarf_csr_3701,
+ dwarf_csr_3702,
+ dwarf_csr_3703,
+ dwarf_csr_3704,
+ dwarf_csr_3705,
+ dwarf_csr_3706,
+ dwarf_csr_3707,
+ dwarf_csr_3708,
+ dwarf_csr_3709,
+ dwarf_csr_3710,
+ dwarf_csr_3711,
+ dwarf_csr_3712,
+ dwarf_csr_3713,
+ dwarf_csr_3714,
+ dwarf_csr_3715,
+ dwarf_csr_3716,
+ dwarf_csr_3717,
+ dwarf_csr_3718,
+ dwarf_csr_3719,
+ dwarf_csr_3720,
+ dwarf_csr_3721,
+ dwarf_csr_3722,
+ dwarf_csr_3723,
+ dwarf_csr_3724,
+ dwarf_csr_3725,
+ dwarf_csr_3726,
+ dwarf_csr_3727,
+ dwarf_csr_3728,
+ dwarf_csr_3729,
+ dwarf_csr_3730,
+ dwarf_csr_3731,
+ dwarf_csr_3732,
+ dwarf_csr_3733,
+ dwarf_csr_3734,
+ dwarf_csr_3735,
+ dwarf_csr_3736,
+ dwarf_csr_3737,
+ dwarf_csr_3738,
+ dwarf_csr_3739,
+ dwarf_csr_3740,
+ dwarf_csr_3741,
+ dwarf_csr_3742,
+ dwarf_csr_3743,
+ dwarf_csr_3744,
+ dwarf_csr_3745,
+ dwarf_csr_3746,
+ dwarf_csr_3747,
+ dwarf_csr_3748,
+ dwarf_csr_3749,
+ dwarf_csr_3750,
+ dwarf_csr_3751,
+ dwarf_csr_3752,
+ dwarf_csr_3753,
+ dwarf_csr_3754,
+ dwarf_csr_3755,
+ dwarf_csr_3756,
+ dwarf_csr_3757,
+ dwarf_csr_3758,
+ dwarf_csr_3759,
+ dwarf_csr_3760,
+ dwarf_csr_3761,
+ dwarf_csr_3762,
+ dwarf_csr_3763,
+ dwarf_csr_3764,
+ dwarf_csr_3765,
+ dwarf_csr_3766,
+ dwarf_csr_3767,
+ dwarf_csr_3768,
+ dwarf_csr_3769,
+ dwarf_csr_3770,
+ dwarf_csr_3771,
+ dwarf_csr_3772,
+ dwarf_csr_3773,
+ dwarf_csr_3774,
+ dwarf_csr_3775,
+ dwarf_csr_3776,
+ dwarf_csr_3777,
+ dwarf_csr_3778,
+ dwarf_csr_3779,
+ dwarf_csr_3780,
+ dwarf_csr_3781,
+ dwarf_csr_3782,
+ dwarf_csr_3783,
+ dwarf_csr_3784,
+ dwarf_csr_3785,
+ dwarf_csr_3786,
+ dwarf_csr_3787,
+ dwarf_csr_3788,
+ dwarf_csr_3789,
+ dwarf_csr_3790,
+ dwarf_csr_3791,
+ dwarf_csr_3792,
+ dwarf_csr_3793,
+ dwarf_csr_3794,
+ dwarf_csr_3795,
+ dwarf_csr_3796,
+ dwarf_csr_3797,
+ dwarf_csr_3798,
+ dwarf_csr_3799,
+ dwarf_csr_3800,
+ dwarf_csr_3801,
+ dwarf_csr_3802,
+ dwarf_csr_3803,
+ dwarf_csr_3804,
+ dwarf_csr_3805,
+ dwarf_csr_3806,
+ dwarf_csr_3807,
+ dwarf_csr_3808,
+ dwarf_csr_3809,
+ dwarf_csr_3810,
+ dwarf_csr_3811,
+ dwarf_csr_3812,
+ dwarf_csr_3813,
+ dwarf_csr_3814,
+ dwarf_csr_3815,
+ dwarf_csr_3816,
+ dwarf_csr_3817,
+ dwarf_csr_3818,
+ dwarf_csr_3819,
+ dwarf_csr_3820,
+ dwarf_csr_3821,
+ dwarf_csr_3822,
+ dwarf_csr_3823,
+ dwarf_csr_3824,
+ dwarf_csr_3825,
+ dwarf_csr_3826,
+ dwarf_csr_3827,
+ dwarf_csr_3828,
+ dwarf_csr_3829,
+ dwarf_csr_3830,
+ dwarf_csr_3831,
+ dwarf_csr_3832,
+ dwarf_csr_3833,
+ dwarf_csr_3834,
+ dwarf_csr_3835,
+ dwarf_csr_3836,
+ dwarf_csr_3837,
+ dwarf_csr_3838,
+ dwarf_csr_3839,
+ dwarf_csr_3840,
+ dwarf_csr_3841,
+ dwarf_csr_3842,
+ dwarf_csr_3843,
+ dwarf_csr_3844,
+ dwarf_csr_3845,
+ dwarf_csr_3846,
+ dwarf_csr_3847,
+ dwarf_csr_3848,
+ dwarf_csr_3849,
+ dwarf_csr_3850,
+ dwarf_csr_3851,
+ dwarf_csr_3852,
+ dwarf_csr_3853,
+ dwarf_csr_3854,
+ dwarf_csr_3855,
+ dwarf_csr_3856,
+ dwarf_csr_3857,
+ dwarf_csr_3858,
+ dwarf_csr_3859,
+ dwarf_csr_3860,
+ dwarf_csr_3861,
+ dwarf_csr_3862,
+ dwarf_csr_3863,
+ dwarf_csr_3864,
+ dwarf_csr_3865,
+ dwarf_csr_3866,
+ dwarf_csr_3867,
+ dwarf_csr_3868,
+ dwarf_csr_3869,
+ dwarf_csr_3870,
+ dwarf_csr_3871,
+ dwarf_csr_3872,
+ dwarf_csr_3873,
+ dwarf_csr_3874,
+ dwarf_csr_3875,
+ dwarf_csr_3876,
+ dwarf_csr_3877,
+ dwarf_csr_3878,
+ dwarf_csr_3879,
+ dwarf_csr_3880,
+ dwarf_csr_3881,
+ dwarf_csr_3882,
+ dwarf_csr_3883,
+ dwarf_csr_3884,
+ dwarf_csr_3885,
+ dwarf_csr_3886,
+ dwarf_csr_3887,
+ dwarf_csr_3888,
+ dwarf_csr_3889,
+ dwarf_csr_3890,
+ dwarf_csr_3891,
+ dwarf_csr_3892,
+ dwarf_csr_3893,
+ dwarf_csr_3894,
+ dwarf_csr_3895,
+ dwarf_csr_3896,
+ dwarf_csr_3897,
+ dwarf_csr_3898,
+ dwarf_csr_3899,
+ dwarf_csr_3900,
+ dwarf_csr_3901,
+ dwarf_csr_3902,
+ dwarf_csr_3903,
+ dwarf_csr_3904,
+ dwarf_csr_3905,
+ dwarf_csr_3906,
+ dwarf_csr_3907,
+ dwarf_csr_3908,
+ dwarf_csr_3909,
+ dwarf_csr_3910,
+ dwarf_csr_3911,
+ dwarf_csr_3912,
+ dwarf_csr_3913,
+ dwarf_csr_3914,
+ dwarf_csr_3915,
+ dwarf_csr_3916,
+ dwarf_csr_3917,
+ dwarf_csr_3918,
+ dwarf_csr_3919,
+ dwarf_csr_3920,
+ dwarf_csr_3921,
+ dwarf_csr_3922,
+ dwarf_csr_3923,
+ dwarf_csr_3924,
+ dwarf_csr_3925,
+ dwarf_csr_3926,
+ dwarf_csr_3927,
+ dwarf_csr_3928,
+ dwarf_csr_3929,
+ dwarf_csr_3930,
+ dwarf_csr_3931,
+ dwarf_csr_3932,
+ dwarf_csr_3933,
+ dwarf_csr_3934,
+ dwarf_csr_3935,
+ dwarf_csr_3936,
+ dwarf_csr_3937,
+ dwarf_csr_3938,
+ dwarf_csr_3939,
+ dwarf_csr_3940,
+ dwarf_csr_3941,
+ dwarf_csr_3942,
+ dwarf_csr_3943,
+ dwarf_csr_3944,
+ dwarf_csr_3945,
+ dwarf_csr_3946,
+ dwarf_csr_3947,
+ dwarf_csr_3948,
+ dwarf_csr_3949,
+ dwarf_csr_3950,
+ dwarf_csr_3951,
+ dwarf_csr_3952,
+ dwarf_csr_3953,
+ dwarf_csr_3954,
+ dwarf_csr_3955,
+ dwarf_csr_3956,
+ dwarf_csr_3957,
+ dwarf_csr_3958,
+ dwarf_csr_3959,
+ dwarf_csr_3960,
+ dwarf_csr_3961,
+ dwarf_csr_3962,
+ dwarf_csr_3963,
+ dwarf_csr_3964,
+ dwarf_csr_3965,
+ dwarf_csr_3966,
+ dwarf_csr_3967,
+ dwarf_csr_3968,
+ dwarf_csr_3969,
+ dwarf_csr_3970,
+ dwarf_csr_3971,
+ dwarf_csr_3972,
+ dwarf_csr_3973,
+ dwarf_csr_3974,
+ dwarf_csr_3975,
+ dwarf_csr_3976,
+ dwarf_csr_3977,
+ dwarf_csr_3978,
+ dwarf_csr_3979,
+ dwarf_csr_3980,
+ dwarf_csr_3981,
+ dwarf_csr_3982,
+ dwarf_csr_3983,
+ dwarf_csr_3984,
+ dwarf_csr_3985,
+ dwarf_csr_3986,
+ dwarf_csr_3987,
+ dwarf_csr_3988,
+ dwarf_csr_3989,
+ dwarf_csr_3990,
+ dwarf_csr_3991,
+ dwarf_csr_3992,
+ dwarf_csr_3993,
+ dwarf_csr_3994,
+ dwarf_csr_3995,
+ dwarf_csr_3996,
+ dwarf_csr_3997,
+ dwarf_csr_3998,
+ dwarf_csr_3999,
+ dwarf_csr_4000,
+ dwarf_csr_4001,
+ dwarf_csr_4002,
+ dwarf_csr_4003,
+ dwarf_csr_4004,
+ dwarf_csr_4005,
+ dwarf_csr_4006,
+ dwarf_csr_4007,
+ dwarf_csr_4008,
+ dwarf_csr_4009,
+ dwarf_csr_4010,
+ dwarf_csr_4011,
+ dwarf_csr_4012,
+ dwarf_csr_4013,
+ dwarf_csr_4014,
+ dwarf_csr_4015,
+ dwarf_csr_4016,
+ dwarf_csr_4017,
+ dwarf_csr_4018,
+ dwarf_csr_4019,
+ dwarf_csr_4020,
+ dwarf_csr_4021,
+ dwarf_csr_4022,
+ dwarf_csr_4023,
+ dwarf_csr_4024,
+ dwarf_csr_4025,
+ dwarf_csr_4026,
+ dwarf_csr_4027,
+ dwarf_csr_4028,
+ dwarf_csr_4029,
+ dwarf_csr_4030,
+ dwarf_csr_4031,
+ dwarf_csr_4032,
+ dwarf_csr_4033,
+ dwarf_csr_4034,
+ dwarf_csr_4035,
+ dwarf_csr_4036,
+ dwarf_csr_4037,
+ dwarf_csr_4038,
+ dwarf_csr_4039,
+ dwarf_csr_4040,
+ dwarf_csr_4041,
+ dwarf_csr_4042,
+ dwarf_csr_4043,
+ dwarf_csr_4044,
+ dwarf_csr_4045,
+ dwarf_csr_4046,
+ dwarf_csr_4047,
+ dwarf_csr_4048,
+ dwarf_csr_4049,
+ dwarf_csr_4050,
+ dwarf_csr_4051,
+ dwarf_csr_4052,
+ dwarf_csr_4053,
+ dwarf_csr_4054,
+ dwarf_csr_4055,
+ dwarf_csr_4056,
+ dwarf_csr_4057,
+ dwarf_csr_4058,
+ dwarf_csr_4059,
+ dwarf_csr_4060,
+ dwarf_csr_4061,
+ dwarf_csr_4062,
+ dwarf_csr_4063,
+ dwarf_csr_4064,
+ dwarf_csr_4065,
+ dwarf_csr_4066,
+ dwarf_csr_4067,
+ dwarf_csr_4068,
+ dwarf_csr_4069,
+ dwarf_csr_4070,
+ dwarf_csr_4071,
+ dwarf_csr_4072,
+ dwarf_csr_4073,
+ dwarf_csr_4074,
+ dwarf_csr_4075,
+ dwarf_csr_4076,
+ dwarf_csr_4077,
+ dwarf_csr_4078,
+ dwarf_csr_4079,
+ dwarf_csr_4080,
+ dwarf_csr_4081,
+ dwarf_csr_4082,
+ dwarf_csr_4083,
+ dwarf_csr_4084,
+ dwarf_csr_4085,
+ dwarf_csr_4086,
+ dwarf_csr_4087,
+ dwarf_csr_4088,
+ dwarf_csr_4089,
+ dwarf_csr_4090,
+ dwarf_csr_4091,
+ dwarf_csr_4092,
+ dwarf_csr_4093,
+ dwarf_csr_4094,
+ dwarf_csr_4095 = 8191,
+
+ dwarf_first_csr = dwarf_csr_0,
+ // The single-precision floating-point extension adds a floating-point CSR
+ // (fcsr) to a base scalar RISC-V ISA.
+ dwarf_fpr_fcsr = dwarf_csr_3,
+ // The vector extension adds seven unprivileged CSRs (vstart, vxsat, vxrm,
+ // vcsr, vtype, vl, vlenb) to a base scalar RISC-V ISA.
+ dwarf_vpr_vstart = dwarf_csr_8,
+ dwarf_vpr_vxsat = dwarf_csr_9,
+ dwarf_vpr_vxrm = dwarf_csr_10,
+ dwarf_vpr_vcsr = dwarf_csr_15,
+ dwarf_vpr_vl = dwarf_csr_3104,
+ dwarf_vpr_vtype = dwarf_csr_3105,
+ dwarf_vpr_vlenb = dwarf_csr_3106,
+ dwarf_last_csr = dwarf_csr_4095,
// register ABI name
dwarf_gpr_zero = dwarf_gpr_x0,
@@ -196,6 +4297,381 @@ enum {
dwarf_fpr_ft10 = dwarf_fpr_f30,
dwarf_fpr_ft11 = dwarf_fpr_f31,
+ dwarf_csr_fflags = dwarf_csr_1,
+ dwarf_csr_frm = dwarf_csr_2,
+ dwarf_csr_fcsr = dwarf_csr_3,
+ dwarf_csr_vstart = dwarf_csr_8,
+ dwarf_csr_vxsat = dwarf_csr_9,
+ dwarf_csr_vxrm = dwarf_csr_10,
+ dwarf_csr_vcsr = dwarf_csr_15,
+ dwarf_csr_sstatus = dwarf_csr_256,
+ dwarf_csr_sie = dwarf_csr_260,
+ dwarf_csr_stvec = dwarf_csr_261,
+ dwarf_csr_scounteren = dwarf_csr_262,
+ dwarf_csr_senvcfg = dwarf_csr_266,
+ dwarf_csr_sstateen0 = dwarf_csr_268,
+ dwarf_csr_sstateen1 = dwarf_csr_269,
+ dwarf_csr_sstateen2 = dwarf_csr_270,
+ dwarf_csr_sstateen3 = dwarf_csr_271,
+ dwarf_csr_scountinhibit = dwarf_csr_288,
+ dwarf_csr_sscratch = dwarf_csr_320,
+ dwarf_csr_sepc = dwarf_csr_321,
+ dwarf_csr_scause = dwarf_csr_322,
+ dwarf_csr_stval = dwarf_csr_323,
+ dwarf_csr_sip = dwarf_csr_324,
+ dwarf_csr_satp = dwarf_csr_384,
+ dwarf_csr_vsstatus = dwarf_csr_512,
+ dwarf_csr_vsie = dwarf_csr_516,
+ dwarf_csr_vstvec = dwarf_csr_517,
+ dwarf_csr_vsscratch = dwarf_csr_576,
+ dwarf_csr_vsepc = dwarf_csr_577,
+ dwarf_csr_vscause = dwarf_csr_578,
+ dwarf_csr_vstval = dwarf_csr_579,
+ dwarf_csr_vsip = dwarf_csr_580,
+ dwarf_csr_vsatp = dwarf_csr_640,
+ dwarf_csr_mstatus = dwarf_csr_768,
+ dwarf_csr_misa = dwarf_csr_769,
+ dwarf_csr_medeleg = dwarf_csr_770,
+ dwarf_csr_mideleg = dwarf_csr_771,
+ dwarf_csr_mie = dwarf_csr_772,
+ dwarf_csr_mtvec = dwarf_csr_773,
+ dwarf_csr_mcounteren = dwarf_csr_774,
+ dwarf_csr_menvcfg = dwarf_csr_778,
+ dwarf_csr_mstateen0 = dwarf_csr_780,
+ dwarf_csr_mstateen1 = dwarf_csr_781,
+ dwarf_csr_mstateen2 = dwarf_csr_782,
+ dwarf_csr_mstateen3 = dwarf_csr_783,
+ dwarf_csr_mstatush = dwarf_csr_784,
+ dwarf_csr_medelegh = dwarf_csr_786,
+ dwarf_csr_menvcfgh = dwarf_csr_794,
+ dwarf_csr_mstateen0h = dwarf_csr_796,
+ dwarf_csr_mstateen1h = dwarf_csr_797,
+ dwarf_csr_mstateen2h = dwarf_csr_798,
+ dwarf_csr_mstateen3h = dwarf_csr_799,
+ dwarf_csr_mcountinhibit = dwarf_csr_800,
+ dwarf_csr_mhpmevent3 = dwarf_csr_803,
+ dwarf_csr_mhpmevent4 = dwarf_csr_804,
+ dwarf_csr_mhpmevent5 = dwarf_csr_805,
+ dwarf_csr_mhpmevent6 = dwarf_csr_806,
+ dwarf_csr_mhpmevent7 = dwarf_csr_807,
+ dwarf_csr_mhpmevent8 = dwarf_csr_808,
+ dwarf_csr_mhpmevent9 = dwarf_csr_809,
+ dwarf_csr_mhpmevent10 = dwarf_csr_810,
+ dwarf_csr_mhpmevent11 = dwarf_csr_811,
+ dwarf_csr_mhpmevent12 = dwarf_csr_812,
+ dwarf_csr_mhpmevent13 = dwarf_csr_813,
+ dwarf_csr_mhpmevent14 = dwarf_csr_814,
+ dwarf_csr_mhpmevent15 = dwarf_csr_815,
+ dwarf_csr_mhpmevent16 = dwarf_csr_816,
+ dwarf_csr_mhpmevent17 = dwarf_csr_817,
+ dwarf_csr_mhpmevent18 = dwarf_csr_818,
+ dwarf_csr_mhpmevent19 = dwarf_csr_819,
+ dwarf_csr_mhpmevent20 = dwarf_csr_820,
+ dwarf_csr_mhpmevent21 = dwarf_csr_821,
+ dwarf_csr_mhpmevent22 = dwarf_csr_822,
+ dwarf_csr_mhpmevent23 = dwarf_csr_823,
+ dwarf_csr_mhpmevent24 = dwarf_csr_824,
+ dwarf_csr_mhpmevent25 = dwarf_csr_825,
+ dwarf_csr_mhpmevent26 = dwarf_csr_826,
+ dwarf_csr_mhpmevent27 = dwarf_csr_827,
+ dwarf_csr_mhpmevent28 = dwarf_csr_828,
+ dwarf_csr_mhpmevent29 = dwarf_csr_829,
+ dwarf_csr_mhpmevent30 = dwarf_csr_830,
+ dwarf_csr_mhpmevent31 = dwarf_csr_831,
+ dwarf_csr_mscratch = dwarf_csr_832,
+ dwarf_csr_mepc = dwarf_csr_833,
+ dwarf_csr_mcause = dwarf_csr_834,
+ dwarf_csr_mtval = dwarf_csr_835,
+ dwarf_csr_mip = dwarf_csr_836,
+ dwarf_csr_mtinst = dwarf_csr_842,
+ dwarf_csr_mtval2 = dwarf_csr_843,
+ dwarf_csr_pmpcfg0 = dwarf_csr_928,
+ dwarf_csr_pmpcfg1 = dwarf_csr_929,
+ dwarf_csr_pmpcfg2 = dwarf_csr_930,
+ dwarf_csr_pmpcfg3 = dwarf_csr_931,
+ dwarf_csr_pmpcfg4 = dwarf_csr_932,
+ dwarf_csr_pmpcfg5 = dwarf_csr_933,
+ dwarf_csr_pmpcfg6 = dwarf_csr_934,
+ dwarf_csr_pmpcfg7 = dwarf_csr_935,
+ dwarf_csr_pmpcfg8 = dwarf_csr_936,
+ dwarf_csr_pmpcfg9 = dwarf_csr_937,
+ dwarf_csr_pmpcfg10 = dwarf_csr_938,
+ dwarf_csr_pmpcfg11 = dwarf_csr_939,
+ dwarf_csr_pmpcfg12 = dwarf_csr_940,
+ dwarf_csr_pmpcfg13 = dwarf_csr_941,
+ dwarf_csr_pmpcfg14 = dwarf_csr_942,
+ dwarf_csr_pmpcfg15 = dwarf_csr_943,
+ dwarf_csr_pmpaddr0 = dwarf_csr_944,
+ dwarf_csr_pmpaddr1 = dwarf_csr_945,
+ dwarf_csr_pmpaddr2 = dwarf_csr_946,
+ dwarf_csr_pmpaddr3 = dwarf_csr_947,
+ dwarf_csr_pmpaddr4 = dwarf_csr_948,
+ dwarf_csr_pmpaddr5 = dwarf_csr_949,
+ dwarf_csr_pmpaddr6 = dwarf_csr_950,
+ dwarf_csr_pmpaddr7 = dwarf_csr_951,
+ dwarf_csr_pmpaddr8 = dwarf_csr_952,
+ dwarf_csr_pmpaddr9 = dwarf_csr_953,
+ dwarf_csr_pmpaddr10 = dwarf_csr_954,
+ dwarf_csr_pmpaddr11 = dwarf_csr_955,
+ dwarf_csr_pmpaddr12 = dwarf_csr_956,
+ dwarf_csr_pmpaddr13 = dwarf_csr_957,
+ dwarf_csr_pmpaddr14 = dwarf_csr_958,
+ dwarf_csr_pmpaddr15 = dwarf_csr_959,
+ dwarf_csr_pmpaddr16 = dwarf_csr_960,
+ dwarf_csr_pmpaddr17 = dwarf_csr_961,
+ dwarf_csr_pmpaddr18 = dwarf_csr_962,
+ dwarf_csr_pmpaddr19 = dwarf_csr_963,
+ dwarf_csr_pmpaddr20 = dwarf_csr_964,
+ dwarf_csr_pmpaddr21 = dwarf_csr_965,
+ dwarf_csr_pmpaddr22 = dwarf_csr_966,
+ dwarf_csr_pmpaddr23 = dwarf_csr_967,
+ dwarf_csr_pmpaddr24 = dwarf_csr_968,
+ dwarf_csr_pmpaddr25 = dwarf_csr_969,
+ dwarf_csr_pmpaddr26 = dwarf_csr_970,
+ dwarf_csr_pmpaddr27 = dwarf_csr_971,
+ dwarf_csr_pmpaddr28 = dwarf_csr_972,
+ dwarf_csr_pmpaddr29 = dwarf_csr_973,
+ dwarf_csr_pmpaddr30 = dwarf_csr_974,
+ dwarf_csr_pmpaddr31 = dwarf_csr_975,
+ dwarf_csr_pmpaddr32 = dwarf_csr_976,
+ dwarf_csr_pmpaddr33 = dwarf_csr_977,
+ dwarf_csr_pmpaddr34 = dwarf_csr_978,
+ dwarf_csr_pmpaddr35 = dwarf_csr_979,
+ dwarf_csr_pmpaddr36 = dwarf_csr_980,
+ dwarf_csr_pmpaddr37 = dwarf_csr_981,
+ dwarf_csr_pmpaddr38 = dwarf_csr_982,
+ dwarf_csr_pmpaddr39 = dwarf_csr_983,
+ dwarf_csr_pmpaddr40 = dwarf_csr_984,
+ dwarf_csr_pmpaddr41 = dwarf_csr_985,
+ dwarf_csr_pmpaddr42 = dwarf_csr_986,
+ dwarf_csr_pmpaddr43 = dwarf_csr_987,
+ dwarf_csr_pmpaddr44 = dwarf_csr_988,
+ dwarf_csr_pmpaddr45 = dwarf_csr_989,
+ dwarf_csr_pmpaddr46 = dwarf_csr_990,
+ dwarf_csr_pmpaddr47 = dwarf_csr_991,
+ dwarf_csr_pmpaddr48 = dwarf_csr_992,
+ dwarf_csr_pmpaddr49 = dwarf_csr_993,
+ dwarf_csr_pmpaddr50 = dwarf_csr_994,
+ dwarf_csr_pmpaddr51 = dwarf_csr_995,
+ dwarf_csr_pmpaddr52 = dwarf_csr_996,
+ dwarf_csr_pmpaddr53 = dwarf_csr_997,
+ dwarf_csr_pmpaddr54 = dwarf_csr_998,
+ dwarf_csr_pmpaddr55 = dwarf_csr_999,
+ dwarf_csr_pmpaddr56 = dwarf_csr_1000,
+ dwarf_csr_pmpaddr57 = dwarf_csr_1001,
+ dwarf_csr_pmpaddr58 = dwarf_csr_1002,
+ dwarf_csr_pmpaddr59 = dwarf_csr_1003,
+ dwarf_csr_pmpaddr60 = dwarf_csr_1004,
+ dwarf_csr_pmpaddr61 = dwarf_csr_1005,
+ dwarf_csr_pmpaddr62 = dwarf_csr_1006,
+ dwarf_csr_pmpaddr63 = dwarf_csr_1007,
+ dwarf_csr_scontext = dwarf_csr_1448,
+ dwarf_csr_hstatus = dwarf_csr_1536,
+ dwarf_csr_hedeleg = dwarf_csr_1538,
+ dwarf_csr_hideleg = dwarf_csr_1539,
+ dwarf_csr_hie = dwarf_csr_1540,
+ dwarf_csr_htimedelta = dwarf_csr_1541,
+ dwarf_csr_hcounteren = dwarf_csr_1542,
+ dwarf_csr_hgeie = dwarf_csr_1543,
+ dwarf_csr_henvcfg = dwarf_csr_1546,
+ dwarf_csr_hstateen0 = dwarf_csr_1548,
+ dwarf_csr_hstateen1 = dwarf_csr_1549,
+ dwarf_csr_hstateen2 = dwarf_csr_1550,
+ dwarf_csr_hstateen3 = dwarf_csr_1551,
+ dwarf_csr_hedelegh = dwarf_csr_1554,
+ dwarf_csr_htimedeltah = dwarf_csr_1557,
+ dwarf_csr_henvcfgh = dwarf_csr_1562,
+ dwarf_csr_hstateen0h = dwarf_csr_1564,
+ dwarf_csr_hstateen1h = dwarf_csr_1565,
+ dwarf_csr_hstateen2h = dwarf_csr_1566,
+ dwarf_csr_hstateen3h = dwarf_csr_1567,
+ dwarf_csr_htval = dwarf_csr_1603,
+ dwarf_csr_hip = dwarf_csr_1604,
+ dwarf_csr_hvip = dwarf_csr_1605,
+ dwarf_csr_htinst = dwarf_csr_1610,
+ dwarf_csr_hgatp = dwarf_csr_1664,
+ dwarf_csr_hcontext = dwarf_csr_1704,
+ dwarf_csr_mhpmevent3h = dwarf_csr_1827,
+ dwarf_csr_mhpmevent4h = dwarf_csr_1828,
+ dwarf_csr_mhpmevent5h = dwarf_csr_1829,
+ dwarf_csr_mhpmevent6h = dwarf_csr_1830,
+ dwarf_csr_mhpmevent7h = dwarf_csr_1831,
+ dwarf_csr_mhpmevent8h = dwarf_csr_1832,
+ dwarf_csr_mhpmevent9h = dwarf_csr_1833,
+ dwarf_csr_mhpmevent10h = dwarf_csr_1834,
+ dwarf_csr_mhpmevent11h = dwarf_csr_1835,
+ dwarf_csr_mhpmevent12h = dwarf_csr_1836,
+ dwarf_csr_mhpmevent13h = dwarf_csr_1837,
+ dwarf_csr_mhpmevent14h = dwarf_csr_1838,
+ dwarf_csr_mhpmevent15h = dwarf_csr_1839,
+ dwarf_csr_mhpmevent16h = dwarf_csr_1840,
+ dwarf_csr_mhpmevent17h = dwarf_csr_1841,
+ dwarf_csr_mhpmevent18h = dwarf_csr_1842,
+ dwarf_csr_mhpmevent19h = dwarf_csr_1843,
+ dwarf_csr_mhpmevent20h = dwarf_csr_1844,
+ dwarf_csr_mhpmevent21h = dwarf_csr_1845,
+ dwarf_csr_mhpmevent22h = dwarf_csr_1846,
+ dwarf_csr_mhpmevent23h = dwarf_csr_1847,
+ dwarf_csr_mhpmevent24h = dwarf_csr_1848,
+ dwarf_csr_mhpmevent25h = dwarf_csr_1849,
+ dwarf_csr_mhpmevent26h = dwarf_csr_1850,
+ dwarf_csr_mhpmevent27h = dwarf_csr_1851,
+ dwarf_csr_mhpmevent28h = dwarf_csr_1852,
+ dwarf_csr_mhpmevent29h = dwarf_csr_1853,
+ dwarf_csr_mhpmevent30h = dwarf_csr_1854,
+ dwarf_csr_mhpmevent31h = dwarf_csr_1855,
+ dwarf_csr_mnscratch = dwarf_csr_1856,
+ dwarf_csr_mnepc = dwarf_csr_1857,
+ dwarf_csr_mncause = dwarf_csr_1858,
+ dwarf_csr_mnstatus = dwarf_csr_1860,
+ dwarf_csr_mseccfg = dwarf_csr_1863,
+ dwarf_csr_mseccfgh = dwarf_csr_1879,
+ dwarf_csr_tselect = dwarf_csr_1952,
+ dwarf_csr_tdata1 = dwarf_csr_1953,
+ dwarf_csr_tdata2 = dwarf_csr_1954,
+ dwarf_csr_tdata3 = dwarf_csr_1955,
+ dwarf_csr_mcontext = dwarf_csr_1960,
+ dwarf_csr_dcsr = dwarf_csr_1968,
+ dwarf_csr_dpc = dwarf_csr_1969,
+ dwarf_csr_dscratch0 = dwarf_csr_1970,
+ dwarf_csr_dscratch1 = dwarf_csr_1971,
+ dwarf_csr_mcycle = dwarf_csr_2816,
+ dwarf_csr_minstret = dwarf_csr_2818,
+ dwarf_csr_mhpmcounter3 = dwarf_csr_2819,
+ dwarf_csr_mhpmcounter4 = dwarf_csr_2820,
+ dwarf_csr_mhpmcounter5 = dwarf_csr_2821,
+ dwarf_csr_mhpmcounter6 = dwarf_csr_2822,
+ dwarf_csr_mhpmcounter7 = dwarf_csr_2823,
+ dwarf_csr_mhpmcounter8 = dwarf_csr_2824,
+ dwarf_csr_mhpmcounter9 = dwarf_csr_2825,
+ dwarf_csr_mhpmcounter10 = dwarf_csr_2826,
+ dwarf_csr_mhpmcounter11 = dwarf_csr_2827,
+ dwarf_csr_mhpmcounter12 = dwarf_csr_2828,
+ dwarf_csr_mhpmcounter13 = dwarf_csr_2829,
+ dwarf_csr_mhpmcounter14 = dwarf_csr_2830,
+ dwarf_csr_mhpmcounter15 = dwarf_csr_2831,
+ dwarf_csr_mhpmcounter16 = dwarf_csr_2832,
+ dwarf_csr_mhpmcounter17 = dwarf_csr_2833,
+ dwarf_csr_mhpmcounter18 = dwarf_csr_2834,
+ dwarf_csr_mhpmcounter19 = dwarf_csr_2835,
+ dwarf_csr_mhpmcounter20 = dwarf_csr_2836,
+ dwarf_csr_mhpmcounter21 = dwarf_csr_2837,
+ dwarf_csr_mhpmcounter22 = dwarf_csr_2838,
+ dwarf_csr_mhpmcounter23 = dwarf_csr_2839,
+ dwarf_csr_mhpmcounter24 = dwarf_csr_2840,
+ dwarf_csr_mhpmcounter25 = dwarf_csr_2841,
+ dwarf_csr_mhpmcounter26 = dwarf_csr_2842,
+ dwarf_csr_mhpmcounter27 = dwarf_csr_2843,
+ dwarf_csr_mhpmcounter28 = dwarf_csr_2844,
+ dwarf_csr_mhpmcounter29 = dwarf_csr_2845,
+ dwarf_csr_mhpmcounter30 = dwarf_csr_2846,
+ dwarf_csr_mhpmcounter31 = dwarf_csr_2847,
+ dwarf_csr_mcycleh = dwarf_csr_2944,
+ dwarf_csr_minstreth = dwarf_csr_2946,
+ dwarf_csr_mhpmcounter3h = dwarf_csr_2947,
+ dwarf_csr_mhpmcounter4h = dwarf_csr_2948,
+ dwarf_csr_mhpmcounter5h = dwarf_csr_2949,
+ dwarf_csr_mhpmcounter6h = dwarf_csr_2950,
+ dwarf_csr_mhpmcounter7h = dwarf_csr_2951,
+ dwarf_csr_mhpmcounter8h = dwarf_csr_2952,
+ dwarf_csr_mhpmcounter9h = dwarf_csr_2953,
+ dwarf_csr_mhpmcounter10h = dwarf_csr_2954,
+ dwarf_csr_mhpmcounter11h = dwarf_csr_2955,
+ dwarf_csr_mhpmcounter12h = dwarf_csr_2956,
+ dwarf_csr_mhpmcounter13h = dwarf_csr_2957,
+ dwarf_csr_mhpmcounter14h = dwarf_csr_2958,
+ dwarf_csr_mhpmcounter15h = dwarf_csr_2959,
+ dwarf_csr_mhpmcounter16h = dwarf_csr_2960,
+ dwarf_csr_mhpmcounter17h = dwarf_csr_2961,
+ dwarf_csr_mhpmcounter18h = dwarf_csr_2962,
+ dwarf_csr_mhpmcounter19h = dwarf_csr_2963,
+ dwarf_csr_mhpmcounter20h = dwarf_csr_2964,
+ dwarf_csr_mhpmcounter21h = dwarf_csr_2965,
+ dwarf_csr_mhpmcounter22h = dwarf_csr_2966,
+ dwarf_csr_mhpmcounter23h = dwarf_csr_2967,
+ dwarf_csr_mhpmcounter24h = dwarf_csr_2968,
+ dwarf_csr_mhpmcounter25h = dwarf_csr_2969,
+ dwarf_csr_mhpmcounter26h = dwarf_csr_2970,
+ dwarf_csr_mhpmcounter27h = dwarf_csr_2971,
+ dwarf_csr_mhpmcounter28h = dwarf_csr_2972,
+ dwarf_csr_mhpmcounter29h = dwarf_csr_2973,
+ dwarf_csr_mhpmcounter30h = dwarf_csr_2974,
+ dwarf_csr_mhpmcounter31h = dwarf_csr_2975,
+ dwarf_csr_cycle = dwarf_csr_3072,
+ dwarf_csr_time = dwarf_csr_3073,
+ dwarf_csr_instret = dwarf_csr_3074,
+ dwarf_csr_hpmcounter3 = dwarf_csr_3075,
+ dwarf_csr_hpmcounter4 = dwarf_csr_3076,
+ dwarf_csr_hpmcounter5 = dwarf_csr_3077,
+ dwarf_csr_hpmcounter6 = dwarf_csr_3078,
+ dwarf_csr_hpmcounter7 = dwarf_csr_3079,
+ dwarf_csr_hpmcounter8 = dwarf_csr_3080,
+ dwarf_csr_hpmcounter9 = dwarf_csr_3081,
+ dwarf_csr_hpmcounter10 = dwarf_csr_3082,
+ dwarf_csr_hpmcounter11 = dwarf_csr_3083,
+ dwarf_csr_hpmcounter12 = dwarf_csr_3084,
+ dwarf_csr_hpmcounter13 = dwarf_csr_3085,
+ dwarf_csr_hpmcounter14 = dwarf_csr_3086,
+ dwarf_csr_hpmcounter15 = dwarf_csr_3087,
+ dwarf_csr_hpmcounter16 = dwarf_csr_3088,
+ dwarf_csr_hpmcounter17 = dwarf_csr_3089,
+ dwarf_csr_hpmcounter18 = dwarf_csr_3090,
+ dwarf_csr_hpmcounter19 = dwarf_csr_3091,
+ dwarf_csr_hpmcounter20 = dwarf_csr_3092,
+ dwarf_csr_hpmcounter21 = dwarf_csr_3093,
+ dwarf_csr_hpmcounter22 = dwarf_csr_3094,
+ dwarf_csr_hpmcounter23 = dwarf_csr_3095,
+ dwarf_csr_hpmcounter24 = dwarf_csr_3096,
+ dwarf_csr_hpmcounter25 = dwarf_csr_3097,
+ dwarf_csr_hpmcounter26 = dwarf_csr_3098,
+ dwarf_csr_hpmcounter27 = dwarf_csr_3099,
+ dwarf_csr_hpmcounter28 = dwarf_csr_3100,
+ dwarf_csr_hpmcounter29 = dwarf_csr_3101,
+ dwarf_csr_hpmcounter30 = dwarf_csr_3102,
+ dwarf_csr_hpmcounter31 = dwarf_csr_3103,
+ dwarf_csr_vl = dwarf_csr_3104,
+ dwarf_csr_vtype = dwarf_csr_3105,
+ dwarf_csr_vlenb = dwarf_csr_3106,
+ dwarf_csr_cycleh = dwarf_csr_3200,
+ dwarf_csr_timeh = dwarf_csr_3201,
+ dwarf_csr_instreth = dwarf_csr_3202,
+ dwarf_csr_hpmcounter3h = dwarf_csr_3203,
+ dwarf_csr_hpmcounter4h = dwarf_csr_3204,
+ dwarf_csr_hpmcounter5h = dwarf_csr_3205,
+ dwarf_csr_hpmcounter6h = dwarf_csr_3206,
+ dwarf_csr_hpmcounter7h = dwarf_csr_3207,
+ dwarf_csr_hpmcounter8h = dwarf_csr_3208,
+ dwarf_csr_hpmcounter9h = dwarf_csr_3209,
+ dwarf_csr_hpmcounter10h = dwarf_csr_3210,
+ dwarf_csr_hpmcounter11h = dwarf_csr_3211,
+ dwarf_csr_hpmcounter12h = dwarf_csr_3212,
+ dwarf_csr_hpmcounter13h = dwarf_csr_3213,
+ dwarf_csr_hpmcounter14h = dwarf_csr_3214,
+ dwarf_csr_hpmcounter15h = dwarf_csr_3215,
+ dwarf_csr_hpmcounter16h = dwarf_csr_3216,
+ dwarf_csr_hpmcounter17h = dwarf_csr_3217,
+ dwarf_csr_hpmcounter18h = dwarf_csr_3218,
+ dwarf_csr_hpmcounter19h = dwarf_csr_3219,
+ dwarf_csr_hpmcounter20h = dwarf_csr_3220,
+ dwarf_csr_hpmcounter21h = dwarf_csr_3221,
+ dwarf_csr_hpmcounter22h = dwarf_csr_3222,
+ dwarf_csr_hpmcounter23h = dwarf_csr_3223,
+ dwarf_csr_hpmcounter24h = dwarf_csr_3224,
+ dwarf_csr_hpmcounter25h = dwarf_csr_3225,
+ dwarf_csr_hpmcounter26h = dwarf_csr_3226,
+ dwarf_csr_hpmcounter27h = dwarf_csr_3227,
+ dwarf_csr_hpmcounter28h = dwarf_csr_3228,
+ dwarf_csr_hpmcounter29h = dwarf_csr_3229,
+ dwarf_csr_hpmcounter30h = dwarf_csr_3230,
+ dwarf_csr_hpmcounter31h = dwarf_csr_3231,
+ dwarf_csr_scountovf = dwarf_csr_3488,
+ dwarf_csr_hgeip = dwarf_csr_3602,
+ dwarf_csr_mvendorid = dwarf_csr_3857,
+ dwarf_csr_marchid = dwarf_csr_3858,
+ dwarf_csr_mimpid = dwarf_csr_3859,
+ dwarf_csr_mhartid = dwarf_csr_3860,
+ dwarf_csr_mconfigptr = dwarf_csr_3861,
+
// mock pc regnum
dwarf_gpr_pc = 11451,
};
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