[Lldb-commits] [lldb] [lldb] Support riscv32 ELF corefiles (PR #115408)

[via lldb-commits]

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@@ -0,0 +1,185 @@
+//===-- RegisterInfos_riscv32.h ---------------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifdef DECLARE_REGISTER_INFOS_RISCV32_STRUCT
+
+#include "Utility/RISCV_DWARF_Registers.h"
+#include "lldb-riscv-register-enums.h"
+#include "lldb/lldb-defines.h"
+#include "lldb/lldb-enumerations.h"
+#include "lldb/lldb-private.h"
+
+#include <stddef.h>
+
+#ifndef GPR_OFFSET
+#error GPR_OFFSET must be defined before including this header file
+#endif
+
+#ifndef FPR_OFFSET
+#error FPR_OFFSET must be defined before including this header file
+#endif
+
+using namespace riscv_dwarf;
+
+// clang-format off
+
+// I suppose EHFrame and DWARF are the same.
+#define KIND_HELPER(reg, generic_kind)                                         \
+  {                                                                            \
+    riscv_dwarf::dwarf_##reg, riscv_dwarf::dwarf_##reg, generic_kind,          \
+    LLDB_INVALID_REGNUM, reg##_riscv                                           \
+  }
+
+// Generates register kinds array for vector registers
+#define GPR32_KIND(reg, generic_kind) KIND_HELPER(reg, generic_kind)
+
+// FPR register kinds array for vector registers
+#define FPR32_KIND(reg, generic_kind) KIND_HELPER(reg, generic_kind)
+
+// VPR register kinds array for vector registers
+#define VPR_KIND(reg, generic_kind) KIND_HELPER(reg, generic_kind)
+
+// Defines a 32-bit general purpose register
+#define DEFINE_GPR32(reg, generic_kind) DEFINE_GPR32_ALT(reg, reg, generic_kind)
+
+// Defines a 32-bit general purpose register
+#define DEFINE_GPR32_ALT(reg, alt, generic_kind)                               \
+  {                                                                            \
+    #reg, #alt, 4, GPR_OFFSET(gpr_##reg##_riscv - gpr_first_riscv),            \
+    lldb::eEncodingUint, lldb::eFormatHex,                                     \
+    GPR32_KIND(gpr_##reg, generic_kind), nullptr, nullptr, nullptr,            \
+  }
+
+#define DEFINE_FPR32(reg, generic_kind) DEFINE_FPR32_ALT(reg, reg, generic_kind)
+
+#define DEFINE_FPR32_ALT(reg, alt, generic_kind) DEFINE_FPR_ALT(reg, alt, 4, generic_kind)
+
+#define DEFINE_FPR_ALT(reg, alt, size, generic_kind)                           \
+  {                                                                            \
+    #reg, #alt, size, FPR_OFFSET(fpr_##reg##_riscv - fpr_first_riscv),         \
+    lldb::eEncodingUint, lldb::eFormatHex,                                     \
+    FPR32_KIND(fpr_##reg, generic_kind), nullptr, nullptr, nullptr,           \
+  }
+
+#define DEFINE_VPR(reg, generic_kind) DEFINE_VPR_ALT(reg, reg, generic_kind)
+
+// Defines a scalable vector register, with default size 128 bits
+// The byte offset 0 is a placeholder, which should be corrected at runtime.
+#define DEFINE_VPR_ALT(reg, alt, generic_kind)                                 \
+  {                                                                            \
+    #reg, #alt, 16, 0, lldb::eEncodingVector, lldb::eFormatVectorOfUInt8,      \
+    VPR_KIND(vpr_##reg, generic_kind), nullptr, nullptr, nullptr               \
+  }
+
+// clang-format on
+
+static lldb_private::RegisterInfo g_register_infos_riscv32_le[] = {
+    // DEFINE_GPR32(name, GENERIC KIND)
+    DEFINE_GPR32(pc, LLDB_REGNUM_GENERIC_PC),
+    DEFINE_GPR32_ALT(ra, x1, LLDB_REGNUM_GENERIC_RA),
+    DEFINE_GPR32_ALT(sp, x2, LLDB_REGNUM_GENERIC_SP),
+    DEFINE_GPR32_ALT(gp, x3, LLDB_INVALID_REGNUM),
+    DEFINE_GPR32_ALT(tp, x4, LLDB_INVALID_REGNUM),
+    DEFINE_GPR32_ALT(t0, x5, LLDB_INVALID_REGNUM),
+    DEFINE_GPR32_ALT(t1, x6, LLDB_INVALID_REGNUM),
+    DEFINE_GPR32_ALT(t2, x7, LLDB_INVALID_REGNUM),
+    DEFINE_GPR32_ALT(fp, x8, LLDB_REGNUM_GENERIC_FP),
+    DEFINE_GPR32_ALT(s1, x9, LLDB_INVALID_REGNUM),
+    DEFINE_GPR32_ALT(a0, x10, LLDB_REGNUM_GENERIC_ARG1),
+    DEFINE_GPR32_ALT(a1, x11, LLDB_REGNUM_GENERIC_ARG2),
+    DEFINE_GPR32_ALT(a2, x12, LLDB_REGNUM_GENERIC_ARG3),
+    DEFINE_GPR32_ALT(a3, x13, LLDB_REGNUM_GENERIC_ARG4),
+    DEFINE_GPR32_ALT(a4, x14, LLDB_REGNUM_GENERIC_ARG5),
+    DEFINE_GPR32_ALT(a5, x15, LLDB_REGNUM_GENERIC_ARG6),
+    DEFINE_GPR32_ALT(a6, x16, LLDB_REGNUM_GENERIC_ARG7),
+    DEFINE_GPR32_ALT(a7, x17, LLDB_REGNUM_GENERIC_ARG8),
+    DEFINE_GPR32_ALT(s2, x18, LLDB_INVALID_REGNUM),
+    DEFINE_GPR32_ALT(s3, x19, LLDB_INVALID_REGNUM),
+    DEFINE_GPR32_ALT(s4, x20, LLDB_INVALID_REGNUM),
+    DEFINE_GPR32_ALT(s5, x21, LLDB_INVALID_REGNUM),
+    DEFINE_GPR32_ALT(s6, x22, LLDB_INVALID_REGNUM),
+    DEFINE_GPR32_ALT(s7, x23, LLDB_INVALID_REGNUM),
+    DEFINE_GPR32_ALT(s8, x24, LLDB_INVALID_REGNUM),
+    DEFINE_GPR32_ALT(s9, x25, LLDB_INVALID_REGNUM),
+    DEFINE_GPR32_ALT(s10, x26, LLDB_INVALID_REGNUM),
+    DEFINE_GPR32_ALT(s11, x27, LLDB_INVALID_REGNUM),
+    DEFINE_GPR32_ALT(t3, x28, LLDB_INVALID_REGNUM),
+    DEFINE_GPR32_ALT(t4, x29, LLDB_INVALID_REGNUM),
+    DEFINE_GPR32_ALT(t5, x30, LLDB_INVALID_REGNUM),
+    DEFINE_GPR32_ALT(t6, x31, LLDB_INVALID_REGNUM),
+    DEFINE_GPR32_ALT(zero, x0, LLDB_INVALID_REGNUM),
----------------
tedwoodward wrote:

@jasonmolenda I had the same thought when we were internally implementing 32 bit core dumps, and realized that the zero register can be another "register" that the dumper uses to communicate interesting data. I know our internal team that wanted this plans to use it for something (I don't know what).

https://github.com/llvm/llvm-project/pull/115408