[Lldb-commits] [lldb] [lldb] Add more ARM checks in TestLldbGdbServer.py (PR #130277)

[David Spickett via lldb-commits]

https://github.com/DavidSpickett created https://github.com/llvm/llvm-project/pull/130277

When https://github.com/llvm/llvm-project/pull/130034 enabled RISC-V here I noticed that these should run for ARM as well.

ARM only has 4 argument registers, which matches Arm's ABI for it: https://github.com/ARM-software/abi-aa/blob/main/aapcs32/aapcs32.rst#core-registers

The ABI defines a link register LR, and I assume that's what becomes 'ra' in LLDB.

Tested on ARM and AArch64 Linux.

>From 091dd938faad4c28fe746af0093c2249078adc5a Mon Sep 17 00:00:00 2001
From: David Spickett <david.spickett at linaro.org>
Date: Fri, 7 Mar 2025 12:08:29 +0000
Subject: [PATCH] [lldb] Add more ARM checks in TestLldbGdbServer.py

When https://github.com/llvm/llvm-project/pull/130034 enabled
RISC-V here I noticed that these should run for ARM as well.

ARM only has 4 argument registers, which matches Arm's ABI for it:
https://github.com/ARM-software/abi-aa/blob/main/aapcs32/aapcs32.rst#core-registers

The ABI defines a link register LR, and I assume that's what becomes
'ra' in LLDB.

Tested on ARM and AArch64 Linux.
---
 lldb/packages/Python/lldbsuite/test/lldbtest.py      | 7 +++++++
 lldb/test/API/tools/lldb-server/TestLldbGdbServer.py | 8 ++++----
 2 files changed, 11 insertions(+), 4 deletions(-)

diff --git a/lldb/packages/Python/lldbsuite/test/lldbtest.py b/lldb/packages/Python/lldbsuite/test/lldbtest.py
index 7d0e6e9a970eb..590024ef77119 100644
--- a/lldb/packages/Python/lldbsuite/test/lldbtest.py
+++ b/lldb/packages/Python/lldbsuite/test/lldbtest.py
@@ -1344,6 +1344,13 @@ def isAArch64(self):
         arch = self.getArchitecture().lower()
         return arch in ["aarch64", "arm64", "arm64e"]
 
+    def isARM(self):
+        """Returns true if the architecture is ARM, meaning 32-bit ARM. Which could
+        be M profile, A profile Armv7-a, or the AArch32 mode of Armv8-a."""
+        return not self.isAArch64() and (
+            self.getArchitecture().lower().startswith("arm")
+        )
+
     def isAArch64SVE(self):
         return self.isAArch64() and "sve" in self.getCPUInfo()
 
diff --git a/lldb/test/API/tools/lldb-server/TestLldbGdbServer.py b/lldb/test/API/tools/lldb-server/TestLldbGdbServer.py
index ce75e3e89e0a6..12c97bc62dcef 100644
--- a/lldb/test/API/tools/lldb-server/TestLldbGdbServer.py
+++ b/lldb/test/API/tools/lldb-server/TestLldbGdbServer.py
@@ -199,12 +199,12 @@ def test_qRegisterInfo_contains_required_generics_debugserver(self):
         if not self.isRISCV():
             self.assertIn("flags", generic_regs)
 
-        if self.isRISCV():
-            # Special RISC-V register for a return address
+        if self.isRISCV() or self.isAArch64() or self.isARM():
+            # Specific register for a return address
             self.assertIn("ra", generic_regs)
 
-            # RISC-V's function arguments registers
-            for i in range(1, 9):
+            # Function arguments registers
+            for i in range(1, 5 if self.isARM() else 9):
                 self.assertIn(f"arg{i}", generic_regs)
 
     def test_qRegisterInfo_contains_at_least_one_register_set(self):