[Lldb-commits] [lldb] [lldb] Adapt llgs tests for RISC-V (PR #130034)

[David Spickett via lldb-commits]

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@@ -195,8 +195,17 @@ def test_qRegisterInfo_contains_required_generics_debugserver(self):
         # Ensure we have a stack pointer register.
         self.assertIn("sp", generic_regs)
 
-        # Ensure we have a flags register.
-        self.assertIn("flags", generic_regs)
+        # Ensure we have a flags register. RISC-V doesn't have a flags register
+        if not self.isRISCV():
+            self.assertIn("flags", generic_regs)
+
+        if self.isRISCV():
+            # Special RISC-V register for a return address
+            self.assertIn("ra", generic_regs)
+
+            # RISC-V's function arguments registers
+            for i in range(1, 9):
+                self.assertIn(f"arg{i}", generic_regs)
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DavidSpickett wrote:

Some of these registers do exist for AArch64 (probably Arm too) but we just never checked for them. I will look into that myself.

https://github.com/llvm/llvm-project/pull/130034