[Lldb-commits] [lldb] [llvm] [lldb][RISC-V] Extended if conditions to support alias names for registers (PR #124475)
via lldb-commits
lldb-commits at lists.llvm.org
Thu Feb 20 06:50:55 PST 2025
https://github.com/kper updated https://github.com/llvm/llvm-project/pull/124475
>From 4feaf723ff8f879bd82bb82108d9e6bac4b90026 Mon Sep 17 00:00:00 2001
From: Kevin Per <kevin.per at protonmail.com>
Date: Sun, 26 Jan 2025 17:34:17 +0000
Subject: [PATCH] [lldb] Extended if conditions to support alias names for
registers
---
.../Plugins/ABI/RISCV/ABISysV_riscv.cpp | 54 ++++++
.../TestGDBServerTargetXML.py | 148 ++++++++++++++++
.../basic_eh_frame-riscv64.yaml | 20 +++
.../postmortem/elf-core/TestLinuxCore.py | 158 ++++++++++--------
.../Shell/Register/Inputs/riscv64-gp-read.cpp | 36 ++++
lldb/test/Shell/Register/riscv64-gp-read.test | 141 ++++++++++++++++
llvm/utils/lit/lit/llvm/config.py | 8 +-
7 files changed, 491 insertions(+), 74 deletions(-)
create mode 100644 lldb/test/API/functionalities/gdb_remote_client/basic_eh_frame-riscv64.yaml
create mode 100644 lldb/test/Shell/Register/Inputs/riscv64-gp-read.cpp
create mode 100644 lldb/test/Shell/Register/riscv64-gp-read.test
diff --git a/lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.cpp b/lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.cpp
index 8412991933d27..c463bd006b3db 100644
--- a/lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.cpp
+++ b/lldb/source/Plugins/ABI/RISCV/ABISysV_riscv.cpp
@@ -850,8 +850,62 @@ void ABISysV_riscv::AugmentRegisterInfo(
it.value().alt_name.SetCString("x3");
else if (it.value().name == "fp")
it.value().alt_name.SetCString("s0");
+ else if (it.value().name == "tp")
+ it.value().alt_name.SetCString("x4");
else if (it.value().name == "s0")
it.value().alt_name.SetCString("x8");
+ else if (it.value().name == "s1")
+ it.value().alt_name.SetCString("x9");
+ else if (it.value().name == "t0")
+ it.value().alt_name.SetCString("x5");
+ else if (it.value().name == "t1")
+ it.value().alt_name.SetCString("x6");
+ else if (it.value().name == "t2")
+ it.value().alt_name.SetCString("x7");
+ else if (it.value().name == "a0")
+ it.value().alt_name.SetCString("x10");
+ else if (it.value().name == "a1")
+ it.value().alt_name.SetCString("x11");
+ else if (it.value().name == "a2")
+ it.value().alt_name.SetCString("x12");
+ else if (it.value().name == "a3")
+ it.value().alt_name.SetCString("x13");
+ else if (it.value().name == "a4")
+ it.value().alt_name.SetCString("x14");
+ else if (it.value().name == "a5")
+ it.value().alt_name.SetCString("x15");
+ else if (it.value().name == "a6")
+ it.value().alt_name.SetCString("x16");
+ else if (it.value().name == "a7")
+ it.value().alt_name.SetCString("x17");
+ else if (it.value().name == "s2")
+ it.value().alt_name.SetCString("x18");
+ else if (it.value().name == "s3")
+ it.value().alt_name.SetCString("x19");
+ else if (it.value().name == "s4")
+ it.value().alt_name.SetCString("x20");
+ else if (it.value().name == "s5")
+ it.value().alt_name.SetCString("x21");
+ else if (it.value().name == "s6")
+ it.value().alt_name.SetCString("x22");
+ else if (it.value().name == "s7")
+ it.value().alt_name.SetCString("x23");
+ else if (it.value().name == "s8")
+ it.value().alt_name.SetCString("x24");
+ else if (it.value().name == "s9")
+ it.value().alt_name.SetCString("x25");
+ else if (it.value().name == "s10")
+ it.value().alt_name.SetCString("x26");
+ else if (it.value().name == "s11")
+ it.value().alt_name.SetCString("x27");
+ else if (it.value().name == "t3")
+ it.value().alt_name.SetCString("x28");
+ else if (it.value().name == "t4")
+ it.value().alt_name.SetCString("x29");
+ else if (it.value().name == "t5")
+ it.value().alt_name.SetCString("x30");
+ else if (it.value().name == "t6")
+ it.value().alt_name.SetCString("x31");
// Set generic regnum so lldb knows what the PC, etc is
it.value().regnum_generic = GetGenericNum(it.value().name.GetStringRef());
diff --git a/lldb/test/API/functionalities/gdb_remote_client/TestGDBServerTargetXML.py b/lldb/test/API/functionalities/gdb_remote_client/TestGDBServerTargetXML.py
index 22f5553e40802..9a70f67b264ce 100644
--- a/lldb/test/API/functionalities/gdb_remote_client/TestGDBServerTargetXML.py
+++ b/lldb/test/API/functionalities/gdb_remote_client/TestGDBServerTargetXML.py
@@ -652,6 +652,154 @@ def haltReason(self):
)
self.match("register read s31", ["s31 = 128"])
+ @skipIfXmlSupportMissing
+ @skipIfRemote
+ @skipIfLLVMTargetMissing("RISCV")
+ def test_riscv64_regs(self):
+ """Test grabbing various riscv64 registers from gdbserver."""
+
+ class MyResponder(MockGDBServerResponder):
+ reg_data = (
+ "0102030405060708" # zero
+ "0102030405060708" # ra
+ "0102030405060708" # sp
+ "0102030405060708" # gp
+ "0102030405060708" # tp
+ "0102030405060708" # t0
+ "0102030405060708" # t1
+ "0102030405060708" # t2
+ "0102030405060708" # fp
+ "0102030405060708" # s1
+ "0102030405060708" # a0
+ "0102030405060708" # a1
+ "0102030405060708" # a2
+ "0102030405060708" # a3
+ "0102030405060708" # a4
+ "0102030405060708" # a5
+ "0102030405060708" # a6
+ "0102030405060708" # a7
+ "0102030405060708" # s2
+ "0102030405060708" # s3
+ "0102030405060708" # s4
+ "0102030405060708" # s5
+ "0102030405060708" # s6
+ "0102030405060708" # s7
+ "0102030405060708" # s8
+ "0102030405060708" # s9
+ "0102030405060708" # s10
+ "0102030405060708" # s11
+ "0102030405060708" # t3
+ "0102030405060708" # t4
+ "0102030405060708" # t5
+ "0102030405060708" # t6
+ )
+
+ def qXferRead(self, obj, annex, offset, length):
+ if annex == "target.xml":
+ # Note that this XML does not include any aliases, LLDB must generate them itself.
+ return (
+ """<?xml version="1.0"?>
+ <!DOCTYPE feature SYSTEM "gdb-target.dtd">
+ <target>
+ <architecture>riscv</architecture>
+ <feature name="org.gnu.gdb.riscv.cpu">
+ <reg name="zero" bitsize="64" type="int"/>
+ <reg name="ra" bitsize="64" type="code_ptr"/>
+ <reg name="sp" bitsize="64" type="data_ptr"/>
+ <reg name="gp" bitsize="64" type="data_ptr"/>
+ <reg name="tp" bitsize="64" type="data_ptr"/>
+ <reg name="t0" bitsize="64" type="int"/>
+ <reg name="t1" bitsize="64" type="int"/>
+ <reg name="t2" bitsize="64" type="int"/>
+ <reg name="fp" bitsize="64" type="data_ptr"/>
+ <reg name="s1" bitsize="64" type="int"/>
+ <reg name="a0" bitsize="64" type="int"/>
+ <reg name="a1" bitsize="64" type="int"/>
+ <reg name="a2" bitsize="64" type="int"/>
+ <reg name="a3" bitsize="64" type="int"/>
+ <reg name="a4" bitsize="64" type="int"/>
+ <reg name="a5" bitsize="64" type="int"/>
+ <reg name="a6" bitsize="64" type="int"/>
+ <reg name="a7" bitsize="64" type="int"/>
+ <reg name="s2" bitsize="64" type="int"/>
+ <reg name="s3" bitsize="64" type="int"/>
+ <reg name="s4" bitsize="64" type="int"/>
+ <reg name="s5" bitsize="64" type="int"/>
+ <reg name="s6" bitsize="64" type="int"/>
+ <reg name="s7" bitsize="64" type="int"/>
+ <reg name="s8" bitsize="64" type="int"/>
+ <reg name="s9" bitsize="64" type="int"/>
+ <reg name="s10" bitsize="64" type="int"/>
+ <reg name="s11" bitsize="64" type="int"/>
+ <reg name="t3" bitsize="64" type="int"/>
+ <reg name="t4" bitsize="64" type="int"/>
+ <reg name="t5" bitsize="64" type="int"/>
+ <reg name="t6" bitsize="64" type="int"/>
+ <reg name="pc" bitsize="64" type="code_ptr"/>
+ </feature>
+ </target>""",
+ False,
+ )
+ else:
+ return None, False
+
+ def readRegister(self, regnum):
+ return ""
+
+ def readRegisters(self):
+ return self.reg_data
+
+ def writeRegisters(self, reg_hex):
+ self.reg_data = reg_hex
+ return "OK"
+
+ def haltReason(self):
+ return "T02thread:1ff0d;threads:1ff0d;thread-pcs:000000010001bc00;07:0102030405060708;10:1112131415161718;"
+
+ self.server.responder = MyResponder()
+
+ target = self.createTarget("basic_eh_frame-riscv64.yaml")
+ process = self.connect(target)
+ lldbutil.expect_state_changes(
+ self, self.dbg.GetListener(), process, [lldb.eStateStopped]
+ )
+
+ # test generic aliases
+ self.match("register read x0", ["zero = 0x0807060504030201"])
+ self.match("register read x1", ["ra = 0x0807060504030201"])
+ self.match("register read x2", ["sp = 0x0807060504030201"])
+ self.match("register read x3", ["gp = 0x0807060504030201"])
+ self.match("register read x4", ["tp = 0x0807060504030201"])
+ self.match("register read x5", ["t0 = 0x0807060504030201"])
+ self.match("register read x6", ["t1 = 0x0807060504030201"])
+ self.match("register read x7", ["t2 = 0x0807060504030201"])
+ # Register x8 is probably not working because it has two aliases fp, s0
+ # See issue #127900
+ # self.match("register read x8", ["fp = 0x0807060504030201"])
+ self.match("register read x9", ["s1 = 0x0807060504030201"])
+ self.match("register read x10", ["a0 = 0x0807060504030201"])
+ self.match("register read x11", ["a1 = 0x0807060504030201"])
+ self.match("register read x12", ["a2 = 0x0807060504030201"])
+ self.match("register read x13", ["a3 = 0x0807060504030201"])
+ self.match("register read x14", ["a4 = 0x0807060504030201"])
+ self.match("register read x15", ["a5 = 0x0807060504030201"])
+ self.match("register read x16", ["a6 = 0x0807060504030201"])
+ self.match("register read x17", ["a7 = 0x0807060504030201"])
+ self.match("register read x18", ["s2 = 0x0807060504030201"])
+ self.match("register read x19", ["s3 = 0x0807060504030201"])
+ self.match("register read x20", ["s4 = 0x0807060504030201"])
+ self.match("register read x21", ["s5 = 0x0807060504030201"])
+ self.match("register read x22", ["s6 = 0x0807060504030201"])
+ self.match("register read x23", ["s7 = 0x0807060504030201"])
+ self.match("register read x24", ["s8 = 0x0807060504030201"])
+ self.match("register read x25", ["s9 = 0x0807060504030201"])
+ self.match("register read x26", ["s10 = 0x0807060504030201"])
+ self.match("register read x27", ["s11 = 0x0807060504030201"])
+ self.match("register read x28", ["t3 = 0x0807060504030201"])
+ self.match("register read x29", ["t4 = 0x0807060504030201"])
+ self.match("register read x30", ["t5 = 0x0807060504030201"])
+ self.match("register read x31", ["t6 = 0x0807060504030201"])
+
@skipIfXmlSupportMissing
@skipIfRemote
@skipIfLLVMTargetMissing("X86")
diff --git a/lldb/test/API/functionalities/gdb_remote_client/basic_eh_frame-riscv64.yaml b/lldb/test/API/functionalities/gdb_remote_client/basic_eh_frame-riscv64.yaml
new file mode 100644
index 0000000000000..50cdd23f42667
--- /dev/null
+++ b/lldb/test/API/functionalities/gdb_remote_client/basic_eh_frame-riscv64.yaml
@@ -0,0 +1,20 @@
+--- !ELF
+FileHeader:
+ Class: ELFCLASS64
+ Data: ELFDATA2LSB
+ Type: ET_EXEC
+ Machine: EM_RISCV
+Sections:
+ - Name: .text
+ Type: SHT_PROGBITS
+ Flags: [ SHF_ALLOC, SHF_EXECINSTR ]
+ Address: 0x0000000000000570
+ AddressAlign: 0x0000000000000004
+ Content: DEADBEEF
+ - Name: .eh_frame
+ Type: SHT_PROGBITS
+ Flags: [ SHF_ALLOC ]
+ Address: 0x0000000000000688
+ AddressAlign: 0x0000000000000008
+ Content: 000006881000000000000000037a5200017c0101000006981b0d02001000000018000000ccfeffff000006a82200000000070100200000002c000000000006b89cffffff1000000000420e1042880242000006c80c080046c80c0210420e000000000000
+...
diff --git a/lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py b/lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py
index 376d6492d83b6..60caedf4737da 100644
--- a/lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py
+++ b/lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py
@@ -703,42 +703,43 @@ def test_riscv64_regs_gpr_fpr(self):
self.assertTrue(target, VALID_TARGET)
process = target.LoadCore("linux-riscv64.gpr_fpr.core")
- values = {}
- values["pc"] = "0x000000000001016e"
- values["ra"] = "0x00000000000101a4"
- values["sp"] = "0x0000003fffc1d2d0"
- values["gp"] = "0x0000002ae6eccf50"
- values["tp"] = "0x0000003ff3cb5400"
- values["t0"] = "0x7f7f7f7fffffffff"
- values["t1"] = "0x0000002ae6eb9b1c"
- values["t2"] = "0xffffffffffffffff"
- values["fp"] = "0x0000003fffc1d300"
- values["s1"] = "0x0000002ae6eced98"
- values["a0"] = "0x0"
- values["a1"] = "0x0000000000010144"
- values["a2"] = "0x0000002ae6ecedb0"
- values["a3"] = "0xafdbdbff81cf7f81"
- values["a4"] = "0x00000000000101e4"
- values["a5"] = "0x0"
- values["a6"] = "0x2f5b5a40014e0001"
- values["a7"] = "0x00000000000000dd"
- values["s2"] = "0x0000002ae6ec8860"
- values["s3"] = "0x0000002ae6ecedb0"
- values["s4"] = "0x0000003fff886c18"
- values["s5"] = "0x0000002ae6eceb78"
- values["s6"] = "0x0000002ae6ec8860"
- values["s7"] = "0x0000002ae6ec8860"
- values["s8"] = "0x0"
- values["s9"] = "0x000000000000000f"
- values["s10"] = "0x0000002ae6ecc8d0"
- values["s11"] = "0x0000000000000008"
- values["t3"] = "0x0000003ff3be3728"
- values["t4"] = "0x0"
- values["t5"] = "0x0000000000000002"
- values["t6"] = "0x0000002ae6ed08b9"
- values["zero"] = "0x0"
- values["fa5"] = "0xffffffff423c0000"
- values["fcsr"] = "0x00000000"
+ values = {
+ "pc": ("0x000000000001016e", None),
+ "zero": ("0x0", "x0"),
+ "ra": ("0x00000000000101a4", "x1"),
+ "sp": ("0x0000003fffc1d2d0", "x2"),
+ "gp": ("0x0000002ae6eccf50", "x3"),
+ "tp": ("0x0000003ff3cb5400", "x4"),
+ "t0": ("0x7f7f7f7fffffffff", "x5"),
+ "t1": ("0x0000002ae6eb9b1c", "x6"),
+ "t2": ("0xffffffffffffffff", "x7"),
+ "fp": ("0x0000003fffc1d300", "x8"),
+ "s1": ("0x0000002ae6eced98", "x9"),
+ "a0": ("0x0000000000000000", "x10"),
+ "a1": ("0x0000000000010144", "x11"),
+ "a2": ("0x0000002ae6ecedb0", "x12"),
+ "a3": ("0xafdbdbff81cf7f81", "x13"),
+ "a4": ("0x00000000000101e4", "x14"),
+ "a5": ("0x0000000000000000", "x15"),
+ "a6": ("0x2f5b5a40014e0001", "x16"),
+ "a7": ("0x00000000000000dd", "x17"),
+ "s2": ("0x0000002ae6ec8860", "x18"),
+ "s3": ("0x0000002ae6ecedb0", "x19"),
+ "s4": ("0x0000003fff886c18", "x20"),
+ "s5": ("0x0000002ae6eceb78", "x21"),
+ "s6": ("0x0000002ae6ec8860", "x22"),
+ "s7": ("0x0000002ae6ec8860", "x23"),
+ "s8": ("0x0000000000000000", "x24"),
+ "s9": ("0x000000000000000f", "x25"),
+ "s10": ("0x0000002ae6ecc8d0", "x26"),
+ "s11": ("0x0000000000000008", "x27"),
+ "t3": ("0x0000003ff3be3728", "x28"),
+ "t4": ("0x0000000000000000", "x29"),
+ "t5": ("0x0000000000000002", "x30"),
+ "t6": ("0x0000002ae6ed08b9", "x31"),
+ "fa5": ("0xffffffff423c0000", None),
+ "fcsr": ("0x00000000", None),
+ }
fpr_names = {
"ft0",
@@ -776,11 +777,17 @@ def test_riscv64_regs_gpr_fpr(self):
}
fpr_value = "0x0000000000000000"
- for regname, value in values.items():
+ for regname in values:
+ value, alias = values[regname]
self.expect(
"register read {}".format(regname),
substrs=["{} = {}".format(regname, value)],
)
+ if alias:
+ self.expect(
+ "register read {}".format(alias),
+ substrs=["{} = {}".format(regname, value)],
+ )
for regname in fpr_names:
self.expect(
@@ -797,46 +804,53 @@ def test_riscv64_regs_gpr_only(self):
self.assertTrue(target, VALID_TARGET)
process = target.LoadCore("linux-riscv64.gpr_only.core")
- values = {}
- values["pc"] = "0x0000000000010164"
- values["ra"] = "0x0000000000010194"
- values["sp"] = "0x00fffffff4d5fcc0"
- values["gp"] = "0x0000000000157678"
- values["tp"] = "0x00ffffff99c43400"
- values["t0"] = "0x00ffffff99c6b260"
- values["t1"] = "0x00ffffff99b7bd54"
- values["t2"] = "0x0000000003f0b27f"
- values["fp"] = "0x00fffffff4d5fcf0"
- values["s1"] = "0x0000000000000003"
- values["a0"] = "0x0"
- values["a1"] = "0x0000000000010144"
- values["a2"] = "0x0000000000176460"
- values["a3"] = "0x000000000015ee38"
- values["a4"] = "0x00000000423c0000"
- values["a5"] = "0x0"
- values["a6"] = "0x0"
- values["a7"] = "0x00000000000000dd"
- values["s2"] = "0x0"
- values["s3"] = "0x000000000014ddf8"
- values["s4"] = "0x000000000003651c"
- values["s5"] = "0x00fffffffccd8d28"
- values["s6"] = "0x000000000014ddf8"
- values["s7"] = "0x00ffffff99c69d48"
- values["s8"] = "0x00ffffff99c6a008"
- values["s9"] = "0x0"
- values["s10"] = "0x0"
- values["s11"] = "0x0"
- values["t3"] = "0x00ffffff99c42000"
- values["t4"] = "0x00ffffff99af8e20"
- values["t5"] = "0x0000000000000005"
- values["t6"] = "0x44760bdd8d5f6381"
- values["zero"] = "0x0"
+ values = {
+ "pc": ("0x0000000000010164", None),
+ "zero": ("0x0", "x0"),
+ "ra": ("0x0000000000010194", "x1"),
+ "sp": ("0x00fffffff4d5fcc0", "x2"),
+ "gp": ("0x0000000000157678", "x3"),
+ "tp": ("0x00ffffff99c43400", "x4"),
+ "t0": ("0x00ffffff99c6b260", "x5"),
+ "t1": ("0x00ffffff99b7bd54", "x6"),
+ "t2": ("0x0000000003f0b27f", "x7"),
+ "fp": ("0x00fffffff4d5fcf0", "x8"),
+ "s1": ("0x0000000000000003", "x9"),
+ "a0": ("0x0", "x10"),
+ "a1": ("0x0000000000010144", "x11"),
+ "a2": ("0x0000000000176460", "x12"),
+ "a3": ("0x000000000015ee38", "x13"),
+ "a4": ("0x00000000423c0000", "x14"),
+ "a5": ("0x0", "x15"),
+ "a6": ("0x0", "x16"),
+ "a7": ("0x00000000000000dd", "x17"),
+ "s2": ("0x0", "x18"),
+ "s3": ("0x000000000014ddf8", "x19"),
+ "s4": ("0x000000000003651c", "x20"),
+ "s5": ("0x00fffffffccd8d28", "x21"),
+ "s6": ("0x000000000014ddf8", "x22"),
+ "s7": ("0x00ffffff99c69d48", "x23"),
+ "s8": ("0x00ffffff99c6a008", "x24"),
+ "s9": ("0x0", "x25"),
+ "s10": ("0x0", "x26"),
+ "s11": ("0x0", "x27"),
+ "t3": ("0x00ffffff99c42000", "x28"),
+ "t4": ("0x00ffffff99af8e20", "x29"),
+ "t5": ("0x0000000000000005", "x30"),
+ "t6": ("0x44760bdd8d5f6381", "x31"),
+ }
- for regname, value in values.items():
+ for regname in values:
+ value, alias = values[regname]
self.expect(
"register read {}".format(regname),
substrs=["{} = {}".format(regname, value)],
)
+ if alias:
+ self.expect(
+ "register read {}".format(alias),
+ substrs=["{} = {}".format(regname, value)],
+ )
# Check that LLDB does not try to read other registers from core file
self.expect(
diff --git a/lldb/test/Shell/Register/Inputs/riscv64-gp-read.cpp b/lldb/test/Shell/Register/Inputs/riscv64-gp-read.cpp
new file mode 100644
index 0000000000000..d24fcac6d8b24
--- /dev/null
+++ b/lldb/test/Shell/Register/Inputs/riscv64-gp-read.cpp
@@ -0,0 +1,36 @@
+int main() {
+ asm volatile("li x0, 0\n\t"
+ "li x1, 1\n\t"
+ "li x2, 2\n\t"
+ "li x3, 3\n\t"
+ "li x4, 4\n\t"
+ "li x5, 5\n\t"
+ "li x6, 6\n\t"
+ "li x7, 7\n\t"
+ "li x9, 9\n\t"
+ "li x10, 10\n\t"
+ "li x11, 11\n\t"
+ "li x12, 12\n\t"
+ "li x13, 13\n\t"
+ "li x14, 14\n\t"
+ "li x15, 15\n\t"
+ "li x16, 16\n\t"
+ "li x17, 17\n\t"
+ "li x18, 18\n\t"
+ "li x19, 19\n\t"
+ "li x20, 20\n\t"
+ "li x21, 21\n\t"
+ "li x22, 22\n\t"
+ "li x23, 23\n\t"
+ "li x24, 24\n\t"
+ "li x25, 25\n\t"
+ "li x26, 26\n\t"
+ "li x27, 27\n\t"
+ "li x28, 28\n\t"
+ "li x29, 29\n\t"
+ "li x30, 30\n\t"
+ "li x31, 31\n\t"
+ "ebreak \n\t");
+
+ return 0;
+}
diff --git a/lldb/test/Shell/Register/riscv64-gp-read.test b/lldb/test/Shell/Register/riscv64-gp-read.test
new file mode 100644
index 0000000000000..b3c894675f973
--- /dev/null
+++ b/lldb/test/Shell/Register/riscv64-gp-read.test
@@ -0,0 +1,141 @@
+# REQUIRES: native && target-riscv64
+# RUN: %clangxx_host %p/Inputs/riscv64-gp-read.cpp -o %t
+# RUN: %lldb -b -s %s %t | FileCheck %s
+process launch
+
+register read --all
+# CHECK-DAG: ra = 0x1
+# CHECK-DAG: sp = 0x2
+# CHECK-DAG: gp = 0x3
+# CHECK-DAG: tp = 0x4
+# CHECK-DAG: t0 = 0x5
+# CHECK-DAG: t1 = 0x6
+# CHECK-DAG: t2 = 0x7
+# CHECK-DAG: fp = 0x00007ffffffffc60
+# CHECK-DAG: s1 = 0x9
+# CHECK-DAG: a0 = 0xa
+# CHECK-DAG: a1 = 0xb
+# CHECK-DAG: a2 = 0xc
+# CHECK-DAG: a3 = 0xd
+# CHECK-DAG: a4 = 0xe
+# CHECK-DAG: a5 = 0xf
+# CHECK-DAG: a6 = 0x10
+# CHECK-DAG: a7 = 0x11
+# CHECK-DAG: s2 = 0x12
+# CHECK-DAG: s3 = 0x13
+# CHECK-DAG: s4 = 0x14
+# CHECK-DAG: s5 = 0x15
+# CHECK-DAG: s6 = 0x16
+# CHECK-DAG: s7 = 0x17
+# CHECK-DAG: s8 = 0x18
+# CHECK-DAG: s9 = 0x19
+# CHECK-DAG: s10 = 0x1a
+# CHECK-DAG: s11 = 0x1b
+# CHECK-DAG: t3 = 0x1c
+# CHECK-DAG: t4 = 0x1d
+# CHECK-DAG: t5 = 0x1e
+# CHECK-DAG: t6 = 0x1f
+# CHECK-DAG: zero = 0x0
+
+register read zero ra sp gp tp t0 t1 t2 s0 fp s1 a0 a1 a2 a3 a4 a5 a6 a7 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 t3 t4 t5 t6
+# CHECK-DAG: zero = 0x0
+# CHECK-DAG: ra = 0x1
+# CHECK-DAG: sp = 0x2
+# CHECK-DAG: gp = 0x3
+# CHECK-DAG: tp = 0x4
+# CHECK-DAG: t0 = 0x5
+# CHECK-DAG: t1 = 0x6
+# CHECK-DAG: t2 = 0x7
+# CHECK-DAG: fp = 0x00007ffffffffc60
+# CHECK-DAG: fp = 0x00007ffffffffc60
+# CHECK-DAG: s1 = 0x9
+# CHECK-DAG: a0 = 0xa
+# CHECK-DAG: a1 = 0xb
+# CHECK-DAG: a2 = 0xc
+# CHECK-DAG: a3 = 0xd
+# CHECK-DAG: a4 = 0xe
+# CHECK-DAG: a5 = 0xf
+# CHECK-DAG: a6 = 0x10
+# CHECK-DAG: a7 = 0x11
+# CHECK-DAG: s2 = 0x12
+# CHECK-DAG: s3 = 0x13
+# CHECK-DAG: s4 = 0x14
+# CHECK-DAG: s5 = 0x15
+# CHECK-DAG: s6 = 0x16
+# CHECK-DAG: s7 = 0x17
+# CHECK-DAG: s8 = 0x18
+# CHECK-DAG: s9 = 0x19
+# CHECK-DAG: s10 = 0x1a
+# CHECK-DAG: s11 = 0x1b
+# CHECK-DAG: t3 = 0x1c
+# CHECK-DAG: t4 = 0x1d
+# CHECK-DAG: t5 = 0x1e
+# CHECK-DAG: t6 = 0x1f
+
+register read zero ra sp gp tp t0 t1 t2 s0 fp s1 a0 a1 a2 a3 a4 a5 a6 a7 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 t3 t4 t5 t6
+# CHECK-DAG: zero = 0x0
+# CHECK-DAG: ra = 0x1
+# CHECK-DAG: sp = 0x2
+# CHECK-DAG: gp = 0x3
+# CHECK-DAG: tp = 0x4
+# CHECK-DAG: t0 = 0x5
+# CHECK-DAG: t1 = 0x6
+# CHECK-DAG: t2 = 0x7
+# CHECK-DAG: fp = 0x00007ffffffffc60
+# CHECK-DAG: fp = 0x00007ffffffffc60
+# CHECK-DAG: s1 = 0x9
+# CHECK-DAG: a0 = 0xa
+# CHECK-DAG: a1 = 0xb
+# CHECK-DAG: a2 = 0xc
+# CHECK-DAG: a3 = 0xd
+# CHECK-DAG: a4 = 0xe
+# CHECK-DAG: a5 = 0xf
+# CHECK-DAG: a6 = 0x10
+# CHECK-DAG: a7 = 0x11
+# CHECK-DAG: s2 = 0x12
+# CHECK-DAG: s3 = 0x13
+# CHECK-DAG: s4 = 0x14
+# CHECK-DAG: s5 = 0x15
+# CHECK-DAG: s6 = 0x16
+# CHECK-DAG: s7 = 0x17
+# CHECK-DAG: s8 = 0x18
+# CHECK-DAG: s9 = 0x19
+# CHECK-DAG: s10 = 0x1a
+# CHECK-DAG: s11 = 0x1b
+# CHECK-DAG: t3 = 0x1c
+# CHECK-DAG: t4 = 0x1d
+# CHECK-DAG: t5 = 0x1e
+# CHECK-DAG: t6 = 0x1f
+
+register read x0 x1 x2 x3 x4 x5 x6 x7 x9 x10 x11 x12 x13 x14 x15 x16 x17 x18 x19 x20 x21 x22 x23 x24 x25 x26 x27 x28 x29 x30 x31
+# CHECK-DAG: zero = 0x0
+# CHECK-DAG: ra = 0x1
+# CHECK-DAG: sp = 0x2
+# CHECK-DAG: gp = 0x3
+# CHECK-DAG: tp = 0x4
+# CHECK-DAG: t0 = 0x5
+# CHECK-DAG: t1 = 0x6
+# CHECK-DAG: t2 = 0x7
+# CHECK-DAG: s1 = 0x9
+# CHECK-DAG: a0 = 0xa
+# CHECK-DAG: a1 = 0xb
+# CHECK-DAG: a2 = 0xc
+# CHECK-DAG: a3 = 0xd
+# CHECK-DAG: a4 = 0xe
+# CHECK-DAG: a5 = 0xf
+# CHECK-DAG: a6 = 0x10
+# CHECK-DAG: a7 = 0x11
+# CHECK-DAG: s2 = 0x12
+# CHECK-DAG: s3 = 0x13
+# CHECK-DAG: s4 = 0x14
+# CHECK-DAG: s5 = 0x15
+# CHECK-DAG: s6 = 0x16
+# CHECK-DAG: s7 = 0x17
+# CHECK-DAG: s8 = 0x18
+# CHECK-DAG: s9 = 0x19
+# CHECK-DAG: s10 = 0x1a
+# CHECK-DAG: s11 = 0x1b
+# CHECK-DAG: t3 = 0x1c
+# CHECK-DAG: t4 = 0x1d
+# CHECK-DAG: t5 = 0x1e
+# CHECK-DAG: t6 = 0x1f
\ No newline at end of file
diff --git a/llvm/utils/lit/lit/llvm/config.py b/llvm/utils/lit/lit/llvm/config.py
index 5f762ec7f3514..e40a422d2db6c 100644
--- a/llvm/utils/lit/lit/llvm/config.py
+++ b/llvm/utils/lit/lit/llvm/config.py
@@ -169,8 +169,12 @@ def __init__(self, lit_config, config):
features.add("target-aarch64")
elif re.match(r"^arm.*", target_triple):
features.add("target-arm")
- if re.match(r'^ppc64le.*-linux', target_triple):
- features.add('target=powerpc64le-linux')
+ elif re.match(r"^ppc64le.*-linux", target_triple):
+ features.add("target=powerpc64le-linux")
+ elif re.match(r"^riscv64-.*-elf", target_triple):
+ features.add("target-riscv64")
+ elif re.match(r"^riscv32-.*-elf.", target_triple):
+ features.add("target-riscv32")
if not user_is_root():
features.add("non-root-user")
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