[Lldb-commits] [lldb] [lldb] Extended if conditions to support alias names for registers (PR #124475)

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``````````bash
darker --check --diff -r f8ab91f74f152c8a6d8aaedb8165109c497a618d...be1c2a0b1b2014b66fe0f4418230395a25016cc8 lldb/test/API/functionalities/gdb_remote_client/TestGDBServerTargetXML.py lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py
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``````````diff
--- gdb_remote_client/TestGDBServerTargetXML.py	2025-01-28 15:23:54.000000 +0000
+++ gdb_remote_client/TestGDBServerTargetXML.py	2025-01-28 16:33:09.693976 +0000
@@ -658,44 +658,42 @@
     def test_riscv64_regs(self):
         """Test grabbing various riscv64 registers from gdbserver."""
 
         class MyResponder(MockGDBServerResponder):
             reg_data = (
-                (
-                    "0102030405060708"  # zero
-                    "0102030405060708"  # ra
-                    "0102030405060708"  # sp
-                    "0102030405060708"  # gp
-                    "0102030405060708"  # tp
-                    "0102030405060708"  # t0 
-                    "0102030405060708"  # t1
-                    "0102030405060708"  # t2
-                    "0102030405060708"  # fp 
-                    "0102030405060708"  # s1
-                    "0102030405060708"  # a0
-                    "0102030405060708"  # a1
-                    "0102030405060708"  # a2
-                    "0102030405060708"  # a3
-                    "0102030405060708"  # a4
-                    "0102030405060708"  # a5
-                    "0102030405060708"  # a6
-                    "0102030405060708"  # a7
-                    "0102030405060708"  # s2
-                    "0102030405060708"  # s3
-                    "0102030405060708"  # s4
-                    "0102030405060708"  # s5
-                    "0102030405060708"  # s6
-                    "0102030405060708"  # s7
-                    "0102030405060708"  # s8
-                    "0102030405060708"  # s9
-                    "0102030405060708"  # s10
-                    "0102030405060708"  # s11
-                    "0102030405060708"  # t3
-                    "0102030405060708"  # t4
-                    "0102030405060708"  # t5
-                    "0102030405060708"  # t6
-                )
+                "0102030405060708"  # zero
+                "0102030405060708"  # ra
+                "0102030405060708"  # sp
+                "0102030405060708"  # gp
+                "0102030405060708"  # tp
+                "0102030405060708"  # t0
+                "0102030405060708"  # t1
+                "0102030405060708"  # t2
+                "0102030405060708"  # fp
+                "0102030405060708"  # s1
+                "0102030405060708"  # a0
+                "0102030405060708"  # a1
+                "0102030405060708"  # a2
+                "0102030405060708"  # a3
+                "0102030405060708"  # a4
+                "0102030405060708"  # a5
+                "0102030405060708"  # a6
+                "0102030405060708"  # a7
+                "0102030405060708"  # s2
+                "0102030405060708"  # s3
+                "0102030405060708"  # s4
+                "0102030405060708"  # s5
+                "0102030405060708"  # s6
+                "0102030405060708"  # s7
+                "0102030405060708"  # s8
+                "0102030405060708"  # s9
+                "0102030405060708"  # s10
+                "0102030405060708"  # s11
+                "0102030405060708"  # t3
+                "0102030405060708"  # t4
+                "0102030405060708"  # t5
+                "0102030405060708"
             )
 
             def qXferRead(self, obj, annex, offset, length):
                 if annex == "target.xml":
                     return (
@@ -797,11 +795,10 @@
         self.match("register read x27", ["s11 = 0x0807060504030201"])
         self.match("register read x28", ["t3 = 0x0807060504030201"])
         self.match("register read x29", ["t4 = 0x0807060504030201"])
         self.match("register read x30", ["t5 = 0x0807060504030201"])
         self.match("register read x31", ["t6 = 0x0807060504030201"])
-
 
     @skipIfXmlSupportMissing
     @skipIfRemote
     @skipIfLLVMTargetMissing("X86")
     def test_x86_64_no_duplicate_subregs(self):

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https://github.com/llvm/llvm-project/pull/124475