[Lldb-commits] [lldb] [lldb] Support riscv32 corefiles (PR #115408)
Jonas Devlieghere via lldb-commits
lldb-commits at lists.llvm.org
Thu Nov 7 17:20:31 PST 2024
https://github.com/JDevlieghere created https://github.com/llvm/llvm-project/pull/115408
None
>From db9978e0bf8ce26a71eb73393c4951d14cdbd510 Mon Sep 17 00:00:00 2001
From: Jonas Devlieghere <jonas at devlieghere.com>
Date: Thu, 7 Nov 2024 17:18:50 -0800
Subject: [PATCH] [lldb] Support riscv32 corefiles
---
.../Plugins/Process/Utility/CMakeLists.txt | 2 +
.../Utility/RegisterContextPOSIX_riscv32.cpp | 81 ++++++++
.../Utility/RegisterContextPOSIX_riscv32.h | 63 ++++++
.../Utility/RegisterInfoPOSIX_riscv32.cpp | 142 ++++++++++++++
.../Utility/RegisterInfoPOSIX_riscv32.h | 76 +++++++
.../Utility/RegisterInfoPOSIX_riscv64.cpp | 9 +-
.../Process/Utility/RegisterInfos_riscv32.h | 185 ++++++++++++++++++
.../Plugins/Process/elf-core/CMakeLists.txt | 1 +
.../RegisterContextPOSIXCore_riscv32.cpp | 81 ++++++++
.../RegisterContextPOSIXCore_riscv32.h | 56 ++++++
10 files changed, 691 insertions(+), 5 deletions(-)
create mode 100644 lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_riscv32.cpp
create mode 100644 lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_riscv32.h
create mode 100644 lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_riscv32.cpp
create mode 100644 lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_riscv32.h
create mode 100644 lldb/source/Plugins/Process/Utility/RegisterInfos_riscv32.h
create mode 100644 lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv32.cpp
create mode 100644 lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv32.h
diff --git a/lldb/source/Plugins/Process/Utility/CMakeLists.txt b/lldb/source/Plugins/Process/Utility/CMakeLists.txt
index 308ea29e31ad77..5ffd2d7114cc98 100644
--- a/lldb/source/Plugins/Process/Utility/CMakeLists.txt
+++ b/lldb/source/Plugins/Process/Utility/CMakeLists.txt
@@ -39,6 +39,7 @@ add_lldb_library(lldbPluginProcessUtility
RegisterContextPOSIX_arm64.cpp
RegisterContextPOSIX_loongarch64.cpp
RegisterContextPOSIX_mips64.cpp
+ RegisterContextPOSIX_riscv32.cpp
RegisterContextPOSIX_powerpc.cpp
RegisterContextPOSIX_ppc64le.cpp
RegisterContextPOSIX_riscv64.cpp
@@ -53,6 +54,7 @@ add_lldb_library(lldbPluginProcessUtility
RegisterInfoPOSIX_arm64.cpp
RegisterInfoPOSIX_loongarch64.cpp
RegisterInfoPOSIX_ppc64le.cpp
+ RegisterInfoPOSIX_riscv32.cpp
RegisterInfoPOSIX_riscv64.cpp
StopInfoMachException.cpp
ThreadMemory.cpp
diff --git a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_riscv32.cpp b/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_riscv32.cpp
new file mode 100644
index 00000000000000..64064f86cea046
--- /dev/null
+++ b/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_riscv32.cpp
@@ -0,0 +1,81 @@
+//===-- RegisterContextPOSIX_riscv32.cpp ------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "RegisterContextPOSIX_riscv32.h"
+#include "lldb/Target/Process.h"
+#include "lldb/Target/Target.h"
+#include "lldb/Target/Thread.h"
+#include "lldb/Utility/DataBufferHeap.h"
+#include "lldb/Utility/DataExtractor.h"
+#include "lldb/Utility/Endian.h"
+#include "lldb/Utility/RegisterValue.h"
+#include "lldb/Utility/Scalar.h"
+#include "llvm/Support/Compiler.h"
+
+using namespace lldb;
+using namespace lldb_private;
+
+RegisterContextPOSIX_riscv32::RegisterContextPOSIX_riscv32(
+ lldb_private::Thread &thread,
+ std::unique_ptr<RegisterInfoPOSIX_riscv32> register_info)
+ : lldb_private::RegisterContext(thread, 0),
+ m_register_info_up(std::move(register_info)) {}
+
+RegisterContextPOSIX_riscv32::~RegisterContextPOSIX_riscv32() = default;
+
+void RegisterContextPOSIX_riscv32::invalidate() {}
+
+void RegisterContextPOSIX_riscv32::InvalidateAllRegisters() {}
+
+size_t RegisterContextPOSIX_riscv32::GetRegisterCount() {
+ return m_register_info_up->GetRegisterCount();
+}
+
+size_t RegisterContextPOSIX_riscv32::GetGPRSize() {
+ return m_register_info_up->GetGPRSize();
+}
+
+unsigned RegisterContextPOSIX_riscv32::GetRegisterSize(unsigned int reg) {
+ return m_register_info_up->GetRegisterInfo()[reg].byte_size;
+}
+
+unsigned RegisterContextPOSIX_riscv32::GetRegisterOffset(unsigned int reg) {
+ return m_register_info_up->GetRegisterInfo()[reg].byte_offset;
+}
+
+const lldb_private::RegisterInfo *
+RegisterContextPOSIX_riscv32::GetRegisterInfoAtIndex(size_t reg) {
+ if (reg < GetRegisterCount())
+ return &GetRegisterInfo()[reg];
+
+ return nullptr;
+}
+
+size_t RegisterContextPOSIX_riscv32::GetRegisterSetCount() {
+ return m_register_info_up->GetRegisterCount();
+}
+
+const lldb_private::RegisterSet *
+RegisterContextPOSIX_riscv32::GetRegisterSet(size_t set) {
+ return m_register_info_up->GetRegisterSet(set);
+}
+
+const lldb_private::RegisterInfo *
+RegisterContextPOSIX_riscv32::GetRegisterInfo() {
+ return m_register_info_up->GetRegisterInfo();
+}
+
+bool RegisterContextPOSIX_riscv32::IsGPR(unsigned int reg) {
+ return m_register_info_up->GetRegisterSetFromRegisterIndex(reg) ==
+ RegisterInfoPOSIX_riscv32::eRegsetMaskDefault;
+}
+
+bool RegisterContextPOSIX_riscv32::IsFPR(unsigned int reg) {
+ return m_register_info_up->GetRegisterSetFromRegisterIndex(reg) ==
+ RegisterInfoPOSIX_riscv32::eRegsetMaskFP;
+}
diff --git a/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_riscv32.h b/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_riscv32.h
new file mode 100644
index 00000000000000..0c25ce11f5754c
--- /dev/null
+++ b/lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_riscv32.h
@@ -0,0 +1,63 @@
+//===-- RegisterContextPOSIX_riscv32.h --------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTPOSIX_RISCV32_H
+#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTPOSIX_RISCV32_H
+
+#include "RegisterInfoInterface.h"
+#include "RegisterInfoPOSIX_riscv32.h"
+#include "lldb-riscv-register-enums.h"
+#include "lldb/Target/RegisterContext.h"
+#include "lldb/Utility/Log.h"
+
+class RegisterContextPOSIX_riscv32 : public lldb_private::RegisterContext {
+public:
+ RegisterContextPOSIX_riscv32(
+ lldb_private::Thread &thread,
+ std::unique_ptr<RegisterInfoPOSIX_riscv32> register_info);
+
+ ~RegisterContextPOSIX_riscv32() override;
+
+ void invalidate();
+
+ void InvalidateAllRegisters() override;
+
+ size_t GetRegisterCount() override;
+
+ virtual size_t GetGPRSize();
+
+ virtual unsigned GetRegisterSize(unsigned reg);
+
+ virtual unsigned GetRegisterOffset(unsigned reg);
+
+ const lldb_private::RegisterInfo *GetRegisterInfoAtIndex(size_t reg) override;
+
+ size_t GetRegisterSetCount() override;
+
+ const lldb_private::RegisterSet *GetRegisterSet(size_t set) override;
+
+protected:
+ std::unique_ptr<RegisterInfoPOSIX_riscv32> m_register_info_up;
+
+ virtual const lldb_private::RegisterInfo *GetRegisterInfo();
+
+ bool IsGPR(unsigned reg);
+
+ bool IsFPR(unsigned reg);
+
+ size_t GetFPRSize() { return sizeof(RegisterInfoPOSIX_riscv32::FPR); }
+
+ uint32_t GetRegNumFCSR() const { return fpr_fcsr_riscv; }
+
+ virtual bool ReadGPR() = 0;
+ virtual bool ReadFPR() = 0;
+ virtual bool WriteGPR() = 0;
+ virtual bool WriteFPR() = 0;
+};
+
+#endif // LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERCONTEXTPOSIX_RISCV32_H
diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_riscv32.cpp b/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_riscv32.cpp
new file mode 100644
index 00000000000000..e213b4a4a18200
--- /dev/null
+++ b/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_riscv32.cpp
@@ -0,0 +1,142 @@
+//===-- RegisterInfoPOSIX_riscv32.cpp -------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===---------------------------------------------------------------------===//
+
+#include "RegisterInfoPOSIX_riscv32.h"
+#include "lldb/Utility/Flags.h"
+#include "lldb/lldb-defines.h"
+#include "llvm/Support/Compiler.h"
+
+#include <cassert>
+#include <stddef.h>
+
+#define GPR_OFFSET(idx) ((idx) * 4 + 0)
+#define FPR_OFFSET(idx) ((idx) * 4 + sizeof(RegisterInfoPOSIX_riscv32::GPR))
+
+#define REG_CONTEXT_SIZE \
+ (sizeof(RegisterInfoPOSIX_riscv32::GPR) + \
+ sizeof(RegisterInfoPOSIX_riscv32::FPR))
+
+#define DECLARE_REGISTER_INFOS_RISCV32_STRUCT
+#include "RegisterInfos_riscv32.h"
+#undef DECLARE_REGISTER_INFOS_RISCV32_STRUCT
+
+const lldb_private::RegisterInfo *RegisterInfoPOSIX_riscv32::GetRegisterInfoPtr(
+ const lldb_private::ArchSpec &target_arch) {
+ switch (target_arch.GetMachine()) {
+ case llvm::Triple::riscv32:
+ return g_register_infos_riscv32_le;
+ default:
+ assert(false && "Unhandled target architecture.");
+ return nullptr;
+ }
+}
+
+uint32_t RegisterInfoPOSIX_riscv32::GetRegisterInfoCount(
+ const lldb_private::ArchSpec &target_arch) {
+ switch (target_arch.GetMachine()) {
+ case llvm::Triple::riscv32:
+ return static_cast<uint32_t>(sizeof(g_register_infos_riscv32_le) /
+ sizeof(g_register_infos_riscv32_le[0]));
+ default:
+ assert(false && "Unhandled target architecture.");
+ return 0;
+ }
+}
+
+// Number of register sets provided by this context.
+enum {
+ k_num_gpr_registers = gpr_last_riscv - gpr_first_riscv + 1,
+ k_num_fpr_registers = fpr_last_riscv - fpr_first_riscv + 1,
+ k_num_register_sets = 2
+};
+
+// RISC-V32 general purpose registers.
+static const uint32_t g_gpr_regnums_riscv32[] = {
+ gpr_pc_riscv, gpr_ra_riscv, gpr_sp_riscv, gpr_x3_riscv,
+ gpr_x4_riscv, gpr_x5_riscv, gpr_x6_riscv, gpr_x7_riscv,
+ gpr_fp_riscv, gpr_x9_riscv, gpr_x10_riscv, gpr_x11_riscv,
+ gpr_x12_riscv, gpr_x13_riscv, gpr_x14_riscv, gpr_x15_riscv,
+ gpr_x16_riscv, gpr_x17_riscv, gpr_x18_riscv, gpr_x19_riscv,
+ gpr_x20_riscv, gpr_x21_riscv, gpr_x22_riscv, gpr_x23_riscv,
+ gpr_x24_riscv, gpr_x25_riscv, gpr_x26_riscv, gpr_x27_riscv,
+ gpr_x28_riscv, gpr_x29_riscv, gpr_x30_riscv, gpr_x31_riscv,
+ gpr_x0_riscv, LLDB_INVALID_REGNUM};
+
+static_assert(((sizeof g_gpr_regnums_riscv32 /
+ sizeof g_gpr_regnums_riscv32[0]) -
+ 1) == k_num_gpr_registers,
+ "g_gpr_regnums_riscv32 has wrong number of register infos");
+
+// RISC-V32 floating point registers.
+static const uint32_t g_fpr_regnums_riscv32[] = {
+ fpr_f0_riscv, fpr_f1_riscv, fpr_f2_riscv, fpr_f3_riscv,
+ fpr_f4_riscv, fpr_f5_riscv, fpr_f6_riscv, fpr_f7_riscv,
+ fpr_f8_riscv, fpr_f9_riscv, fpr_f10_riscv, fpr_f11_riscv,
+ fpr_f12_riscv, fpr_f13_riscv, fpr_f14_riscv, fpr_f15_riscv,
+ fpr_f16_riscv, fpr_f17_riscv, fpr_f18_riscv, fpr_f19_riscv,
+ fpr_f20_riscv, fpr_f21_riscv, fpr_f22_riscv, fpr_f23_riscv,
+ fpr_f24_riscv, fpr_f25_riscv, fpr_f26_riscv, fpr_f27_riscv,
+ fpr_f28_riscv, fpr_f29_riscv, fpr_f30_riscv, fpr_f31_riscv,
+ fpr_fcsr_riscv, LLDB_INVALID_REGNUM};
+
+static_assert(((sizeof g_fpr_regnums_riscv32 /
+ sizeof g_fpr_regnums_riscv32[0]) -
+ 1) == k_num_fpr_registers,
+ "g_fpr_regnums_riscv32 has wrong number of register infos");
+
+// Register sets for RISC-V32.
+static const lldb_private::RegisterSet g_reg_sets_riscv32[k_num_register_sets] =
+ {{"General Purpose Registers", "gpr", k_num_gpr_registers,
+ g_gpr_regnums_riscv32},
+ {"Floating Point Registers", "fpr", k_num_fpr_registers,
+ g_fpr_regnums_riscv32}};
+
+RegisterInfoPOSIX_riscv32::RegisterInfoPOSIX_riscv32(
+ const lldb_private::ArchSpec &target_arch, lldb_private::Flags opt_regsets)
+ : lldb_private::RegisterInfoAndSetInterface(target_arch),
+ m_register_info_p(GetRegisterInfoPtr(target_arch)),
+ m_register_info_count(GetRegisterInfoCount(target_arch)),
+ m_opt_regsets(opt_regsets) {}
+
+uint32_t RegisterInfoPOSIX_riscv32::GetRegisterCount() const {
+ return m_register_info_count;
+}
+
+size_t RegisterInfoPOSIX_riscv32::GetGPRSize() const {
+ return sizeof(struct RegisterInfoPOSIX_riscv32::GPR);
+}
+
+size_t RegisterInfoPOSIX_riscv32::GetFPRSize() const {
+ return sizeof(struct RegisterInfoPOSIX_riscv32::FPR);
+}
+
+const lldb_private::RegisterInfo *
+RegisterInfoPOSIX_riscv32::GetRegisterInfo() const {
+ return m_register_info_p;
+}
+
+size_t RegisterInfoPOSIX_riscv32::GetRegisterSetCount() const {
+ return k_num_register_sets;
+}
+
+size_t RegisterInfoPOSIX_riscv32::GetRegisterSetFromRegisterIndex(
+ uint32_t reg_index) const {
+ // coverity[unsigned_compare]
+ if (reg_index >= gpr_first_riscv && reg_index <= gpr_last_riscv)
+ return eRegsetMaskDefault;
+ if (reg_index >= fpr_first_riscv && reg_index <= fpr_last_riscv)
+ return eRegsetMaskFP;
+ return LLDB_INVALID_REGNUM;
+}
+
+const lldb_private::RegisterSet *
+RegisterInfoPOSIX_riscv32::GetRegisterSet(size_t set_index) const {
+ if (set_index < GetRegisterSetCount())
+ return &g_reg_sets_riscv32[set_index];
+ return nullptr;
+}
diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_riscv32.h b/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_riscv32.h
new file mode 100644
index 00000000000000..f8d85f9e728938
--- /dev/null
+++ b/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_riscv32.h
@@ -0,0 +1,76 @@
+//===-- RegisterInfoPOSIX_riscv32.h -----------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOPOSIX_RISCV32_H
+#define LLDB_SOURCE_PLUGINS_PROCESS_UTILITY_REGISTERINFOPOSIX_RISCV32_H
+
+#include "RegisterInfoAndSetInterface.h"
+#include "lldb/Target/RegisterContext.h"
+#include "lldb/Utility/Flags.h"
+#include "lldb/lldb-private.h"
+
+#include <map>
+
+class RegisterInfoPOSIX_riscv32
+ : public lldb_private::RegisterInfoAndSetInterface {
+public:
+ static const lldb_private::RegisterInfo *
+ GetRegisterInfoPtr(const lldb_private::ArchSpec &target_arch);
+ static uint32_t
+ GetRegisterInfoCount(const lldb_private::ArchSpec &target_arch);
+
+public:
+ // RISC-V32 register set mask value
+ enum {
+ eRegsetMaskDefault = 0,
+ eRegsetMaskFP = 1,
+ eRegsetMaskAll = -1,
+ };
+
+ struct GPR {
+ // note: gpr[0] is pc, not x0
+ uint32_t gpr[32];
+ };
+
+ struct FPR {
+ uint32_t fpr[32];
+ uint32_t fcsr;
+ };
+
+ struct VPR {
+ // The size should be VLEN*32 in bits, but we don't have VLEN here.
+ void *vpr;
+ };
+
+ RegisterInfoPOSIX_riscv32(const lldb_private::ArchSpec &target_arch,
+ lldb_private::Flags flags);
+
+ size_t GetGPRSize() const override;
+
+ size_t GetFPRSize() const override;
+
+ const lldb_private::RegisterInfo *GetRegisterInfo() const override;
+
+ uint32_t GetRegisterCount() const override;
+
+ const lldb_private::RegisterSet *
+ GetRegisterSet(size_t reg_set) const override;
+
+ size_t GetRegisterSetCount() const override;
+
+ size_t GetRegisterSetFromRegisterIndex(uint32_t reg_index) const override;
+
+ bool IsFPPresent() const { return m_opt_regsets.AnySet(eRegsetMaskFP); }
+
+private:
+ const lldb_private::RegisterInfo *m_register_info_p;
+ uint32_t m_register_info_count;
+ lldb_private::Flags m_opt_regsets;
+};
+
+#endif
diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.cpp b/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.cpp
index 4a3737795848e9..a0be54fc76cd53 100644
--- a/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.cpp
+++ b/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.cpp
@@ -6,14 +6,13 @@
//
//===---------------------------------------------------------------------===//
-#include <cassert>
-#include <lldb/Utility/Flags.h>
-#include <stddef.h>
-
+#include "RegisterInfoPOSIX_riscv64.h"
+#include "lldb/Utility/Flags.h"
#include "lldb/lldb-defines.h"
#include "llvm/Support/Compiler.h"
-#include "RegisterInfoPOSIX_riscv64.h"
+#include <cassert>
+#include <stddef.h>
#define GPR_OFFSET(idx) ((idx)*8 + 0)
#define FPR_OFFSET(idx) ((idx)*8 + sizeof(RegisterInfoPOSIX_riscv64::GPR))
diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfos_riscv32.h b/lldb/source/Plugins/Process/Utility/RegisterInfos_riscv32.h
new file mode 100644
index 00000000000000..ab6fec829bbcea
--- /dev/null
+++ b/lldb/source/Plugins/Process/Utility/RegisterInfos_riscv32.h
@@ -0,0 +1,185 @@
+//===-- RegisterInfos_riscv32.h ---------------------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifdef DECLARE_REGISTER_INFOS_RISCV32_STRUCT
+
+#include "Utility/RISCV_DWARF_Registers.h"
+#include "lldb-riscv-register-enums.h"
+#include "lldb/lldb-defines.h"
+#include "lldb/lldb-enumerations.h"
+#include "lldb/lldb-private.h"
+
+#include <stddef.h>
+
+#ifndef GPR_OFFSET
+#error GPR_OFFSET must be defined before including this header file
+#endif
+
+#ifndef FPR_OFFSET
+#error FPR_OFFSET must be defined before including this header file
+#endif
+
+using namespace riscv_dwarf;
+
+// clang-format off
+
+// I suppose EHFrame and DWARF are the same.
+#define KIND_HELPER(reg, generic_kind) \
+ { \
+ riscv_dwarf::dwarf_##reg, riscv_dwarf::dwarf_##reg, generic_kind, \
+ LLDB_INVALID_REGNUM, reg##_riscv \
+ }
+
+// Generates register kinds array for vector registers
+#define GPR32_KIND(reg, generic_kind) KIND_HELPER(reg, generic_kind)
+
+// FPR register kinds array for vector registers
+#define FPR32_KIND(reg, generic_kind) KIND_HELPER(reg, generic_kind)
+
+// VPR register kinds array for vector registers
+#define VPR_KIND(reg, generic_kind) KIND_HELPER(reg, generic_kind)
+
+// Defines a 32-bit general purpose register
+#define DEFINE_GPR32(reg, generic_kind) DEFINE_GPR32_ALT(reg, reg, generic_kind)
+
+// Defines a 32-bit general purpose register
+#define DEFINE_GPR32_ALT(reg, alt, generic_kind) \
+ { \
+ #reg, #alt, 4, GPR_OFFSET(gpr_##reg##_riscv - gpr_first_riscv), \
+ lldb::eEncodingUint, lldb::eFormatHex, \
+ GPR32_KIND(gpr_##reg, generic_kind), nullptr, nullptr, nullptr, \
+ }
+
+#define DEFINE_FPR32(reg, generic_kind) DEFINE_FPR32_ALT(reg, reg, generic_kind)
+
+#define DEFINE_FPR32_ALT(reg, alt, generic_kind) DEFINE_FPR_ALT(reg, alt, 4, generic_kind)
+
+#define DEFINE_FPR_ALT(reg, alt, size, generic_kind) \
+ { \
+ #reg, #alt, size, FPR_OFFSET(fpr_##reg##_riscv - fpr_first_riscv), \
+ lldb::eEncodingUint, lldb::eFormatHex, \
+ FPR32_KIND(fpr_##reg, generic_kind), nullptr, nullptr, nullptr, \
+ }
+
+#define DEFINE_VPR(reg, generic_kind) DEFINE_VPR_ALT(reg, reg, generic_kind)
+
+// Defines a scalable vector register, with default size 128 bits
+// The byte offset 0 is a placeholder, which should be corrected at runtime.
+#define DEFINE_VPR_ALT(reg, alt, generic_kind) \
+ { \
+ #reg, #alt, 16, 0, lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, \
+ VPR_KIND(vpr_##reg, generic_kind), nullptr, nullptr, nullptr \
+ }
+
+// clang-format on
+
+static lldb_private::RegisterInfo g_register_infos_riscv32_le[] = {
+ // DEFINE_GPR32(name, GENERIC KIND)
+ DEFINE_GPR32(pc, LLDB_REGNUM_GENERIC_PC),
+ DEFINE_GPR32_ALT(ra, x1, LLDB_REGNUM_GENERIC_RA),
+ DEFINE_GPR32_ALT(sp, x2, LLDB_REGNUM_GENERIC_SP),
+ DEFINE_GPR32_ALT(gp, x3, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(tp, x4, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(t0, x5, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(t1, x6, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(t2, x7, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(fp, x8, LLDB_REGNUM_GENERIC_FP),
+ DEFINE_GPR32_ALT(s1, x9, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(a0, x10, LLDB_REGNUM_GENERIC_ARG1),
+ DEFINE_GPR32_ALT(a1, x11, LLDB_REGNUM_GENERIC_ARG2),
+ DEFINE_GPR32_ALT(a2, x12, LLDB_REGNUM_GENERIC_ARG3),
+ DEFINE_GPR32_ALT(a3, x13, LLDB_REGNUM_GENERIC_ARG4),
+ DEFINE_GPR32_ALT(a4, x14, LLDB_REGNUM_GENERIC_ARG5),
+ DEFINE_GPR32_ALT(a5, x15, LLDB_REGNUM_GENERIC_ARG6),
+ DEFINE_GPR32_ALT(a6, x16, LLDB_REGNUM_GENERIC_ARG7),
+ DEFINE_GPR32_ALT(a7, x17, LLDB_REGNUM_GENERIC_ARG8),
+ DEFINE_GPR32_ALT(s2, x18, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(s3, x19, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(s4, x20, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(s5, x21, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(s6, x22, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(s7, x23, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(s8, x24, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(s9, x25, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(s10, x26, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(s11, x27, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(t3, x28, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(t4, x29, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(t5, x30, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(t6, x31, LLDB_INVALID_REGNUM),
+ DEFINE_GPR32_ALT(zero, x0, LLDB_INVALID_REGNUM),
+
+ DEFINE_FPR32_ALT(ft0, f0, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(ft1, f1, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(ft2, f2, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(ft3, f3, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(ft4, f4, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(ft5, f5, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(ft6, f6, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(ft7, f7, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fs0, f8, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fs1, f9, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fa0, f10, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fa1, f11, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fa2, f12, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fa3, f13, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fa4, f14, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fa5, f15, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fa6, f16, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fa7, f17, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fs2, f18, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fs3, f19, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fs4, f20, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fs5, f21, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fs6, f22, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fs7, f23, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fs8, f24, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fs9, f25, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fs10, f26, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(fs11, f27, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(ft8, f28, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(ft9, f29, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(ft10, f30, LLDB_INVALID_REGNUM),
+ DEFINE_FPR32_ALT(ft11, f31, LLDB_INVALID_REGNUM),
+ DEFINE_FPR_ALT(fcsr, nullptr, 4, LLDB_INVALID_REGNUM),
+
+ DEFINE_VPR(v0, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v1, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v2, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v3, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v4, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v5, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v6, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v7, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v8, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v9, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v10, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v11, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v12, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v13, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v14, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v15, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v16, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v17, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v18, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v19, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v20, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v21, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v22, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v23, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v24, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v25, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v26, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v27, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v28, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v29, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v30, LLDB_INVALID_REGNUM),
+ DEFINE_VPR(v31, LLDB_INVALID_REGNUM),
+};
+
+#endif // DECLARE_REGISTER_INFOS_RISCV32_STRUCT
diff --git a/lldb/source/Plugins/Process/elf-core/CMakeLists.txt b/lldb/source/Plugins/Process/elf-core/CMakeLists.txt
index 7473fa8d41ccb3..4b0f5199df7195 100644
--- a/lldb/source/Plugins/Process/elf-core/CMakeLists.txt
+++ b/lldb/source/Plugins/Process/elf-core/CMakeLists.txt
@@ -9,6 +9,7 @@ add_lldb_library(lldbPluginProcessElfCore PLUGIN
RegisterContextPOSIXCore_ppc64le.cpp
RegisterContextPOSIXCore_s390x.cpp
RegisterContextPOSIXCore_x86_64.cpp
+ RegisterContextPOSIXCore_riscv32.cpp
RegisterContextPOSIXCore_riscv64.cpp
RegisterContextPOSIXCore_loongarch64.cpp
RegisterUtilities.cpp
diff --git a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv32.cpp b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv32.cpp
new file mode 100644
index 00000000000000..79f546eda66f23
--- /dev/null
+++ b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv32.cpp
@@ -0,0 +1,81 @@
+//===-- RegisterContextPOSIXCore_riscv32.cpp ------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "RegisterContextPOSIXCore_riscv32.h"
+#include "lldb/Utility/DataBufferHeap.h"
+
+using namespace lldb_private;
+
+std::unique_ptr<RegisterContextCorePOSIX_riscv32>
+RegisterContextCorePOSIX_riscv32::Create(Thread &thread, const ArchSpec &arch,
+ const DataExtractor &gpregset,
+ llvm::ArrayRef<CoreNote> notes) {
+ Flags opt_regsets = RegisterInfoPOSIX_riscv32::eRegsetMaskDefault;
+
+ return std::unique_ptr<RegisterContextCorePOSIX_riscv32>(
+ new RegisterContextCorePOSIX_riscv32(
+ thread,
+ std::make_unique<RegisterInfoPOSIX_riscv32>(arch, opt_regsets),
+ gpregset, notes));
+}
+
+RegisterContextCorePOSIX_riscv32::RegisterContextCorePOSIX_riscv32(
+ Thread &thread, std::unique_ptr<RegisterInfoPOSIX_riscv32> register_info,
+ const DataExtractor &gpregset, llvm::ArrayRef<CoreNote> notes)
+ : RegisterContextPOSIX_riscv32(thread, std::move(register_info)) {
+
+ m_gpr.SetData(std::make_shared<DataBufferHeap>(gpregset.GetDataStart(),
+ gpregset.GetByteSize()));
+ m_gpr.SetByteOrder(gpregset.GetByteOrder());
+
+ if (m_register_info_up->IsFPPresent()) {
+ ArchSpec arch = m_register_info_up->GetTargetArchitecture();
+ m_fpr = getRegset(notes, arch.GetTriple(), FPR_Desc);
+ }
+}
+
+RegisterContextCorePOSIX_riscv32::~RegisterContextCorePOSIX_riscv32() = default;
+
+bool RegisterContextCorePOSIX_riscv32::ReadGPR() { return true; }
+
+bool RegisterContextCorePOSIX_riscv32::ReadFPR() { return true; }
+
+bool RegisterContextCorePOSIX_riscv32::WriteGPR() {
+ assert(false && "Writing registers is not allowed for core dumps");
+ return false;
+}
+
+bool RegisterContextCorePOSIX_riscv32::WriteFPR() {
+ assert(false && "Writing registers is not allowed for core dumps");
+ return false;
+}
+
+bool RegisterContextCorePOSIX_riscv32::ReadRegister(
+ const RegisterInfo *reg_info, RegisterValue &value) {
+ const uint8_t *src = nullptr;
+ lldb::offset_t offset = reg_info->byte_offset;
+
+ if (IsGPR(reg_info->kinds[lldb::eRegisterKindLLDB])) {
+ src = m_gpr.GetDataStart();
+ } else if (IsFPR(reg_info->kinds[lldb::eRegisterKindLLDB])) {
+ src = m_fpr.GetDataStart();
+ offset -= GetGPRSize();
+ } else {
+ return false;
+ }
+
+ Status error;
+ value.SetFromMemoryData(*reg_info, src + offset, reg_info->byte_size,
+ lldb::eByteOrderLittle, error);
+ return error.Success();
+}
+
+bool RegisterContextCorePOSIX_riscv32::WriteRegister(
+ const RegisterInfo *reg_info, const RegisterValue &value) {
+ return false;
+}
diff --git a/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv32.h b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv32.h
new file mode 100644
index 00000000000000..d2033bf0112909
--- /dev/null
+++ b/lldb/source/Plugins/Process/elf-core/RegisterContextPOSIXCore_riscv32.h
@@ -0,0 +1,56 @@
+//===-- RegisterContextPOSIXCore_riscv32.h ----------------------*- C++ -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLDB_SOURCE_PLUGINS_PROCESS_ELF_CORE_REGISTERCONTEXTPOSIXCORE_RISCV32_H
+#define LLDB_SOURCE_PLUGINS_PROCESS_ELF_CORE_REGISTERCONTEXTPOSIXCORE_RISCV32_H
+
+#include "Plugins/Process/Utility/RegisterContextPOSIX_riscv32.h"
+#include "Plugins/Process/Utility/RegisterInfoPOSIX_riscv32.h"
+#include "Plugins/Process/elf-core/RegisterUtilities.h"
+#include "lldb/Target/Thread.h"
+#include "lldb/Utility/DataExtractor.h"
+#include "lldb/Utility/RegisterValue.h"
+
+#include <memory>
+
+class RegisterContextCorePOSIX_riscv32 : public RegisterContextPOSIX_riscv32 {
+public:
+ static std::unique_ptr<RegisterContextCorePOSIX_riscv32>
+ Create(lldb_private::Thread &thread, const lldb_private::ArchSpec &arch,
+ const lldb_private::DataExtractor &gpregset,
+ llvm::ArrayRef<lldb_private::CoreNote> notes);
+
+ ~RegisterContextCorePOSIX_riscv32() override;
+
+ bool ReadRegister(const lldb_private::RegisterInfo *reg_info,
+ lldb_private::RegisterValue &value) override;
+
+ bool WriteRegister(const lldb_private::RegisterInfo *reg_info,
+ const lldb_private::RegisterValue &value) override;
+
+protected:
+ RegisterContextCorePOSIX_riscv32(
+ lldb_private::Thread &thread,
+ std::unique_ptr<RegisterInfoPOSIX_riscv32> register_info,
+ const lldb_private::DataExtractor &gpregset,
+ llvm::ArrayRef<lldb_private::CoreNote> notes);
+
+ bool ReadGPR() override;
+
+ bool ReadFPR() override;
+
+ bool WriteGPR() override;
+
+ bool WriteFPR() override;
+
+private:
+ lldb_private::DataExtractor m_gpr;
+ lldb_private::DataExtractor m_fpr;
+};
+
+#endif // LLDB_SOURCE_PLUGINS_PROCESS_ELF_CORE_REGISTERCONTEXTPOSIXCORE_RISCV32_H
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