[Lldb-commits] [lldb] [lldb][RISCV] Support optionally disabled FPR for riscv64 (PR #104547)

[David Spickett via lldb-commits]

DavidSpickett wrote:

> The main thing here - is that some RISC-V platforms might have only general-purpose and vector registers, but non of floating-point ones (e.g. for the case of targets say specifically shaped for ML/AI). 

I had not considered that. I'm used to Arm where if you want to have the new vector extensions you have to have the original FP (Neon) extension too.

Even more reason to make it all dynamic.

https://github.com/llvm/llvm-project/pull/104547