[Lldb-commits] [lldb] [lldb][RISCV] Support optionally disabled FPR (PR #104547)

[Alexey Merzlyakov via lldb-commits]

AlexeyMerzlyakov wrote:

@DavidSpickett, thank you for the review and sorry for late reply, I've just returned from the BT w/o an access to my main PC.

Yes, the way to handle the register sets is pretty similar that ARM64 is using in dynamic model (if I understand it correctly), so all further added register sets could use this as a baseline, I believe.
Regarding review comments, I'll meet them shortly.

> Can you remind me what vpr is as opposed to fpr, is that V as in Vector?

Yes, everything is all right. The main thing here - is that some RISC-V platforms might have only general-purpose and vector registers, but non of floating-point ones (e.g. for the case of targets say specifically shaped for ML/AI). For this case, VPR will be placed in totaling structure right after GPR-s. Here it is important to fill registers arrays and numbers (offsets) correctly.

> Of course it's up to @AlexeyMerzlyakov what their plans are here.

Unfortunately, I have no plans on RV32-s right now. However, the 32-bit support could be added as a set of separate plugins for this target architecture using RV64 as a reference.

https://github.com/llvm/llvm-project/pull/104547